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Fri, 30 Jan 2026 09:31:18 -0800 From: Ketan Patil To: , , CC: , , Ketan Patil Subject: [PATCH v6 3/4] memory: tegra: Add support for multiple IRQs Date: Fri, 30 Jan 2026 17:30:54 +0000 Message-ID: <20260130173055.151255-4-ketanp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260130173055.151255-1-ketanp@nvidia.com> References: <20260130173055.151255-1-ketanp@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF0000150A:EE_|DS2PR12MB9614:EE_ X-MS-Office365-Filtering-Correlation-Id: 5fe19993-3e9d-4e0c-3c82-08de60256afa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?oalGcfzPKYtn2H3VgoRT1w8pSReJIXYhTucvnt7o6/0LLOKKYEA5+26wvPTJ?= =?us-ascii?Q?BylrkeXmph8ET9NRfUJ/oGfJYU+HzvCs5+AK2BJmtB8ZcS6LPVoGrLa2zuP6?= =?us-ascii?Q?7xWwxpbkEQxiq8UBfG4HiuyVf8jn8j5Jg8xCXvm0eUFtjiBeRAYuuAN0ftPh?= =?us-ascii?Q?+GguSxPHZBMziL5rkwSF57z/s7KmEcuyfDudjXOJR7mFnXOLrIAXkr1OSU0A?= =?us-ascii?Q?214Wbp5cFu/mYb2KEC4Z3AUO0tJxr1TgbJU3FWrjsFuOb0TBGsO8B7mXG4lO?= =?us-ascii?Q?ZBDaspWQP41DyZfqujP+82jqIKtU+1F6yOGHpJ81efuUVQjCdemK9LAzID3t?= =?us-ascii?Q?dLAl2afuGSv6o+OdpBl9EewvKK2eBhNDhu9loFDfOqGzIs3dgQRE8SKva8p2?= =?us-ascii?Q?B21yG6VOoMVESrSTgUMd2HvTDdqcqEPbJgkyHJ+xYwpVaJAOa5Ccjvad5c3x?= =?us-ascii?Q?MBrfOyNBhcw8MeCPeQmMPLV5wR9zPbexgB8UP3hqRlNcDXBccYLxGXuNQ71t?= =?us-ascii?Q?Hf1vuo4GFHcf9TaKWkbRkm7yKALKtW8CxFM4A2T9uq91ocbADaOxuDIzegLU?= =?us-ascii?Q?TinCPE6T/Adup38TYa3SmbsGiXqNjkhzL6INw0n7k5J9jPuEU2KqeoME5OR8?= =?us-ascii?Q?6lEvNdW1/k20LM3XmhxYkaGeocjlP8+7HvmZdHBh7SY89o1lvUSPBOuajULx?= =?us-ascii?Q?bOSoWiP/Tw3uG9kiYu40Vjipha5VZFk7Ul4d0fj5siMtdvUuKfXvyCzMpA4K?= =?us-ascii?Q?gW4bvaeFxHbG0Cc3SxV28/tf0z7h1UysC0ULR8uPreBm6UHSh22UKVmI1+Hv?= =?us-ascii?Q?/96wbO/kieJpb1Va6wO+HOcWrQa3nM0DzIqEAI5YXziMWlJHj4dGcXC8bhH1?= =?us-ascii?Q?hTgxw8FQAFX5AEwgJ9vM0YS8XJq8h9Zt3wUth2rtls8qCk5dfZcd6z9/H5OR?= =?us-ascii?Q?bSXBXTM8QvXIItGtkZLcADql6rPiclZ+C7qxbRk0md4KQ2iNBYFYJKLJSeCU?= =?us-ascii?Q?7Zu4xd6cjWc7TPcTxzbnp7LQfWTbcQk93fm/HMpCyyjGkBcsshPn3wIGc+KQ?= =?us-ascii?Q?zTHQ7NQJaKGFNYxWs8wLG0bWUBfDjRZlk/1f+dDsvyM+50Cal9MF0mNnzXRF?= =?us-ascii?Q?Dfl70bKKm/yJ65qqtv7OKx0s/JM2WQIyCtShYDYrfeegJAYjNMSD8Q8VzXRH?= =?us-ascii?Q?jGSYjKpqqeldn+xiU0yxGTBBhok9NLXK35SiiV+tfqxZwI35m4As6DEysaMH?= =?us-ascii?Q?U9Ou7QRZ6Jlw4sCBMQQ1JxBbev1F0aoZQHtmsi4frTT4+NwscGpoiF2Y/UFj?= =?us-ascii?Q?CLHcnkk4a8wAl0ihP5yQXjJukyddmiNOBIxwhE/dwAeV0N2EeBmNjbjpBetr?= =?us-ascii?Q?lks8D7wiS9q9cgv6k3qD/rOhyhRXKWIF5B13MLJ4PuPjJgpvWd8J+oWHE1IS?= =?us-ascii?Q?lrsQIrZbd9IcQc7MNco+b6Y1NNk+AnTJK0h0m6AcuMoYywF5ywf+eIu2wiK9?= =?us-ascii?Q?05INylsiDrOdps7DKh4lry/0IBHmacja+TLcrlsPjaoVn6sFxnrjSXxF8FWM?= =?us-ascii?Q?xKHW8LfqQ+zvF9M0cRacfI34oGqulfKZy3vqG8Re84y0o824BsklM6r2UsvF?= =?us-ascii?Q?Bln6WZsGRqJ1Pxr5UfZwspQK396Z786nlHc2J5f5GDiu7epD0p3mbm6KlRFp?= =?us-ascii?Q?Sd5qyg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; 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charset="utf-8" Add support to handle multiple MC interrupts lines, as supported by Tegra264. Turn the single IRQ handler callback into a counted array to allow specifying a separate handler for each interrupt. Signed-off-by: Ketan Patil --- drivers/memory/tegra/mc.c | 34 +++++++++++++++++++++------------ drivers/memory/tegra/mc.h | 1 + drivers/memory/tegra/tegra186.c | 3 ++- drivers/memory/tegra/tegra20.c | 7 ++++++- include/soc/tegra/mc.h | 6 ++++-- 5 files changed, 35 insertions(+), 16 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 1dacbe2aba4e..49c470f7b1f7 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -398,6 +398,10 @@ unsigned int tegra_mc_get_emem_device_count(struct teg= ra_mc *mc) } EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count); =20 +const irq_handler_t tegra30_mc_irq_handlers[] =3D { + tegra30_mc_handle_irq +}; + #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ defined(CONFIG_ARCH_TEGRA_114_SOC) || \ defined(CONFIG_ARCH_TEGRA_124_SOC) || \ @@ -551,7 +555,8 @@ int tegra30_mc_probe(struct tegra_mc *mc) =20 const struct tegra_mc_ops tegra30_mc_ops =3D { .probe =3D tegra30_mc_probe, - .handle_irq =3D tegra30_mc_handle_irq, + .handle_irq =3D tegra30_mc_irq_handlers, + .num_interrupts =3D ARRAY_SIZE(tegra30_mc_irq_handlers), }; #endif =20 @@ -953,25 +958,30 @@ static int tegra_mc_probe(struct platform_device *pde= v) tegra_mc_num_channel_enabled(mc); =20 if (mc->soc->ops && mc->soc->ops->handle_irq) { - mc->irq =3D platform_get_irq(pdev, 0); - if (mc->irq < 0) - return mc->irq; + unsigned int i; =20 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); =20 + for (i =3D 0; i < mc->soc->ops->num_interrupts; i++) { + int irq; + + irq =3D platform_get_irq(pdev, i); + if (irq < 0) + return irq; + + err =3D devm_request_irq(&pdev->dev, irq, mc->soc->ops->handle_irq[i], = 0, + dev_name(&pdev->dev), mc); + if (err < 0) { + dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); + return err; + } + } + if (mc->soc->num_channels) mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask, MC_INTMASK); else mc_writel(mc, mc->soc->intmask, MC_INTMASK); - - err =3D devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, = 0, - dev_name(&pdev->dev), mc); - if (err < 0) { - dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, - err); - return err; - } } =20 if (mc->soc->reset_ops) { diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 5f816d703d81..464cf75ccadc 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -193,6 +193,7 @@ extern const struct tegra_mc_ops tegra186_mc_ops; #endif =20 irqreturn_t tegra30_mc_handle_irq(int irq, void *data); +extern const irq_handler_t tegra30_mc_irq_handlers[]; extern const char * const tegra_mc_status_names[32]; extern const char * const tegra_mc_error_names[8]; =20 diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra18= 6.c index 51e2dd628fb4..23ec433f0f92 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -174,7 +174,8 @@ const struct tegra_mc_ops tegra186_mc_ops =3D { .remove =3D tegra186_mc_remove, .resume =3D tegra186_mc_resume, .probe_device =3D tegra186_mc_probe_device, - .handle_irq =3D tegra30_mc_handle_irq, + .handle_irq =3D tegra30_mc_irq_handlers, + .num_interrupts =3D 1, }; =20 #if defined(CONFIG_ARCH_TEGRA_186_SOC) diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index 227c3336974d..794255914f2e 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -761,9 +761,14 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void= *data) return IRQ_HANDLED; } =20 +static const irq_handler_t tegra20_mc_irq_handlers[] =3D { + tegra20_mc_handle_irq +}; + static const struct tegra_mc_ops tegra20_mc_ops =3D { .probe =3D tegra20_mc_probe, - .handle_irq =3D tegra20_mc_handle_irq, + .handle_irq =3D tegra20_mc_irq_handlers, + .num_interrupts =3D ARRAY_SIZE(tegra20_mc_irq_handlers), }; =20 const struct tegra_mc_soc tegra20_mc_soc =3D { diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 372f47e824d5..89f94abfaada 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -10,10 +10,11 @@ #include #include #include +#include #include #include -#include #include +#include =20 struct clk; struct device; @@ -164,8 +165,9 @@ struct tegra_mc_ops { int (*probe)(struct tegra_mc *mc); void (*remove)(struct tegra_mc *mc); int (*resume)(struct tegra_mc *mc); - irqreturn_t (*handle_irq)(int irq, void *data); int (*probe_device)(struct tegra_mc *mc, struct device *dev); + const irq_handler_t *handle_irq; + unsigned int num_interrupts; }; =20 struct tegra_mc_regs { --=20 2.17.1