From nobody Sat Feb 7 05:01:26 2026 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012040.outbound.protection.outlook.com [40.107.209.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4F6236402F; Fri, 30 Jan 2026 17:31:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.209.40 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769794298; cv=fail; b=MXDycixDAFHdApIKE+RxrvMZ3t1Bw9LmYEdMy71J1fyDodBtbW1X4E6sv7/tdyRdq55HqIylLOcg8vxK+rQDvnRZqmd2nf6XhjilMRVL+fG/B/siWDDFZ3gwlPuJCy3kMPCUAJkzbzrS2IxPph6MF3KMhMW1SDvh+wSoFLTT3p0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769794298; c=relaxed/simple; bh=CBBwQqZxHyW+OKn9lzwHyuWtMfQCzxnA2m+TzEkhWaw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=s4q0vU2jWQkrZpkZKPefdmW7fdZHE8ObNyzfKizavKK2ux+gJGCNvB1Wy+TXcU9kmpE2BJ24yw7TyU+czPNc5ysHWmrHoFslCCbYAMdPw+N+QAimMsvuDCzj7h7rlBz5eNqT4FFgJ9MSOsNarJh/5hJEnjfPsNpRGT9LsECrIXA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=AepjnHkr; arc=fail smtp.client-ip=40.107.209.40 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="AepjnHkr" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=gKAm5VBRvzl8I2zNC+zTXY+8Ca01k9xyRsJuozLfrEwoXN3VSsgL+pvbMblVgAG37Ne60r/Y+Fh6hYdySjlaUK/WkNRgGUT2R6k22s1iDssPOLSFvs8pjMsnetSNu2ofwKqwBKX9F1jOWcFqDim1hPSZk2DP1HGtJFc9HHpDKfw5YiPtkRYHxqpywQHN2lQEQYN9FjfICQNEjBhTfpYyZlSpyrlxEANm7YFApIo0GlvP/ItTDVNq35fTrYd4M/uKZujUDpOJythTAsPjKAZV3Km6TBqpbnQVWbYPPtQVbLtVXojOuqGwKbwQ3avmS3435q8HhL3e5RHf02g/E1w9+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=q0orgAmKDcVUUwmbxpc8vaZUtOs0YpUbY+CdgUCFv4c=; b=H/DuqnRfk9VG4yx5LzQ7yXn2p0oyP0KswZoH6NIkDrGRnAdbLBDMqd3jijxZGkCl/CZXmCx+Keh35kLQoVcuJUxRFeCi8jeqXsq09T7Owl8N9WWLa4xQNSAZoEq8e5041b25/tdLijqiTQ1KelbVRxyF8ABamoqRSe2V+BJreT/Lp3a1hjpqP37WIMOMBoEI0t1kfpI3QHDX9JUNTTHBYpvN/hwvuzAstcUhy4dIXjQQbhBC6zJjKqVeTIfT9PVlownHoDDkdKz5OWC5fNOGSjh9wEQPzpKcKa5vyqtB8wYnFvSbbFAdEwIvhOuvt2wjuXN4j/xx3SrWBQnlOKsu4w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=q0orgAmKDcVUUwmbxpc8vaZUtOs0YpUbY+CdgUCFv4c=; b=AepjnHkroI0I2+Ny8tMIKoNR2N07j6Tz4KaJLUMQkhc9B+UgMwGIAL40vLS79NcQoklC9FlsbJ1Xu9vP4jlt8ktAvY5w5nxt+LcXkzOkR3DjdDPjluxRGo1qQ7EKcAmhyZI13LAI9ydTqutlTW55TIxmpcgzMhx8owdIqyxbiT9cnRMOSMneRMqT1K1RfoX+8OGCeEI4ZJ8rykDR+IOeI873JjbfyJVcMYjY4jsLiDh+6gvEklkFJLsOLlQyko1G8TXJODz4L9R9B/EMrrCbI8zzVZZzR2ga7xudNEMZAqlwY9leCBAy/QQYJyyTjaEjVNv5dPeZxYV0tpngyFLH5g== Received: from SJ0PR03CA0270.namprd03.prod.outlook.com (2603:10b6:a03:3a0::35) by MW5PR12MB5652.namprd12.prod.outlook.com (2603:10b6:303:1a0::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.7; Fri, 30 Jan 2026 17:31:25 +0000 Received: from SJ5PEPF000001E8.namprd05.prod.outlook.com (2603:10b6:a03:3a0:cafe::b4) by SJ0PR03CA0270.outlook.office365.com (2603:10b6:a03:3a0::35) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9564.12 via Frontend Transport; Fri, 30 Jan 2026 17:31:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ5PEPF000001E8.mail.protection.outlook.com (10.167.242.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Fri, 30 Jan 2026 17:31:25 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 30 Jan 2026 09:31:12 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 30 Jan 2026 09:31:12 -0800 Received: from build-ketanp-bionic-20250813.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Fri, 30 Jan 2026 09:31:12 -0800 From: Ketan Patil To: , , CC: , , Ketan Patil Subject: [PATCH v6 1/4] memory: tegra: Group error handling related registers Date: Fri, 30 Jan 2026 17:30:52 +0000 Message-ID: <20260130173055.151255-2-ketanp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260130173055.151255-1-ketanp@nvidia.com> References: <20260130173055.151255-1-ketanp@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001E8:EE_|MW5PR12MB5652:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b57efe4-9c69-4d8e-2730-08de602564fe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?wv/Zu2udgwpIocTlG+39ThldvuVHiRm7J4d16B2nmB1lf/vOFKm95vPoyNhM?= =?us-ascii?Q?kW6mF3W5NCbLbesJv3ueHCFVJceje5zT2VL41T3Hc6Q/kICL5LXAY1E3FvWO?= =?us-ascii?Q?Lkza8o9CR777q3ZV4vtjmPOtj/9ZmZkNmS3n7repltTTqhWx9w+kVGD9IBwg?= =?us-ascii?Q?fkikorxj5ttHpf4irEJiUHNyRCkTxUiqEol+qaePTNXjcwpTh+0Ih/A3O7A+?= =?us-ascii?Q?d9HX4qBCcpN24bVPYB6x764lJaa5enObkJIJaSZ2TyEo+iUf6IYMrrec8R/6?= =?us-ascii?Q?w+ADYH0JVqrSZz7+5cCrXivrDrCjIAQxEAUZKm7NzrYGIEvejn8M5m6WNwcj?= =?us-ascii?Q?H5RK8pKDSo4aoMFvhW5Qw9lY0hcNABSc9N2NwkkgMxZHeiFTxWX9RzoN1b3E?= =?us-ascii?Q?vIq/rQUJ5QzzknTknAZQVRNbltvwY9REoOvKkjookZlXvSY/1dMNCoYd3bJ9?= =?us-ascii?Q?cMGoqGAzXesNTClS4OjX0J2KZ/P4ktNmLhBfeBYBnoIG7g55gz3MDlErDP2e?= =?us-ascii?Q?0x9DgPUIe0oAaRGfUtFWB+fCoiFQQQCxJ3ggmYcmtFyWa4K9f3cV/43AtVJ9?= =?us-ascii?Q?aJSR38LgoN5UXy4SOX/VlVRbBnAnrOYKHwB2rSs9W7yX1cI2xxkbp4ymhVOG?= =?us-ascii?Q?yCc6jfAAe4BB3gtJptfXiY7l3u3duedn3iAlmlHD2z5TNwVoNWh3C5mXqaaN?= =?us-ascii?Q?GcMxcpLtjZX8o8MrU8lRkjD/zDlB2bhFmGevQ5WZPC36t2GpPIgsXN6GUwjT?= =?us-ascii?Q?u7CFMbznoohDBIxQLfbiTUfp6ZLlyJ5GO4xvZpRVkbaEgsiLhrGqXsFv91Ox?= =?us-ascii?Q?sBD60iJrswoByGV7yIYNpbD00bqQk3JALq7XcihqM1NAYeZLtVjQaIpOyd36?= =?us-ascii?Q?Qm6Iedcze7nPBPffXGSRFCdqEhwiNVcvtOUP4XqY+VURn1L19eQnF/gvkoGP?= =?us-ascii?Q?/fvvr1Q2/84biSYaHYu4WE3IxK/5Op7OZFFd2WpT9IpevjACB8IhWtBJ6K/0?= =?us-ascii?Q?XwW8gTpm1CnekJIvZ1Ccj3cp7rE1WF5OGBi2eT8qP5MdmqhY3VvUUZtFeOUq?= =?us-ascii?Q?nDrbEyLLTBTGnkD1WtyY7KhRwnugkYL34BbwS9Swigj4PNfg6V4jsLL9dqRd?= =?us-ascii?Q?ze5QgedZ4UTUEUHtQVYGDM12UX1jBFpbz6DB3Q7CaNdKjpLFPRjEkWYsG1mN?= =?us-ascii?Q?G1NbBorF2p8KC+BuZFWmx6EZuK6h8nXKbrYI8mfjtMItJwjeX0w4UhrJKQmk?= =?us-ascii?Q?pSmaYNaFf5AuOvdwXl8jAf9DhloMTlvnKkuoMR4AyUW7lYXvKy/enUZZn5zX?= =?us-ascii?Q?QPipXSgEr2FbQnLaT6CbT5+DBocYX+chDsscE8gXMI/NJVJB/ujb7WuWDsm+?= =?us-ascii?Q?bcHYTnegq60042PfUlcgch2kZ3/++Nl8NcnIGJQtSlkZ7Z9BCPe3dpTc/YyO?= =?us-ascii?Q?/lk1mwjOTFzLZxv7ejKZoOUkIbe+/jCiO+dpYP7Dzh9nFouCbfTZzb6Rn9zU?= =?us-ascii?Q?U53OqKdv21w7UKE5H5DxxqpuB6WbjN49i/Gi20eP7vlKqLKV53BBGA5HEU28?= =?us-ascii?Q?dsTqL/3r86sB5h+x86/1pH845vaF9i4FM0ZKcoqz1BtlCGa4FwLpvuoJzNkx?= =?us-ascii?Q?/NZm1FVfsPHcVsHA4dzy+ewGI0HwXyFltv7e4V6qMKpRV80XHtuLU0ISietX?= =?us-ascii?Q?xKsjjQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MIiz1n+2PeHKKt8he0zphO2SqXm25s9ePXpiMEqcJLN47y0ukm1VzT93sjKFMb4wTS2wSKcRJaNrwjKU3eD2WHgokb9v0+H/o/F6/xdl1f/t5K/vZC8if2BYi/MIjMlag/S/QJW3OPqA2nP6Ba9hLi/Vp/gyS9fr7sRv4mPbADCtbLPpuPIswxyXswHwm9ep3By2PKScmVUvfzJVaw4V6EOxNOubwZlPKO3O+L9PnY245dXSorbYlAUk2U7OqkLhe9Xs4wrErdFi91vzbSGZILV1EE+ElGxI+zrykBvGVRXB7p934gyPH9FdMGcGWlYHzh0DWe6w1/rq8pGRDNNtlFGWW2dIGfY/awLCuS6aIhLSnaLQ5f/THf8EVpVa1BOmKBEjSbk176wLxOnboz4JOaIjDRmGYu5chdssNE2sse530GdbB1rrhFf08dzmztdi X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2026 17:31:25.7391 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b57efe4-9c69-4d8e-2730-08de602564fe X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5652 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Group MC error related registers into a struct as they could have SoC specific values. Tegra264 has different register offsets than the existing devices and so in order to add support for Tegra264 we need to first make this change. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- drivers/memory/tegra/mc.c | 47 ++++++++++++++++++++++----------- drivers/memory/tegra/mc.h | 16 +---------- drivers/memory/tegra/tegra114.c | 3 ++- drivers/memory/tegra/tegra124.c | 4 ++- drivers/memory/tegra/tegra186.c | 3 ++- drivers/memory/tegra/tegra194.c | 3 ++- drivers/memory/tegra/tegra20.c | 3 ++- drivers/memory/tegra/tegra210.c | 3 ++- drivers/memory/tegra/tegra234.c | 3 ++- drivers/memory/tegra/tegra30.c | 3 ++- include/soc/tegra/mc.h | 22 ++++++++++++++- 11 files changed, 71 insertions(+), 39 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 6edb210287dc..1dacbe2aba4e 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -56,6 +56,23 @@ static const struct of_device_id tegra_mc_of_match[] =3D= { }; MODULE_DEVICE_TABLE(of, tegra_mc_of_match); =20 +const struct tegra_mc_regs tegra20_mc_regs =3D { + .cfg_channel_enable =3D 0xdf8, + .err_status =3D 0x08, + .err_add =3D 0x0c, + .err_add_hi =3D 0x11fc, + .err_vpr_status =3D 0x654, + .err_vpr_add =3D 0x658, + .err_sec_status =3D 0x67c, + .err_sec_add =3D 0x680, + .err_mts_status =3D 0x9b0, + .err_mts_add =3D 0x9b4, + .err_gen_co_status =3D 0xc00, + .err_gen_co_add =3D 0xc04, + .err_route_status =3D 0x9c0, + .err_route_add =3D 0x9c4, +}; + static void tegra_mc_devm_action_put_device(void *data) { struct tegra_mc *mc =3D data; @@ -600,37 +617,37 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data) =20 switch (intmask) { case MC_INT_DECERR_VPR: - status_reg =3D MC_ERR_VPR_STATUS; - addr_reg =3D MC_ERR_VPR_ADR; + status_reg =3D mc->soc->regs->err_vpr_status; + addr_reg =3D mc->soc->regs->err_vpr_add; break; =20 case MC_INT_SECERR_SEC: - status_reg =3D MC_ERR_SEC_STATUS; - addr_reg =3D MC_ERR_SEC_ADR; + status_reg =3D mc->soc->regs->err_sec_status; + addr_reg =3D mc->soc->regs->err_sec_add; break; =20 case MC_INT_DECERR_MTS: - status_reg =3D MC_ERR_MTS_STATUS; - addr_reg =3D MC_ERR_MTS_ADR; + status_reg =3D mc->soc->regs->err_mts_status; + addr_reg =3D mc->soc->regs->err_mts_add; break; =20 case MC_INT_DECERR_GENERALIZED_CARVEOUT: - status_reg =3D MC_ERR_GENERALIZED_CARVEOUT_STATUS; - addr_reg =3D MC_ERR_GENERALIZED_CARVEOUT_ADR; + status_reg =3D mc->soc->regs->err_gen_co_status; + addr_reg =3D mc->soc->regs->err_gen_co_add; break; =20 case MC_INT_DECERR_ROUTE_SANITY: - status_reg =3D MC_ERR_ROUTE_SANITY_STATUS; - addr_reg =3D MC_ERR_ROUTE_SANITY_ADR; + status_reg =3D mc->soc->regs->err_route_status; + addr_reg =3D mc->soc->regs->err_route_add; break; =20 default: - status_reg =3D MC_ERR_STATUS; - addr_reg =3D MC_ERR_ADR; + status_reg =3D mc->soc->regs->err_status; + addr_reg =3D mc->soc->regs->err_add; =20 #ifdef CONFIG_PHYS_ADDR_T_64BIT if (mc->soc->has_addr_hi_reg) - addr_hi_reg =3D MC_ERR_ADR_HI; + addr_hi_reg =3D mc->soc->regs->err_add_hi; #endif break; } @@ -883,7 +900,7 @@ static void tegra_mc_num_channel_enabled(struct tegra_m= c *mc) unsigned int i; u32 value; =20 - value =3D mc_ch_readl(mc, 0, MC_EMEM_ADR_CFG_CHANNEL_ENABLE); + value =3D mc_ch_readl(mc, 0, mc->soc->regs->cfg_channel_enable); if (value <=3D 0) { mc->num_channels =3D mc->soc->num_channels; return; diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 1d97cf4d3a94..bbe3e2690c64 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved. */ =20 #ifndef MEMORY_TEGRA_MC_H @@ -14,8 +14,6 @@ =20 #define MC_INTSTATUS 0x00 #define MC_INTMASK 0x04 -#define MC_ERR_STATUS 0x08 -#define MC_ERR_ADR 0x0c #define MC_GART_ERROR_REQ 0x30 #define MC_EMEM_ADR_CFG 0x54 #define MC_DECERR_EMEM_OTHERS_STATUS 0x58 @@ -43,19 +41,7 @@ #define MC_EMEM_ARB_OVERRIDE 0xe8 #define MC_TIMING_CONTROL_DBG 0xf8 #define MC_TIMING_CONTROL 0xfc -#define MC_ERR_VPR_STATUS 0x654 -#define MC_ERR_VPR_ADR 0x658 -#define MC_ERR_SEC_STATUS 0x67c -#define MC_ERR_SEC_ADR 0x680 -#define MC_ERR_MTS_STATUS 0x9b0 -#define MC_ERR_MTS_ADR 0x9b4 -#define MC_ERR_ROUTE_SANITY_STATUS 0x9c0 -#define MC_ERR_ROUTE_SANITY_ADR 0x9c4 -#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 -#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 -#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0xdf8 #define MC_GLOBAL_INTSTATUS 0xf24 -#define MC_ERR_ADR_HI 0x11fc =20 #define MC_INT_DECERR_ROUTE_SANITY BIT(20) #define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17) diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra11= 4.c index 41350570c815..ea7e4c7bb5f8 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -1114,4 +1114,5 @@ const struct tegra_mc_soc tegra114_mc_soc =3D { .resets =3D tegra114_mc_resets, .num_resets =3D ARRAY_SIZE(tegra114_mc_resets), .ops =3D &tegra30_mc_ops, + .regs =3D &tegra20_mc_regs, }; diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra12= 4.c index 9d7393e19f12..c5529f79fbb4 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -1275,6 +1275,7 @@ const struct tegra_mc_soc tegra124_mc_soc =3D { .num_resets =3D ARRAY_SIZE(tegra124_mc_resets), .icc_ops =3D &tegra124_mc_icc_ops, .ops =3D &tegra30_mc_ops, + .regs =3D &tegra20_mc_regs, }; #endif /* CONFIG_ARCH_TEGRA_124_SOC */ =20 @@ -1307,5 +1308,6 @@ const struct tegra_mc_soc tegra132_mc_soc =3D { .num_resets =3D ARRAY_SIZE(tegra124_mc_resets), .icc_ops =3D &tegra124_mc_icc_ops, .ops =3D &tegra30_mc_ops, + .regs =3D &tegra20_mc_regs, }; #endif /* CONFIG_ARCH_TEGRA_132_SOC */ diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra18= 6.c index aee11457bf8e..51e2dd628fb4 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2017-2025 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2017-2026 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -914,5 +914,6 @@ const struct tegra_mc_soc tegra186_mc_soc =3D { .ops =3D &tegra186_mc_ops, .ch_intmask =3D 0x0000000f, .global_intstatus_channel_shift =3D 0, + .regs =3D &tegra20_mc_regs, }; #endif diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra19= 4.c index 26035ac3a1eb..5b7ff2dd6812 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2017-2026 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -1358,4 +1358,5 @@ const struct tegra_mc_soc tegra194_mc_soc =3D { .icc_ops =3D &tegra_mc_icc_ops, .ch_intmask =3D 0x00000f00, .global_intstatus_channel_shift =3D 8, + .regs =3D &tegra20_mc_regs, }; diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index a3022e715dee..227c3336974d 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2012-2026 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -778,4 +778,5 @@ const struct tegra_mc_soc tegra20_mc_soc =3D { .num_resets =3D ARRAY_SIZE(tegra20_mc_resets), .icc_ops =3D &tegra20_mc_icc_ops, .ops =3D &tegra20_mc_ops, + .regs =3D &tegra20_mc_regs, }; diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra21= 0.c index 3c2949c16fde..e166b33848e9 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2015-2026 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -1287,4 +1287,5 @@ const struct tegra_mc_soc tegra210_mc_soc =3D { .resets =3D tegra210_mc_resets, .num_resets =3D ARRAY_SIZE(tegra210_mc_resets), .ops =3D &tegra30_mc_ops, + .regs =3D &tegra20_mc_regs, }; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index 5f57cea48b62..512d054d7592 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2022-2023, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2022-2026, NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -1152,4 +1152,5 @@ const struct tegra_mc_soc tegra234_mc_soc =3D { * supported. */ .num_carveouts =3D 32, + .regs =3D &tegra20_mc_regs, }; diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index d3e685c8431f..3f3c7d996b49 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -1400,4 +1400,5 @@ const struct tegra_mc_soc tegra30_mc_soc =3D { .num_resets =3D ARRAY_SIZE(tegra30_mc_resets), .icc_ops =3D &tegra30_mc_icc_ops, .ops =3D &tegra30_mc_ops, + .regs =3D &tegra20_mc_regs, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 6ee4c59db620..372f47e824d5 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (C) 2014 NVIDIA Corporation + * Copyright (C) 2014-2026 NVIDIA Corporation */ =20 #ifndef __SOC_TEGRA_MC_H__ @@ -168,6 +168,23 @@ struct tegra_mc_ops { int (*probe_device)(struct tegra_mc *mc, struct device *dev); }; =20 +struct tegra_mc_regs { + unsigned int cfg_channel_enable; + unsigned int err_status; + unsigned int err_add; + unsigned int err_add_hi; + unsigned int err_vpr_status; + unsigned int err_vpr_add; + unsigned int err_sec_status; + unsigned int err_sec_add; + unsigned int err_mts_status; + unsigned int err_mts_add; + unsigned int err_gen_co_status; + unsigned int err_gen_co_add; + unsigned int err_route_status; + unsigned int err_route_add; +}; + struct tegra_mc_soc { const struct tegra_mc_client *clients; unsigned int num_clients; @@ -196,6 +213,7 @@ struct tegra_mc_soc { =20 const struct tegra_mc_icc_ops *icc_ops; const struct tegra_mc_ops *ops; + const struct tegra_mc_regs *regs; }; =20 struct tegra_mc { @@ -256,4 +274,6 @@ tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigne= d int id, } #endif =20 +extern const struct tegra_mc_regs tegra20_mc_regs; + #endif /* __SOC_TEGRA_MC_H__ */ --=20 2.17.1 From nobody Sat Feb 7 05:01:26 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011060.outbound.protection.outlook.com [40.93.194.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E19D4364040; Fri, 30 Jan 2026 17:31:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.194.60 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769794301; cv=fail; b=qmzButK1TvAKRaH5HB3BFpiWxjM0KMu534KIfzp3SXTjFYUHoMoEk2h8b0yM3tB8hyoL6cIrfpZ94MHwyrTpKX0rqZvXgxW6YOGnQ+beqCfHqJMc452vBKiJNcdonZ+h3C6eEEVdbt7B/vFxlkQG2wrGS/Q617pXmTneCnexsk4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769794301; c=relaxed/simple; bh=JBHft8+p8NIU0Wy8BZccOino7AAx3XQ8uXpnWACqypA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Rav1oInLMFiOHMbXrMEg3fd/TFAJDgsm0S0Fr6rVPdhWh9gjEGpPdo1IueaOWuaxuA8fMcthXDh9aFZ7D2eotiqa+er3PEHKoIyge5GABppsZGCeMZRBjMvhLDxAEiyoRI3BTim/vtpsYjFDZG3KeVTdVKNxnSDZmetCzh1E7ss= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=acOpvVUo; arc=fail smtp.client-ip=40.93.194.60 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="acOpvVUo" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Csq4aRzQeEpwzYBxHqTU4juh9gJrILIwwD/4ld5EX4O57VG4ANmNMzdWelYbv8KHpuFRyn7uYgN9PS6cnb523zbveAgVHvDiAq0vT8hdFxj5Q+ykpSloH+NHyoNI2JG6iSZpj4mPJau0mv+h0JvZKhGvzZGrSbIqkXWOGhXI6Mf8yOjhvmbPWiyG+mb+khuvDelSSccBdcJdVsIrZSiC6yA0G5zifhcHc+MX8Y0KSCT76gOZ+Pkk/2Ua4KNxSBujWvUKa4FwCr6ikno00WgZBLbEuz3Es1ho0UwgufUCUs71VODlRcvM8k3Oixk/oykvK5loB3TCGhrRh98j3GUehw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qThP87H3FJ7t4Bm1czLg0Vbh//Zr+WTwyGBBuQmTeDs=; b=VX7AYqOg7EtmU8llcbQobFeh8dm/di/101aFmDr6xWsvCgVqSqRxRBVWD2LH2WmCaHh/l5Acy9fbOR0UMECa5uZGD1/H/b0EMAuB2YOdGwbayaftTnCQK8OkS1+NdmnZZXV8j8GwhWIJoyYPjiBTRS5a85ZVT46KYRoEmNlhFnoFnIICiyf0I6Cbl8NE2xaO0KVi3TShcikoMxwuo1QczdzwI+PC7LLBSvQu4zA6K/21IhlNG+cKjHl7Paiuo5Qvuzw/Ea4nogC+o53EKMvSAW08BYd+SLYhYeHoE6IqO6g1ZAKV1fav+z+WYltqOt2eW3G0RpVdhkUl5sfR4JXD0g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qThP87H3FJ7t4Bm1czLg0Vbh//Zr+WTwyGBBuQmTeDs=; b=acOpvVUou/FAH3PqySH+JmN0i+jJsOhFgszpuCxvBBPDAR7IKTPjc2cSqRcczQXKfo/HHNlKYo/dvpAp/rBUysfGwaPj+sp4TMyhr75SGO8Tv4fDQsBcsbcWq+S81/HVkzO6b7G3sxgvtmyu7j7lbf27UlW4VZaLoisY4/98XXeYh4iLkiVMEAzUwOtYGbdx+Aoun/nVmAttdW09Vr+v0d3wpBIIJqGjWPLhbSFKszwha3U8PQUAQv+a5KIIZAgITpIQzhQLh9hZDnA2GTb7p4HpEsYi+sxWfytTc+M1wEKaW5EzMYl6b+OAphTis8CQkCsi98zF22BdfW1yh9jkLQ== Received: from SA1P222CA0196.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:3c4::23) by SA1PR12MB6751.namprd12.prod.outlook.com (2603:10b6:806:258::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.8; Fri, 30 Jan 2026 17:31:33 +0000 Received: from SA2PEPF00001508.namprd04.prod.outlook.com (2603:10b6:806:3c4:cafe::15) by SA1P222CA0196.outlook.office365.com (2603:10b6:806:3c4::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9564.13 via Frontend Transport; Fri, 30 Jan 2026 17:31:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SA2PEPF00001508.mail.protection.outlook.com (10.167.242.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Fri, 30 Jan 2026 17:31:33 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 30 Jan 2026 09:31:16 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 30 Jan 2026 09:31:16 -0800 Received: from build-ketanp-bionic-20250813.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Fri, 30 Jan 2026 09:31:16 -0800 From: Ketan Patil To: , , CC: , , Ketan Patil Subject: [PATCH v6 2/4] memory: tegra: Group register and fields Date: Fri, 30 Jan 2026 17:30:53 +0000 Message-ID: <20260130173055.151255-3-ketanp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260130173055.151255-1-ketanp@nvidia.com> References: <20260130173055.151255-1-ketanp@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001508:EE_|SA1PR12MB6751:EE_ X-MS-Office365-Filtering-Correlation-Id: 00d1aed6-1e65-49ce-bb42-08de602569c3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?xboJXkhibHSZVqRcO4C+4zRmOzutnh6YwWMSEqL49G6m0GZNzn28GbGQWhsj?= =?us-ascii?Q?jXyjbCudm+h0rkf4ovyuWEjPsKmjjku9B3mQJWkzZ9sIHW9API0sx7fUpfip?= =?us-ascii?Q?EA4ym+2QR7uqsXViLppJJ1lv0BjUCj9TN8WWhpX6AFW1ImXKgFU0K98EKI7y?= =?us-ascii?Q?uzWlACXQgVww7Txvy15e7Ec147iL3v2DL9i0oSE1Rcg670SGuALyY52Bqrxh?= =?us-ascii?Q?RYfOC8n5slRLyJoMUL9xxuy1ICcmPWBgCACXQmwmBqDcZ1+GKhLTI1Ry4HAy?= =?us-ascii?Q?tvttM9AgQceHAFzouN30xhgm4GKOjDAveNI0izmeCBT/lJBNZdvuUOljolmf?= =?us-ascii?Q?o7J37TSj0sMTm/YCdtyQr+nIiH0ZmHPJFvBsmOeJYGQyDsgfnZxDDuK0dTvp?= =?us-ascii?Q?z2KLNqXD3smJoH2nJdnco7+tG/RAp9OYOQgImacZlaK1GoloVefk1o/acqOG?= =?us-ascii?Q?Fq4eoWzoGO1j34mUasTRI4kVFQZw0nkC2zcPZtnZYOBP6GKiREI8ETguMU9l?= =?us-ascii?Q?yK977OFtSH0t3NDsFHMZ/FqSKUGr9z8Vh/WJM/uP4AKXtL3F2t+SiQBoCalt?= =?us-ascii?Q?80+kkph7nMQrTCj3h/aJVfn4+N2J7gnpuCbKkT5d7dAUuLh4fueTVSje6tJc?= =?us-ascii?Q?YtHbGWbrLFKJA9pEKQdAdl8rOliOGuxTWdEeU4ZuXUjUyeblW0a3LTO5srHA?= =?us-ascii?Q?9bjoX977lxjQnFMg0ui4H/C8bDgdljYRLvmUsYe8k+WWZBhZ7Lmn6wJy2DYF?= =?us-ascii?Q?ZeeXU0Wncf8hd5go/9hDjUpSxebvKd/I2rgqhYZ2GOciy/b+L3PSp126Fo7f?= =?us-ascii?Q?ZucsA/2w97IQXFdOv/s+q79K3Q5nvGVZz9Lz8m760e6BCFYBkcz+9VYJ3g3b?= =?us-ascii?Q?p/MzKXKo9xlaQcERmB9Fx3QzCjVaCUFjeoVY7x+PfmUp4kFfJ2CAjST+osSE?= =?us-ascii?Q?WB3iiGST7SNfjHSqb0T9qap93Bc8YH+CPm08CTbyt7q27p+qIYSj/RBO9qth?= =?us-ascii?Q?3pioh9Vvbj4ZiSk+W5rTXgq20TEc2fnXee9zXLafn4leM8PoMeqI9JK4sHWx?= =?us-ascii?Q?7xyxseKnuB2bIjD1AtGPxpdCaCadggs6tM+Dcqb6P95rqU/f0nkHo1BPTpqd?= =?us-ascii?Q?M6BKYnhbIO9kHH3DJW3nOkAk4tGl4IZpWJvlh9rrzsyI5ILwGNCDDxOAzrWK?= =?us-ascii?Q?BH73Vrsdt7gJ7KsAkQrhID8BG2Ykjb7l40rYG/y0fT0SS9syHvyejNZFl2Go?= =?us-ascii?Q?ZFG+qp7cy3JnzfBfOBx+jS/VCNZ8qgoAv6gBlUB4sWKAuoC7ABgzhxtt4RfD?= =?us-ascii?Q?Pb0k2dT0IY93H3T43vkY0aLMMbGOdxbkwrBNANdSUExDOEG2E1hzv7VH64rO?= =?us-ascii?Q?i341oOEHfJu+OoNRd0zGnS3GY20NoVEJqFfFV8TjIeGftW5LJcUz5fV2xjn3?= =?us-ascii?Q?SS8TONtV4AzRDICbU6L+UvU30gMguVuKO1KiCZBobKGXXdxz6jSIXiEnj0bd?= =?us-ascii?Q?wX2cnHDOZbhaI4hxHqNNHYg2oOJ7062AcA2ymvvhtdRJbfWpTDyhdlXFzxg+?= =?us-ascii?Q?s3eJspfSJ+DY6qvTSb2F6IAeGzsd8dfMSfX1MDwvx4dtlAyN6XRd5U8MUIgd?= =?us-ascii?Q?TVl9HCbVicWAAl5VohA0/2fKkFm3Rvd/zyIDYMNKZuoKEcoIz6e5H++Bw43E?= =?us-ascii?Q?uFJocA=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 95TXtFR+OSNdQpHJVHIhM8gUYtuGqwfBHHKe12WScAx2QKZF0t51M7DFAtzfPaS4sZHBQoKagPegtMs4ArpNuUDDlfhHeB4vILQEwtkDJd/HfQmA61oG56StNR2pT49pWgq1QjoP2vvFt9n4uEf/+OPXABDe+Eqjaw4nOdaaQa6sbR5WDmKoSZP1fNB4j/OAaXRrqhgZAQALUD6sKEq2Egb4I2RW1MouGiOFdPiW5nU6cHXDNRrt/NedA6ut9Ioj45IE+aD8lXNo0ctrOvR7FYAorfKCaRQ2ifzW5hLw7WpP0klgwzAwCIuscKr23wCiSM51ZYkH6Kr9SBTQMdxqmAqDDGIZquZe7XB9sMlrH6+Rzo3BPHiOM9Lz50sAdwVJiFVmKoB534SDLfX2wrJ8LtjmqFTBBMmMhaEhMgM8cHsj+f54npkly6W7UM3j6mIt X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2026 17:31:33.6384 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 00d1aed6-1e65-49ce-bb42-08de602569c3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001508.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6751 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current register definitions are not in sorted order. Sort these registers according to their address. Put bit fields and masks of the corresponding registers below the register definitions to clearly identify which fields belongs to which registers. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- drivers/memory/tegra/mc.h | 62 +++++++++++++++++++++------------------ 1 file changed, 33 insertions(+), 29 deletions(-) diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index bbe3e2690c64..5f816d703d81 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -13,13 +13,35 @@ #include =20 #define MC_INTSTATUS 0x00 +/* Bit field of MC_INTSTATUS register */ +#define MC_INT_DECERR_EMEM BIT(6) +#define MC_INT_INVALID_GART_PAGE BIT(7) +#define MC_INT_SECURITY_VIOLATION BIT(8) +#define MC_INT_ARBITRATION_EMEM BIT(9) +#define MC_INT_INVALID_SMMU_PAGE BIT(10) +#define MC_INT_INVALID_APB_ASID_UPDATE BIT(11) +#define MC_INT_DECERR_VPR BIT(12) +#define MC_INT_SECERR_SEC BIT(13) +#define MC_INT_DECERR_MTS BIT(16) +#define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17) +#define MC_INT_DECERR_ROUTE_SANITY BIT(20) + #define MC_INTMASK 0x04 #define MC_GART_ERROR_REQ 0x30 #define MC_EMEM_ADR_CFG 0x54 +#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) + #define MC_DECERR_EMEM_OTHERS_STATUS 0x58 #define MC_SECURITY_VIOLATION_STATUS 0x74 #define MC_EMEM_ARB_CFG 0x90 +#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) ((x) & 0x1ff) +#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff + #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 +#define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30) +#define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31) +#define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff + #define MC_EMEM_ARB_TIMING_RCD 0x98 #define MC_EMEM_ARB_TIMING_RP 0x9c #define MC_EMEM_ARB_TIMING_RC 0xa0 @@ -39,45 +61,27 @@ #define MC_EMEM_ARB_MISC1 0xdc #define MC_EMEM_ARB_RING1_THROTTLE 0xe0 #define MC_EMEM_ARB_OVERRIDE 0xe8 +#define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3 + #define MC_TIMING_CONTROL_DBG 0xf8 #define MC_TIMING_CONTROL 0xfc +#define MC_TIMING_UPDATE BIT(0) + #define MC_GLOBAL_INTSTATUS 0xf24 =20 -#define MC_INT_DECERR_ROUTE_SANITY BIT(20) -#define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17) -#define MC_INT_DECERR_MTS BIT(16) -#define MC_INT_SECERR_SEC BIT(13) -#define MC_INT_DECERR_VPR BIT(12) -#define MC_INT_INVALID_APB_ASID_UPDATE BIT(11) -#define MC_INT_INVALID_SMMU_PAGE BIT(10) -#define MC_INT_ARBITRATION_EMEM BIT(9) -#define MC_INT_SECURITY_VIOLATION BIT(8) -#define MC_INT_INVALID_GART_PAGE BIT(7) -#define MC_INT_DECERR_EMEM BIT(6) +/* Bit field of MC_ERR_STATUS_0 register */ +#define MC_ERR_STATUS_RW BIT(16) +#define MC_ERR_STATUS_SECURITY BIT(17) +#define MC_ERR_STATUS_NONSECURE BIT(25) +#define MC_ERR_STATUS_WRITABLE BIT(26) +#define MC_ERR_STATUS_READABLE BIT(27) =20 #define MC_ERR_STATUS_TYPE_SHIFT 28 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (0x6 << 28) #define MC_ERR_STATUS_TYPE_MASK (0x7 << 28) -#define MC_ERR_STATUS_READABLE BIT(27) -#define MC_ERR_STATUS_WRITABLE BIT(26) -#define MC_ERR_STATUS_NONSECURE BIT(25) + #define MC_ERR_STATUS_ADR_HI_SHIFT 20 #define MC_ERR_STATUS_ADR_HI_MASK 0x3 -#define MC_ERR_STATUS_SECURITY BIT(17) -#define MC_ERR_STATUS_RW BIT(16) - -#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) - -#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) ((x) & 0x1ff) -#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff - -#define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff -#define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30) -#define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31) - -#define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3 - -#define MC_TIMING_UPDATE BIT(0) =20 #define MC_BROADCAST_CHANNEL ~0 =20 --=20 2.17.1 From nobody Sat Feb 7 05:01:26 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010018.outbound.protection.outlook.com [52.101.193.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A72BB3644D1; Fri, 30 Jan 2026 17:31:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.193.18 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769794303; cv=fail; b=rLGd+Tb3eMoPYjdh2o7sOVNRgHYEKIymAg8JkQpWUHCMfS2FJwGVoXsmAxu5gFGGblQEn7hbOJEX+Dr5ODlhAV8j84f1NXuQJwgKIlAO/nKcDCpS+rs5c9oXWFvPt1UZyU5ht2P8hAJQlJqVXLpNZM51CbYDxD+KGJ2WtQEeAb4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769794303; c=relaxed/simple; bh=tOQiR992wMNl8OOu5U6Q/Q0VWeYktcEV8ahANf02u/k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kKy926ydn8/N/98mWUI249XFYIkIutmBDHGkXIh6R+EL7+qB4M0171GLRkcRDJDSkNvn4lh2jDxpa8YAZGL6zOXYepngNJpbC7DWft4nKxgpXcthr8q+2MBPaDro3yt6qc7h1qRaYEMKeVBsiUR4h3s3W7oJ72Z6Zn1zI37E+kc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=QYwpk+fS; arc=fail smtp.client-ip=52.101.193.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="QYwpk+fS" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=QL/HY/k1wKkUL6n/r3jiwBiFFEIHUHroYblnFm5ZHjeQ/keSFBKUZUX6Jn7JnzUueXc+94iNKzOkSaFAdhI7307r42rMDJXhfx+3XX2sjvtZ3JYp2iXmzhJ6fd3OA+FQMy5qow0fsL47uOIvoPwsPuuW3c+FW4Eur1gWycbEE0ilyl0XDLDp9BoWkJsTUB6gKeh02OFFjUqpuE43eabLhzZ18T3ho4yCAeQZYotdlnRMhtyXn2PDa7yqi2/ktme2XM3TABj/CHF5c7p8KITQTJ0SN/cAiJV9QSxUtLAs4VAcqsaKbCt33HwNICl5sV/TNjfmWgNeXv/28CkagV+9Xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=BeY5L0XjHXFxwDiI3iQhXBBwvU3JRt2MedP5gikfN7Q=; b=l9h2NoVm55rA2VKzipWI3aJGOymp+UW+mqZK8/5cz1EZCIGLgxCMg8Vb8z8EDH1K/3XH5RVvBQJfz9NOxQ/mydN00mKMxEhBaQL1d1pvw+7BPmfvf+MKxyxlsvLyP/OP0eptVgu1zH0xw+59PEP6AcZ5WOXTq+id7NAqsf09zBNs6jIZocW4TeZNGmpk1+g6mnKn9Roie5koskhbNWz46waTfxJhoJKRYszdYOb9jursMMuWxbye0pVt1Mfknhwd8d1q4+sxJVPQGehRjboqr7TWalGqpxIxsGGQLXm+X482dFicydzeShAGQTGtozgo4r8mKMGob5pgSG9m85tC+A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BeY5L0XjHXFxwDiI3iQhXBBwvU3JRt2MedP5gikfN7Q=; b=QYwpk+fS1JLZ3zqLeoENsXfr2gq5NhBog6xNXekVMMn4Octx0J0/RAi09VVcIlvTHgV9wpg2EScbx542kd7YUSjXWq7vaHHitCc5IUmiH7gdo0F+ZdFNBCNYT3cZbdOVu+lA6i1ga69EgS3fD7X1F3+GhsdpWC+Q7nxzUokdVzEPc+w+3qkdmYR/wY4uSXUPg1wERZ8a9hYDxQ0U2IRZca2kEumjRS/HZyQQTXHeOY7jZiCwbtB10org8DwvztF20cM6vRti/7Q1wBlyXbJXRgDoJEPYYtr1AYo5nZ6xNCA8inAp9AF1cjA2O1nmpz5dUuhHGmmlaxWyqqIAXpsqvw== Received: from SA0PR12CA0023.namprd12.prod.outlook.com (2603:10b6:806:6f::28) by DS2PR12MB9614.namprd12.prod.outlook.com (2603:10b6:8:276::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.8; Fri, 30 Jan 2026 17:31:35 +0000 Received: from SA2PEPF0000150A.namprd04.prod.outlook.com (2603:10b6:806:6f:cafe::a3) by SA0PR12CA0023.outlook.office365.com (2603:10b6:806:6f::28) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9564.11 via Frontend Transport; Fri, 30 Jan 2026 17:31:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SA2PEPF0000150A.mail.protection.outlook.com (10.167.242.42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Fri, 30 Jan 2026 17:31:35 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 30 Jan 2026 09:31:19 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 30 Jan 2026 09:31:18 -0800 Received: from build-ketanp-bionic-20250813.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Fri, 30 Jan 2026 09:31:18 -0800 From: Ketan Patil To: , , CC: , , Ketan Patil Subject: [PATCH v6 3/4] memory: tegra: Add support for multiple IRQs Date: Fri, 30 Jan 2026 17:30:54 +0000 Message-ID: <20260130173055.151255-4-ketanp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260130173055.151255-1-ketanp@nvidia.com> References: <20260130173055.151255-1-ketanp@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF0000150A:EE_|DS2PR12MB9614:EE_ X-MS-Office365-Filtering-Correlation-Id: 5fe19993-3e9d-4e0c-3c82-08de60256afa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?oalGcfzPKYtn2H3VgoRT1w8pSReJIXYhTucvnt7o6/0LLOKKYEA5+26wvPTJ?= =?us-ascii?Q?BylrkeXmph8ET9NRfUJ/oGfJYU+HzvCs5+AK2BJmtB8ZcS6LPVoGrLa2zuP6?= =?us-ascii?Q?7xWwxpbkEQxiq8UBfG4HiuyVf8jn8j5Jg8xCXvm0eUFtjiBeRAYuuAN0ftPh?= =?us-ascii?Q?+GguSxPHZBMziL5rkwSF57z/s7KmEcuyfDudjXOJR7mFnXOLrIAXkr1OSU0A?= =?us-ascii?Q?214Wbp5cFu/mYb2KEC4Z3AUO0tJxr1TgbJU3FWrjsFuOb0TBGsO8B7mXG4lO?= =?us-ascii?Q?ZBDaspWQP41DyZfqujP+82jqIKtU+1F6yOGHpJ81efuUVQjCdemK9LAzID3t?= =?us-ascii?Q?dLAl2afuGSv6o+OdpBl9EewvKK2eBhNDhu9loFDfOqGzIs3dgQRE8SKva8p2?= =?us-ascii?Q?B21yG6VOoMVESrSTgUMd2HvTDdqcqEPbJgkyHJ+xYwpVaJAOa5Ccjvad5c3x?= =?us-ascii?Q?MBrfOyNBhcw8MeCPeQmMPLV5wR9zPbexgB8UP3hqRlNcDXBccYLxGXuNQ71t?= =?us-ascii?Q?Hf1vuo4GFHcf9TaKWkbRkm7yKALKtW8CxFM4A2T9uq91ocbADaOxuDIzegLU?= =?us-ascii?Q?TinCPE6T/Adup38TYa3SmbsGiXqNjkhzL6INw0n7k5J9jPuEU2KqeoME5OR8?= =?us-ascii?Q?6lEvNdW1/k20LM3XmhxYkaGeocjlP8+7HvmZdHBh7SY89o1lvUSPBOuajULx?= =?us-ascii?Q?bOSoWiP/Tw3uG9kiYu40Vjipha5VZFk7Ul4d0fj5siMtdvUuKfXvyCzMpA4K?= =?us-ascii?Q?gW4bvaeFxHbG0Cc3SxV28/tf0z7h1UysC0ULR8uPreBm6UHSh22UKVmI1+Hv?= =?us-ascii?Q?/96wbO/kieJpb1Va6wO+HOcWrQa3nM0DzIqEAI5YXziMWlJHj4dGcXC8bhH1?= =?us-ascii?Q?hTgxw8FQAFX5AEwgJ9vM0YS8XJq8h9Zt3wUth2rtls8qCk5dfZcd6z9/H5OR?= =?us-ascii?Q?bSXBXTM8QvXIItGtkZLcADql6rPiclZ+C7qxbRk0md4KQ2iNBYFYJKLJSeCU?= =?us-ascii?Q?7Zu4xd6cjWc7TPcTxzbnp7LQfWTbcQk93fm/HMpCyyjGkBcsshPn3wIGc+KQ?= =?us-ascii?Q?zTHQ7NQJaKGFNYxWs8wLG0bWUBfDjRZlk/1f+dDsvyM+50Cal9MF0mNnzXRF?= =?us-ascii?Q?Dfl70bKKm/yJ65qqtv7OKx0s/JM2WQIyCtShYDYrfeegJAYjNMSD8Q8VzXRH?= =?us-ascii?Q?jGSYjKpqqeldn+xiU0yxGTBBhok9NLXK35SiiV+tfqxZwI35m4As6DEysaMH?= =?us-ascii?Q?U9Ou7QRZ6Jlw4sCBMQQ1JxBbev1F0aoZQHtmsi4frTT4+NwscGpoiF2Y/UFj?= =?us-ascii?Q?CLHcnkk4a8wAl0ihP5yQXjJukyddmiNOBIxwhE/dwAeV0N2EeBmNjbjpBetr?= =?us-ascii?Q?lks8D7wiS9q9cgv6k3qD/rOhyhRXKWIF5B13MLJ4PuPjJgpvWd8J+oWHE1IS?= =?us-ascii?Q?lrsQIrZbd9IcQc7MNco+b6Y1NNk+AnTJK0h0m6AcuMoYywF5ywf+eIu2wiK9?= =?us-ascii?Q?05INylsiDrOdps7DKh4lry/0IBHmacja+TLcrlsPjaoVn6sFxnrjSXxF8FWM?= =?us-ascii?Q?xKHW8LfqQ+zvF9M0cRacfI34oGqulfKZy3vqG8Re84y0o824BsklM6r2UsvF?= =?us-ascii?Q?Bln6WZsGRqJ1Pxr5UfZwspQK396Z786nlHc2J5f5GDiu7epD0p3mbm6KlRFp?= =?us-ascii?Q?Sd5qyg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2uyPfsKvPszGSK+qAkr70naoahpEDExRhoV4/URwPlbaa/GyyQ71TWFi/mTwOtEYSWI5/MIKsHrPfDvC5fREhGoxZEYPYK5y2zCg5LgJS2494fGK2+1EYcDpQKMa7oeua8zhDu0EQ0/3m9dipw/gui6CP8bcDfAnWdlwmegMMZLgCug89CjQAq4vnUP1HbsNUWyXQnEu8XlMYVUlDcfFHDR0sMEAW0yV7fATC35hzw3REDZDa/Wkq7HV55ML8w6W5gKr6RjkcIKiDQQV8nuIumynkSj5PPUdqMzeow5neg0i4LPn+hFa99owJSZCtbJnS1XqLuqS9UYS2SJIr6+P+mtR/KQwEj5e2WNyNIoyysspzW/ZyCZXjTItEvDyIK4ahB5UKYuz3MlyK2DIHntlW3pXtO0utDMtqIPHHEAIqGocBuGYzJ7Yxx7imvWKJBUz X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2026 17:31:35.6867 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5fe19993-3e9d-4e0c-3c82-08de60256afa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF0000150A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9614 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support to handle multiple MC interrupts lines, as supported by Tegra264. Turn the single IRQ handler callback into a counted array to allow specifying a separate handler for each interrupt. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- drivers/memory/tegra/mc.c | 34 +++++++++++++++++++++------------ drivers/memory/tegra/mc.h | 1 + drivers/memory/tegra/tegra186.c | 3 ++- drivers/memory/tegra/tegra20.c | 7 ++++++- include/soc/tegra/mc.h | 6 ++++-- 5 files changed, 35 insertions(+), 16 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 1dacbe2aba4e..49c470f7b1f7 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -398,6 +398,10 @@ unsigned int tegra_mc_get_emem_device_count(struct teg= ra_mc *mc) } EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count); =20 +const irq_handler_t tegra30_mc_irq_handlers[] =3D { + tegra30_mc_handle_irq +}; + #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ defined(CONFIG_ARCH_TEGRA_114_SOC) || \ defined(CONFIG_ARCH_TEGRA_124_SOC) || \ @@ -551,7 +555,8 @@ int tegra30_mc_probe(struct tegra_mc *mc) =20 const struct tegra_mc_ops tegra30_mc_ops =3D { .probe =3D tegra30_mc_probe, - .handle_irq =3D tegra30_mc_handle_irq, + .handle_irq =3D tegra30_mc_irq_handlers, + .num_interrupts =3D ARRAY_SIZE(tegra30_mc_irq_handlers), }; #endif =20 @@ -953,25 +958,30 @@ static int tegra_mc_probe(struct platform_device *pde= v) tegra_mc_num_channel_enabled(mc); =20 if (mc->soc->ops && mc->soc->ops->handle_irq) { - mc->irq =3D platform_get_irq(pdev, 0); - if (mc->irq < 0) - return mc->irq; + unsigned int i; =20 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); =20 + for (i =3D 0; i < mc->soc->ops->num_interrupts; i++) { + int irq; + + irq =3D platform_get_irq(pdev, i); + if (irq < 0) + return irq; + + err =3D devm_request_irq(&pdev->dev, irq, mc->soc->ops->handle_irq[i], = 0, + dev_name(&pdev->dev), mc); + if (err < 0) { + dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); + return err; + } + } + if (mc->soc->num_channels) mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask, MC_INTMASK); else mc_writel(mc, mc->soc->intmask, MC_INTMASK); - - err =3D devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, = 0, - dev_name(&pdev->dev), mc); - if (err < 0) { - dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, - err); - return err; - } } =20 if (mc->soc->reset_ops) { diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 5f816d703d81..464cf75ccadc 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -193,6 +193,7 @@ extern const struct tegra_mc_ops tegra186_mc_ops; #endif =20 irqreturn_t tegra30_mc_handle_irq(int irq, void *data); +extern const irq_handler_t tegra30_mc_irq_handlers[]; extern const char * const tegra_mc_status_names[32]; extern const char * const tegra_mc_error_names[8]; =20 diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra18= 6.c index 51e2dd628fb4..23ec433f0f92 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -174,7 +174,8 @@ const struct tegra_mc_ops tegra186_mc_ops =3D { .remove =3D tegra186_mc_remove, .resume =3D tegra186_mc_resume, .probe_device =3D tegra186_mc_probe_device, - .handle_irq =3D tegra30_mc_handle_irq, + .handle_irq =3D tegra30_mc_irq_handlers, + .num_interrupts =3D 1, }; =20 #if defined(CONFIG_ARCH_TEGRA_186_SOC) diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index 227c3336974d..794255914f2e 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -761,9 +761,14 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void= *data) return IRQ_HANDLED; } =20 +static const irq_handler_t tegra20_mc_irq_handlers[] =3D { + tegra20_mc_handle_irq +}; + static const struct tegra_mc_ops tegra20_mc_ops =3D { .probe =3D tegra20_mc_probe, - .handle_irq =3D tegra20_mc_handle_irq, + .handle_irq =3D tegra20_mc_irq_handlers, + .num_interrupts =3D ARRAY_SIZE(tegra20_mc_irq_handlers), }; =20 const struct tegra_mc_soc tegra20_mc_soc =3D { diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 372f47e824d5..89f94abfaada 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -10,10 +10,11 @@ #include #include #include +#include #include #include -#include #include +#include =20 struct clk; struct device; @@ -164,8 +165,9 @@ struct tegra_mc_ops { int (*probe)(struct tegra_mc *mc); void (*remove)(struct tegra_mc *mc); int (*resume)(struct tegra_mc *mc); - irqreturn_t (*handle_irq)(int irq, void *data); int (*probe_device)(struct tegra_mc *mc, struct device *dev); + const irq_handler_t *handle_irq; + unsigned int num_interrupts; }; =20 struct tegra_mc_regs { --=20 2.17.1 From nobody Sat Feb 7 05:01:26 2026 Received: from BL0PR03CU003.outbound.protection.outlook.com (mail-eastusazon11012055.outbound.protection.outlook.com [52.101.53.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A709A36F417; Fri, 30 Jan 2026 17:31:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.53.55 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769794307; cv=fail; b=AsYPsOf8GMLcEZAKPlgJyg4+pIQIY0arxcrtu0yLpjXrHW9Zw2SAmRkZ+CHtdwHuy/T9iBFx3qQgMTccpGMEMzVBQkH9QvIL3UOg3YilGGqMJUYSbW1i+8ixdZCorxNLWrMCWHhJKKmPeDCjhJYRbV3iCKJtnmWtoapZjNh86N0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769794307; c=relaxed/simple; bh=f9infTZqCm1jVjrCICPoq/krhd3WdBBxJuRZG4SRVPM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UFHRI3+uH6C6Q00jBNHspvRqc1E3dbetoWp6oCpJ4Qdsi8wKmG1v+gSXslcJM7CgkayWiGn2zCZxCaYi00567jWrDT+MsuEWZBlOyjJrG1XVwtzHxU2fE2fc9BGmrD16OTp6aZkMaa0F2He+ab/Gzi0yD7/tAuoQCdoId/PINjs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=tgFA9vHo; arc=fail smtp.client-ip=52.101.53.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="tgFA9vHo" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=f0XwMLUUUOIpsK3Je5IwRDLcC9UURV5nds1ape4hSmMzr0fEnA6+B2NoGyzh7qArwVGel/MUkpLZfoYo+W08yN1Ub7s3sKscx3cqNzR7sLD6tkWeNOpo8GqTJbppmhBMmXYThXx6I/uCbGViWOv6EsMTQH+UrICeTtRjlGEMzZmS51BWvuqYJO9Tn8x5/I6QMbIkjatUv+ILXJXCZ7++ETskrw8V+w58cwN2seTChNO9O0BlGbqWbs8bNhgmg34gDaMCpnWVgMAV7CTZ3ZyvuqAnAdGIdco2mn6oRFVyhtOIPIWxDiT7rQIno0KOOxKtr+68HVfQ/3vw0rtAOtPBlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=KM7aCe89k7VFJVUztZCL5tjSkOTAbFPez5PFKFuWheM=; b=Gvpp6AerzbT5PkYoIY4Vvi/ZdFKdarWkEAAL41cIRFw2lLzfIsaF57s5IAGDiZbUBqB9Q1OMFLnV0aTjK6vuMzGM4TKJSDD572T2tXcA42HEoOT6sOVCjCXchPyBuqZJVVxOT34mu1653zUEwMfCxp5OvRci66JzoXj4FFDbmqwRSqH87OyUWfNjraEilxOXiSQuGK1NoixEyBaeubmZzO9emQaBnQgcOCpkeeqgxDQDdN/XQU+ryLrnw6bR3Lmse2Ll5hgDGdqQMYbzLN+E5Trv/zgMaH19c1SgyR1zuoWI4oDxsCtyA9xruWIS8KPgWkyEBIBXPB8kA8pBBDzBBw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KM7aCe89k7VFJVUztZCL5tjSkOTAbFPez5PFKFuWheM=; b=tgFA9vHoyEJd6e3J56zyx/rRV/LQDG88KHsvzGso3jvh1P9s3+obYcex4mKP7lpV4wMe9OpzZhXBOKsJGhwkXNRY3cSJ3tja9cAal6sggJkeIYz9ynLDq0Z54EvJY0oZ2uc2Yftof7W0P5bodw36yjPWRekLfSDw6oYVk9Ns0Emu4+TYeo5XEuPEllpeXziX1QP0cLQ+O1/HA69jucyob8wTNuZbFbo3m/QDFmWdUKwmf1HDM0IC6lX2aFNYqaQyyFB7Z806wFA+w1erUkqjJy+yrTkqF3D051pGKCe8HjNurScIl67Xba6yY6foRnH4tMwSR72lf7DFwkWXS1aRMg== Received: from SJ0PR13CA0106.namprd13.prod.outlook.com (2603:10b6:a03:2c5::21) by MN2PR12MB4373.namprd12.prod.outlook.com (2603:10b6:208:261::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.12; Fri, 30 Jan 2026 17:31:34 +0000 Received: from SJ5PEPF000001ED.namprd05.prod.outlook.com (2603:10b6:a03:2c5:cafe::f2) by SJ0PR13CA0106.outlook.office365.com (2603:10b6:a03:2c5::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9587.2 via Frontend Transport; Fri, 30 Jan 2026 17:31:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ5PEPF000001ED.mail.protection.outlook.com (10.167.242.201) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Fri, 30 Jan 2026 17:31:34 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 30 Jan 2026 09:31:21 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 30 Jan 2026 09:31:20 -0800 Received: from build-ketanp-bionic-20250813.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Fri, 30 Jan 2026 09:31:20 -0800 From: Ketan Patil To: , , CC: , , Ketan Patil Subject: [PATCH v6 4/4] memory: tegra: Add MC error logging support for Tegra264 Date: Fri, 30 Jan 2026 17:30:55 +0000 Message-ID: <20260130173055.151255-5-ketanp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260130173055.151255-1-ketanp@nvidia.com> References: <20260130173055.151255-1-ketanp@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001ED:EE_|MN2PR12MB4373:EE_ X-MS-Office365-Filtering-Correlation-Id: dc40b2c5-af9d-437c-0fff-08de602569fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?g6PJNN9RCynnGqemwjawlRYu98AN4O5ELezRpN2ens8jsIZRi9ddCQruuFoV?= =?us-ascii?Q?/0eh4N/N3cGvvkDESncqseX/5MgtfU+cbMmND6qZepUf9KXUyZ5NvcDovpN4?= =?us-ascii?Q?X8bAgXAG8OdejuAaxK1+zwpRiup3rSEOko7kmhXIQ79ejI0Uy5Xbv1s/5HeX?= =?us-ascii?Q?CVPZkbG3qKjruAd/uAa6/lDA+ujnb8u4GjM5xrvGJhrgOyBlHgrDsfFD+j8o?= =?us-ascii?Q?1Vp3fNcjP2kkhyFNfsMuRAvmS5S1beli1HDeJCxrZF/1jujzOupvR/zMzAWq?= =?us-ascii?Q?p0iivV9d5i/pi5VtxCPKw7DGPXIz++53aJ7frZBscdCWoxndz1YONSASSbi9?= =?us-ascii?Q?UMcvchj4wgGGL+aFjl76h+/Q3/9BCdQeyBvWe6roPkr/ew0jeH822kvCVnyH?= =?us-ascii?Q?M+J81SA1/WXv7aO58vJW17sjuh1rTeky5khjll9zTTrjGrXuFf7rS7QgdVQJ?= =?us-ascii?Q?ZoFY7+sZTP2VmbCxGpKW4fwIu6gSsqulw1mViWj7TohJZattJQx4eFCBoUXx?= =?us-ascii?Q?a7ws+p/e2Wujy3TTgBZWj9f41/yZysXoUlLOIqv21m6hjpoYUjbveeNTQ94h?= =?us-ascii?Q?vEtuYFzhnhK2FI5GjwoQXxXJQ9h/L/UTH2QTdugQxjIYoMKXkFNUXMOrFc1k?= =?us-ascii?Q?2aWK2ieYTDhFNw7Pp4J3tosn7dGtYGLQv5Pfn87fNvBSWnltPl5cJVPgCQnR?= =?us-ascii?Q?xfGXofFd0Gu7enC++PqLqlZhoo6IyhE92sdj4lbXbUu7rEYB0xSSw7WFIuYH?= =?us-ascii?Q?QP2kbbHjAD1Az0a0HqPmIy2EEBehJqU4slRPA6NjdvYU4turAC9+vn1Nz5yo?= =?us-ascii?Q?sK1JDI7nHrpfR0nQ+8sHyFJslIiGeC7omuicPBHSyHVA3f53xmIGjgbz8Uch?= =?us-ascii?Q?DxkiU6MBcpHi+RTbf2a9xvr/ZpoUW4mrvWaSkrKePniZmAtAuvyygpO4AWDe?= =?us-ascii?Q?v3fY0p87CuTkOmWAdwqMnpwzepqwYcan1OIL3ZtrlysX1Ty/bRdWaEpQRxpM?= =?us-ascii?Q?1BD/7gMfHTF08z9+Q9jejQcCW9UFoEeGCOl3+nu8D2ZLCOUUfW5TYS4tqHDe?= =?us-ascii?Q?jSJSvI0+bm3X2cZbJrl+d6OEW8hotC/FEHlMGjzDqEv3tsLdopxXX/YNPs1R?= =?us-ascii?Q?PLmHtezgzij38SHrXdGV2KAcX0gh0La88G1+zG8VBg/oY8O7JxJfcMprLTwx?= =?us-ascii?Q?vrWyY8LSExg7AYUBVgd/ffx1h9lJnSBpmIrqkOHuAitXMDUj1SmX0uFrzV8B?= =?us-ascii?Q?bQXiQOwBEthGIbfu+SV3LdgDr+H8wAFoOBmlqaFzQFV6nYe1JnhJ6EAd9hAR?= =?us-ascii?Q?dsOd8ZJ4dKQd6CToOVXfX/HLlvdYx3aEzIFQfPR/Qxuh+EQnYphtWwHkLZf4?= =?us-ascii?Q?UJXE4dnh5VwzMG7wPn+eFlDXDtwMBp73i5S1RQUXs9tRCAqQH+jV3/qbjb6+?= =?us-ascii?Q?pYLhjFAiQPvNF5Gn/jwhfH/UikSvQENwKluOqocxZ7N6T4wAqVa/Mxsjmrnv?= =?us-ascii?Q?5q1JdB5CfX2KkuvixT8m8TgE+Kc0r55/K6UFJFjqxgH7CyUog0OB91NRb5Vq?= =?us-ascii?Q?sUEMGU0Oij2kK7TXElmwMjqORe0kcc9Ag5+e4svmX/8tC7NXs7Ua7VtuNzlT?= =?us-ascii?Q?TwnNkY+VmTQrwpJEbacmoEN+I61epc/AZU1w87fCXI7/DsNi2MtsK8an7aNb?= =?us-ascii?Q?INJdKQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qCS9I7rrSYV4FZO54Dj9vP8vvigccMUivZwEHLkf7fj+vxx45aos9w/9HDW4dVVs+WuEBl3a70buwpr0HjMsmFxBkvcttSGPnaC5MRgYa2I6L/IEl8FVkXqKoEVpZvWV6xI4Y4c6ms90wIAqOnbb/DWUeVUSnDMmKw/SwK/Ko+1mmdkqX0JEUxnBaMEYhe7yBHH9fNTircwQBzKztJDIr1EFpDVKr2o6jCYMZDc7B+bmMgH/Hmyek1nVqb9q8MZ5XXoto3kMzSaaypRifFJC4aORSD43u8ybThVjlSpxukyTSKLFDmJ7haK7EL+lrNb5O4qpqC02CxCzjhR5lMSNriDYUuoPXdvLlvlsfyMxujnxi/Hx0pfMhuGHOiO2GHT43H9r4D4DgFcXFWVC2thjZwfglJ9tYF4HwbjolF+3Eb3El9Q4DU2CCGIgsacYfYO2 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2026 17:31:34.1107 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dc40b2c5-af9d-437c-0fff-08de602569fa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4373 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In Tegra264, different components from memory subsystems like Memory Controller Fabric (MCF), HUB, HUB Common (HUBC), Side Band Shim (SBS) and channels have different interrupt lines for receiving memory controller error interrupts. Add support for logging memory controller errors on Tegra264. - Add MC error handling flow for MCF, HUB, HUBC, SBS and channels. - Each of these components have different interrupt lines for MC error. - Register interrupt handlers for interrupts from these different MC components. - There is no global interrupt status register in Tegra264 unlike older Tegra chips. - There are common interrupt status registers in case of MCF, HUB, HUBC from which figure out the slice number or hub number responsible for generating interrupt and then read interrupt status register to find out type of violation. - Introduce new SoC specific fields in tegra_mc_soc like interrupt mask values for MCF, HUB, HUBC etc., which are SoC specific. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- drivers/memory/tegra/mc.c | 35 +-- drivers/memory/tegra/mc.h | 83 ++++++- drivers/memory/tegra/tegra114.c | 13 +- drivers/memory/tegra/tegra124.c | 32 ++- drivers/memory/tegra/tegra186.c | 24 +- drivers/memory/tegra/tegra194.c | 17 +- drivers/memory/tegra/tegra20.c | 23 +- drivers/memory/tegra/tegra210.c | 16 +- drivers/memory/tegra/tegra234.c | 17 +- drivers/memory/tegra/tegra264.c | 428 +++++++++++++++++++++++++++++++- drivers/memory/tegra/tegra30.c | 13 +- include/soc/tegra/mc.h | 10 +- 12 files changed, 648 insertions(+), 63 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 49c470f7b1f7..a102a8ea7926 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -597,16 +597,16 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data) } =20 /* mask all interrupts to avoid flooding */ - status =3D mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmask; + status =3D mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmasks[0]= .mask; } else { - status =3D mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; + status =3D mc_readl(mc, MC_INTSTATUS) & mc->soc->intmasks[0].mask; } =20 if (!status) return IRQ_NONE; =20 for_each_set_bit(bit, &status, 32) { - const char *error =3D tegra_mc_status_names[bit] ?: "unknown"; + const char *error =3D tegra20_mc_status_names[bit] ?: "unknown"; const char *client =3D "unknown", *desc; const char *direction, *secure; u32 status_reg, addr_reg; @@ -669,9 +669,11 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data) addr =3D mc_ch_readl(mc, channel, addr_hi_reg); else addr =3D mc_readl(mc, addr_hi_reg); - } else { + } else if (mc->soc->mc_addr_hi_mask) { addr =3D ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & - MC_ERR_STATUS_ADR_HI_MASK); + mc->soc->mc_addr_hi_mask); + } else { + WARN_ON(1); } addr <<=3D 32; } @@ -696,11 +698,11 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data) } } =20 - type =3D (value & MC_ERR_STATUS_TYPE_MASK) >> + type =3D (value & mc->soc->mc_err_status_type_mask) >> MC_ERR_STATUS_TYPE_SHIFT; - desc =3D tegra_mc_error_names[type]; + desc =3D tegra20_mc_error_names[type]; =20 - switch (value & MC_ERR_STATUS_TYPE_MASK) { + switch (value & mc->soc->mc_err_status_type_mask) { case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: perm[0] =3D ' '; perm[1] =3D '['; @@ -753,7 +755,7 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data) return IRQ_HANDLED; } =20 -const char *const tegra_mc_status_names[32] =3D { +const char *const tegra20_mc_status_names[32] =3D { [ 1] =3D "External interrupt", [ 6] =3D "EMEM address decode error", [ 7] =3D "GART page fault", @@ -766,9 +768,10 @@ const char *const tegra_mc_status_names[32] =3D { [16] =3D "MTS carveout violation", [17] =3D "Generalized carveout violation", [20] =3D "Route Sanity error", + [21] =3D "GIC_MSI error", }; =20 -const char *const tegra_mc_error_names[8] =3D { +const char *const tegra20_mc_error_names[8] =3D { [2] =3D "EMEM decode error", [3] =3D "TrustZone violation", [4] =3D "Carveout violation", @@ -977,11 +980,13 @@ static int tegra_mc_probe(struct platform_device *pde= v) } } =20 - if (mc->soc->num_channels) - mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask, - MC_INTMASK); - else - mc_writel(mc, mc->soc->intmask, MC_INTMASK); + for (i =3D 0; i < mc->soc->num_intmasks; i++) { + if (mc->soc->num_channels) + mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask, + mc->soc->intmasks[i].reg); + else + mc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg); + } } =20 if (mc->soc->reset_ops) { diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 464cf75ccadc..28b01f6173f4 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -25,6 +25,7 @@ #define MC_INT_DECERR_MTS BIT(16) #define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17) #define MC_INT_DECERR_ROUTE_SANITY BIT(20) +#define MC_INT_DECERR_ROUTE_SANITY_GIC_MSI BIT(21) =20 #define MC_INTMASK 0x04 #define MC_GART_ERROR_REQ 0x30 @@ -76,15 +77,82 @@ #define MC_ERR_STATUS_WRITABLE BIT(26) #define MC_ERR_STATUS_READABLE BIT(27) =20 +#define MC_ERR_STATUS_GSC_ADR_HI_MASK 0xffff +#define MC_ERR_STATUS_GSC_ADR_HI_SHIFT 16 +#define MC_ERR_STATUS_RT_ADR_HI_SHIFT 15 + #define MC_ERR_STATUS_TYPE_SHIFT 28 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (0x6 << 28) -#define MC_ERR_STATUS_TYPE_MASK (0x7 << 28) +#define MC_ERR_STATUS_RT_TYPE_MASK (0xf << 28) +#define MC_ERR_STATUS_RT_TYPE_SHIFT 28 =20 #define MC_ERR_STATUS_ADR_HI_SHIFT 20 -#define MC_ERR_STATUS_ADR_HI_MASK 0x3 =20 #define MC_BROADCAST_CHANNEL ~0 =20 +/* Tegra264 specific registers */ + +/* Registers for MSS HUB */ +#define MSS_HUB_GLOBAL_INTSTATUS_0 0x6000 +#define MSS_HUBC_INTR BIT(0) +#define MSS_HUB_GLOBAL_MASK 0x7F00 +#define MSS_HUB_GLOBAL_SHIFT 8 + +#define MSS_HUB_HUBC_INTSTATUS_0 0x6008 +#define MSS_HUB_INTRSTATUS_0 0x600c +#define MSS_HUB_HUBC_INTMASK_0 0x6010 +#define MSS_HUB_HUBC_SCRUB_DONE_INTMASK BIT(0) + +#define MSS_HUB_HUBC_INTPRIORITY_0 0x6014 +#define MSS_HUB_INTRMASK_0 0x6018 +#define MSS_HUB_COALESCER_ERR_INTMASK BIT(0) +#define MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK BIT(1) +#define MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK BIT(2) +#define MSS_HUB_MSI_ERR_INTMASK BIT(3) +#define MSS_HUB_POISON_RSP_INTMASK BIT(4) +#define MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK BIT(5) +#define MSS_HUB_RESERVED_PA_ERR_INTMASK BIT(6) + +#define MSS_HUB_INTRPRIORITY_0 0x601c +#define MSS_HUB_SMMU_BYPASS_ALLOW_ERR_STATUS_0 0x6020 +#define MSS_HUB_MSI_ERR_STATUS_0 0x6024 +#define MSS_HUB_POISON_RSP_STATUS_0 0x6028 +#define MSS_HUB_COALESCE_ERR_STATUS_0 0x60e0 +#define MSS_HUB_COALESCE_ERR_ADR_HI_0 0x60e4 +#define MSS_HUB_COALESCE_ERR_ADR_0 0x60e8 +#define MSS_HUB_RESTRICTED_ACCESS_ERR_STATUS_0 0x638c +#define MSS_HUB_RESERVED_PA_ERR_STATUS_0 0x6390 +#define MSS_HUB_ILLEGAL_TBUGRP_ID_ERR_STATUS_0 0x63b0 + +/* Registers for channels */ +#define MC_CH_INTSTATUS_0 0x82d4 +#define MC_CH_INTMASK_0 0x82d8 +#define WCAM_ERR_INTMASK BIT(19) + +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS_1_0 0xbc74 + +/* Registers for MCF */ +#define MCF_COMMON_INTSTATUS0_0_0 0xce04 +#define MCF_INTSTATUS_0 0xce2c +#define MCF_INTMASK_0 0xce30 +#define MCF_INTPRIORITY_0 0xce34 + +/* Registers for SBS */ +#define MSS_SBS_INTSTATUS_0 0xec08 +#define MSS_SBS_INTMASK_0 0xec0c +#define MSS_SBS_FILL_FIFO_ISO_OVERFLOW_INTMASK BIT(0) +#define MSS_SBS_FILL_FIFO_SISO_OVERFLOW_INTMASK BIT(1) +#define MSS_SBS_FILL_FIFO_NISO_OVERFLOW_INTMASK BIT(2) + +/* Bit field of MC_ERR_ROUTE_SANITY_STATUS_0 register */ +#define MC_ERR_ROUTE_SANITY_RW BIT(12) +#define MC_ERR_ROUTE_SANITY_SEC BIT(13) + +#define ERR_GENERALIZED_APERTURE_ID_SHIFT 0 +#define ERR_GENERALIZED_APERTURE_ID_MASK 0x1F +#define ERR_GENERALIZED_CARVEOUT_APERTURE_ID_SHIFT 5 +#define ERR_GENERALIZED_CARVEOUT_APERTURE_ID_MASK 0x1F + static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents) { val =3D val * percents; @@ -187,15 +255,18 @@ extern const struct tegra_mc_ops tegra30_mc_ops; =20 #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \ defined(CONFIG_ARCH_TEGRA_194_SOC) || \ - defined(CONFIG_ARCH_TEGRA_234_SOC) || \ - defined(CONFIG_ARCH_TEGRA_264_SOC) + defined(CONFIG_ARCH_TEGRA_234_SOC) extern const struct tegra_mc_ops tegra186_mc_ops; #endif =20 irqreturn_t tegra30_mc_handle_irq(int irq, void *data); extern const irq_handler_t tegra30_mc_irq_handlers[]; -extern const char * const tegra_mc_status_names[32]; -extern const char * const tegra_mc_error_names[8]; +extern const char * const tegra20_mc_status_names[32]; +extern const char * const tegra20_mc_error_names[8]; +int tegra186_mc_probe(struct tegra_mc *mc); +int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev); +int tegra186_mc_resume(struct tegra_mc *mc); +void tegra186_mc_remove(struct tegra_mc *mc); =20 /* * These IDs are for internal use of Tegra ICC drivers. The ID numbers are diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra11= 4.c index ea7e4c7bb5f8..ddc81d844723 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -1101,6 +1101,14 @@ static const struct tegra_mc_reset tegra114_mc_reset= s[] =3D { TEGRA114_MC_RESET(VI, 0x200, 0x204, 17), }; =20 +static const struct tegra_mc_intmask tegra114_mc_intmasks[] =3D { + { + .reg =3D MC_INTMASK, + .mask =3D MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION | + MC_INT_DECERR_EMEM, + }, +}; + const struct tegra_mc_soc tegra114_mc_soc =3D { .clients =3D tegra114_mc_clients, .num_clients =3D ARRAY_SIZE(tegra114_mc_clients), @@ -1108,11 +1116,12 @@ const struct tegra_mc_soc tegra114_mc_soc =3D { .atom_size =3D 32, .client_id_mask =3D 0x7f, .smmu =3D &tegra114_smmu_soc, - .intmask =3D MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION | - MC_INT_DECERR_EMEM, + .intmasks =3D tegra114_mc_intmasks, + .num_intmasks =3D ARRAY_SIZE(tegra114_mc_intmasks), .reset_ops =3D &tegra_mc_reset_ops_common, .resets =3D tegra114_mc_resets, .num_resets =3D ARRAY_SIZE(tegra114_mc_resets), .ops =3D &tegra30_mc_ops, .regs =3D &tegra20_mc_regs, + .mc_err_status_type_mask =3D (0x7 << 28), }; diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra12= 4.c index c5529f79fbb4..b21b10562ab2 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -1258,6 +1258,15 @@ static const struct tegra_smmu_soc tegra124_smmu_soc= =3D { .num_asids =3D 128, }; =20 +static const struct tegra_mc_intmask tegra124_mc_intmasks[] =3D { + { + .reg =3D MC_INTMASK, + .mask =3D MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + }, +}; + const struct tegra_mc_soc tegra124_mc_soc =3D { .clients =3D tegra124_mc_clients, .num_clients =3D ARRAY_SIZE(tegra124_mc_clients), @@ -1267,15 +1276,16 @@ const struct tegra_mc_soc tegra124_mc_soc =3D { .smmu =3D &tegra124_smmu_soc, .emem_regs =3D tegra124_mc_emem_regs, .num_emem_regs =3D ARRAY_SIZE(tegra124_mc_emem_regs), - .intmask =3D MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | - MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | - MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .intmasks =3D tegra124_mc_intmasks, + .num_intmasks =3D ARRAY_SIZE(tegra124_mc_intmasks), .reset_ops =3D &tegra_mc_reset_ops_common, .resets =3D tegra124_mc_resets, .num_resets =3D ARRAY_SIZE(tegra124_mc_resets), .icc_ops =3D &tegra124_mc_icc_ops, .ops =3D &tegra30_mc_ops, .regs =3D &tegra20_mc_regs, + .mc_addr_hi_mask =3D 0x3, + .mc_err_status_type_mask =3D (0x7 << 28), }; #endif /* CONFIG_ARCH_TEGRA_124_SOC */ =20 @@ -1293,6 +1303,15 @@ static const struct tegra_smmu_soc tegra132_smmu_soc= =3D { .num_asids =3D 128, }; =20 +static const struct tegra_mc_intmask tegra132_mc_intmasks[] =3D { + { + .reg =3D MC_INTMASK, + .mask =3D MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + }, +}; + const struct tegra_mc_soc tegra132_mc_soc =3D { .clients =3D tegra124_mc_clients, .num_clients =3D ARRAY_SIZE(tegra124_mc_clients), @@ -1300,14 +1319,15 @@ const struct tegra_mc_soc tegra132_mc_soc =3D { .atom_size =3D 32, .client_id_mask =3D 0x7f, .smmu =3D &tegra132_smmu_soc, - .intmask =3D MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | - MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | - MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .intmasks =3D tegra132_mc_intmasks, + .num_intmasks =3D ARRAY_SIZE(tegra132_mc_intmasks), .reset_ops =3D &tegra_mc_reset_ops_common, .resets =3D tegra124_mc_resets, .num_resets =3D ARRAY_SIZE(tegra124_mc_resets), .icc_ops =3D &tegra124_mc_icc_ops, .ops =3D &tegra30_mc_ops, .regs =3D &tegra20_mc_regs, + .mc_addr_hi_mask =3D 0x3, + .mc_err_status_type_mask =3D (0x7 << 28), }; #endif /* CONFIG_ARCH_TEGRA_132_SOC */ diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra18= 6.c index 23ec433f0f92..135eb5603637 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -23,7 +23,7 @@ #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16) #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8) =20 -static int tegra186_mc_probe(struct tegra_mc *mc) +int tegra186_mc_probe(struct tegra_mc *mc) { struct platform_device *pdev =3D to_platform_device(mc->dev); struct resource *res; @@ -76,7 +76,7 @@ static int tegra186_mc_probe(struct tegra_mc *mc) return 0; } =20 -static void tegra186_mc_remove(struct tegra_mc *mc) +void tegra186_mc_remove(struct tegra_mc *mc) { of_platform_depopulate(mc->dev); } @@ -124,7 +124,7 @@ static void tegra186_mc_client_sid_override(struct tegr= a_mc *mc, } #endif =20 -static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *de= v) +int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) { #if IS_ENABLED(CONFIG_IOMMU_API) struct of_phandle_args args; @@ -154,7 +154,7 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc= , struct device *dev) return 0; } =20 -static int tegra186_mc_resume(struct tegra_mc *mc) +int tegra186_mc_resume(struct tegra_mc *mc) { #if IS_ENABLED(CONFIG_IOMMU_API) unsigned int i; @@ -903,18 +903,28 @@ static const struct tegra_mc_client tegra186_mc_clien= ts[] =3D { }, }; =20 +static const struct tegra_mc_intmask tegra186_mc_intmasks[] =3D { + { + .reg =3D MC_INTMASK, + .mask =3D MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + }, +}; + const struct tegra_mc_soc tegra186_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra186_mc_clients), .clients =3D tegra186_mc_clients, .num_address_bits =3D 40, .num_channels =3D 4, .client_id_mask =3D 0xff, - .intmask =3D MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | - MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | - MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .intmasks =3D tegra186_mc_intmasks, + .num_intmasks =3D ARRAY_SIZE(tegra186_mc_intmasks), .ops =3D &tegra186_mc_ops, .ch_intmask =3D 0x0000000f, .global_intstatus_channel_shift =3D 0, .regs =3D &tegra20_mc_regs, + .mc_addr_hi_mask =3D 0x3, + .mc_err_status_type_mask =3D (0x7 << 28), }; #endif diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra19= 4.c index 5b7ff2dd6812..2be6250db9cc 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -1343,20 +1343,29 @@ static const struct tegra_mc_client tegra194_mc_cli= ents[] =3D { }, }; =20 +static const struct tegra_mc_intmask tegra194_mc_intmasks[] =3D { + { + .reg =3D MC_INTMASK, + .mask =3D MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOU= T | + MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + }, +}; + const struct tegra_mc_soc tegra194_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra194_mc_clients), .clients =3D tegra194_mc_clients, .num_address_bits =3D 40, .num_channels =3D 16, .client_id_mask =3D 0xff, - .intmask =3D MC_INT_DECERR_ROUTE_SANITY | - MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | - MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | - MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .intmasks =3D tegra194_mc_intmasks, + .num_intmasks =3D ARRAY_SIZE(tegra194_mc_intmasks), .has_addr_hi_reg =3D true, .ops =3D &tegra186_mc_ops, .icc_ops =3D &tegra_mc_icc_ops, .ch_intmask =3D 0x00000f00, .global_intstatus_channel_shift =3D 8, .regs =3D &tegra20_mc_regs, + .mc_addr_hi_mask =3D 0x3, + .mc_err_status_type_mask =3D (0x7 << 28), }; diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index 794255914f2e..d1153bb996ee 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -695,12 +695,12 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, voi= d *data) unsigned int bit; =20 /* mask all interrupts to avoid flooding */ - status =3D mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; + status =3D mc_readl(mc, MC_INTSTATUS) & mc->soc->intmasks[0].mask; if (!status) return IRQ_NONE; =20 for_each_set_bit(bit, &status, 32) { - const char *error =3D tegra_mc_status_names[bit]; + const char *error =3D tegra20_mc_status_names[bit]; const char *direction =3D "read", *secure =3D ""; const char *client, *desc; phys_addr_t addr; @@ -713,7 +713,7 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void = *data) value =3D mc_readl(mc, reg); =20 id =3D value & mc->soc->client_id_mask; - desc =3D tegra_mc_error_names[2]; + desc =3D tegra20_mc_error_names[2]; =20 if (value & BIT(31)) direction =3D "write"; @@ -724,7 +724,7 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void = *data) value =3D mc_readl(mc, reg); =20 id =3D (value >> 1) & mc->soc->client_id_mask; - desc =3D tegra_mc_error_names[2]; + desc =3D tegra20_mc_error_names[2]; =20 if (value & BIT(0)) direction =3D "write"; @@ -736,7 +736,7 @@ static irqreturn_t tegra20_mc_handle_irq(int irq, void = *data) =20 id =3D value & mc->soc->client_id_mask; type =3D (value & BIT(30)) ? 4 : 3; - desc =3D tegra_mc_error_names[type]; + desc =3D tegra20_mc_error_names[type]; secure =3D "secure "; =20 if (value & BIT(31)) @@ -771,17 +771,26 @@ static const struct tegra_mc_ops tegra20_mc_ops =3D { .num_interrupts =3D ARRAY_SIZE(tegra20_mc_irq_handlers), }; =20 +static const struct tegra_mc_intmask tegra20_mc_intmasks[] =3D { + { + .reg =3D MC_INTMASK, + .mask =3D MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE | + MC_INT_DECERR_EMEM, + }, +}; + const struct tegra_mc_soc tegra20_mc_soc =3D { .clients =3D tegra20_mc_clients, .num_clients =3D ARRAY_SIZE(tegra20_mc_clients), .num_address_bits =3D 32, .client_id_mask =3D 0x3f, - .intmask =3D MC_INT_SECURITY_VIOLATION | MC_INT_INVALID_GART_PAGE | - MC_INT_DECERR_EMEM, + .intmasks =3D tegra20_mc_intmasks, + .num_intmasks =3D ARRAY_SIZE(tegra20_mc_intmasks), .reset_ops =3D &tegra20_mc_reset_ops, .resets =3D tegra20_mc_resets, .num_resets =3D ARRAY_SIZE(tegra20_mc_resets), .icc_ops =3D &tegra20_mc_icc_ops, .ops =3D &tegra20_mc_ops, .regs =3D &tegra20_mc_regs, + .mc_err_status_type_mask =3D (0x7 << 28), }; diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra21= 0.c index e166b33848e9..8e5011ea57be 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -1273,6 +1273,15 @@ static const struct tegra_mc_reset tegra210_mc_reset= s[] =3D { TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13), }; =20 +static const struct tegra_mc_intmask tegra210_mc_intmasks[] =3D { + { + .reg =3D MC_INTMASK, + .mask =3D MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + }, +}; + const struct tegra_mc_soc tegra210_mc_soc =3D { .clients =3D tegra210_mc_clients, .num_clients =3D ARRAY_SIZE(tegra210_mc_clients), @@ -1280,12 +1289,13 @@ const struct tegra_mc_soc tegra210_mc_soc =3D { .atom_size =3D 64, .client_id_mask =3D 0xff, .smmu =3D &tegra210_smmu_soc, - .intmask =3D MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | - MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | - MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .intmasks =3D tegra210_mc_intmasks, + .num_intmasks =3D ARRAY_SIZE(tegra210_mc_intmasks), .reset_ops =3D &tegra_mc_reset_ops_common, .resets =3D tegra210_mc_resets, .num_resets =3D ARRAY_SIZE(tegra210_mc_resets), .ops =3D &tegra30_mc_ops, .regs =3D &tegra20_mc_regs, + .mc_addr_hi_mask =3D 0x3, + .mc_err_status_type_mask =3D (0x7 << 28), }; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index 512d054d7592..d920144e6cfa 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -1132,16 +1132,23 @@ static const struct tegra_mc_icc_ops tegra234_mc_ic= c_ops =3D { .set =3D tegra234_mc_icc_set, }; =20 +static const struct tegra_mc_intmask tegra234_mc_intmasks[] =3D { + { + .reg =3D MC_INTMASK, + .mask =3D MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOU= T | + MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + }, +}; + const struct tegra_mc_soc tegra234_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra234_mc_clients), .clients =3D tegra234_mc_clients, .num_address_bits =3D 40, .num_channels =3D 16, .client_id_mask =3D 0x1ff, - .intmask =3D MC_INT_DECERR_ROUTE_SANITY | - MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | - MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | - MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .intmasks =3D tegra234_mc_intmasks, + .num_intmasks =3D ARRAY_SIZE(tegra234_mc_intmasks), .has_addr_hi_reg =3D true, .ops =3D &tegra186_mc_ops, .icc_ops =3D &tegra234_mc_icc_ops, @@ -1153,4 +1160,6 @@ const struct tegra_mc_soc tegra234_mc_soc =3D { */ .num_carveouts =3D 32, .regs =3D &tegra20_mc_regs, + .mc_addr_hi_mask =3D 0x3, + .mc_err_status_type_mask =3D (0x7 << 28), }; diff --git a/drivers/memory/tegra/tegra264.c b/drivers/memory/tegra/tegra26= 4.c index 5203e6c11372..5eac05b63d4f 100644 --- a/drivers/memory/tegra/tegra264.c +++ b/drivers/memory/tegra/tegra264.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2025, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2025-2026, NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -188,6 +188,41 @@ static const struct tegra_mc_client tegra264_mc_client= s[] =3D { }, }; =20 +static const char *const tegra_hub_status_names[32] =3D { + [0] =3D "coalescer error", + [1] =3D "SMMU BYPASS ALLOW error", + [2] =3D "Illegal tbugrp_id error", + [3] =3D "Malformed MSI request error", + [4] =3D "Read response with poison bit error", + [5] =3D "Restricted access violation error", + [6] =3D "Reserved PA error", +}; + +static const char *const tegra264_mc_error_names[4] =3D { + [1] =3D "EMEM decode error", + [2] =3D "TrustZone violation", + [3] =3D "Carveout violation", +}; + +static const char *const tegra264_rt_error_names[16] =3D { + [1] =3D "DECERR_PARTIAL_POPULATED", + [2] =3D "DECERR_SMMU_BYPASS", + [3] =3D "DECERR_INVALID_MMIO", + [4] =3D "DECERR_INVALID_GIC_MSI", + [5] =3D "DECERR_ATOMIC_SYSRAM", + [9] =3D "DECERR_REMOTE_REQ_PRE_BOOT", + [10] =3D "DECERR_ISO_OVER_C2C", + [11] =3D "DECERR_UNSUPPORTED_SBS_OPCODE", + [12] =3D "DECERR_SBS_REQ_OVER_SISO_LL", +}; + +/* + * MC instance aperture mapping for hubc registers + */ +static const int mc_hubc_aperture_number[5] =3D { + 7, 8, 9, 10, 11 +}; + /* * tegra264_mc_icc_set() - Pass MC client info to the BPMP-FW * @src: ICC node for Memory Controller's (MC) Client @@ -283,6 +318,320 @@ static int tegra264_mc_icc_get_init_bw(struct icc_nod= e *node, u32 *avg, u32 *pea return 0; } =20 +static void mcf_log_fault(struct tegra_mc *mc, u32 channel, unsigned long = mcf_ch_intstatus) +{ + unsigned int bit; + + for_each_set_bit(bit, &mcf_ch_intstatus, 32) { + const char *client =3D "unknown", *desc =3D "NA"; + u32 status_reg, status1_reg =3D 0, addr_reg, addr_hi_reg =3D 0, err_type= _mask =3D 0; + u32 value, client_id, i, addr_hi_shift =3D 0, addr_hi_mask =3D 0, status= 1; + u32 mc_rw_bit =3D MC_ERR_STATUS_RW, mc_sec_bit =3D MC_ERR_STATUS_SECURIT= Y; + phys_addr_t addr =3D 0; + u8 type; + + switch (BIT(bit)) { + case MC_INT_DECERR_EMEM: + case MC_INT_SECURITY_VIOLATION: + status_reg =3D mc->soc->regs->err_status; + addr_reg =3D mc->soc->regs->err_add; + addr_hi_reg =3D mc->soc->regs->err_add_hi; + err_type_mask =3D mc->soc->mc_err_status_type_mask; + break; + + case MC_INT_DECERR_VPR: + status_reg =3D mc->soc->regs->err_vpr_status; + addr_reg =3D mc->soc->regs->err_vpr_add; + addr_hi_shift =3D MC_ERR_STATUS_ADR_HI_SHIFT; + addr_hi_mask =3D mc->soc->mc_addr_hi_mask; + break; + + case MC_INT_SECERR_SEC: + status_reg =3D mc->soc->regs->err_sec_status; + addr_reg =3D mc->soc->regs->err_sec_add; + addr_hi_shift =3D MC_ERR_STATUS_ADR_HI_SHIFT; + addr_hi_mask =3D mc->soc->mc_addr_hi_mask; + break; + + case MC_INT_DECERR_MTS: + status_reg =3D mc->soc->regs->err_mts_status; + addr_reg =3D mc->soc->regs->err_mts_add; + addr_hi_shift =3D MC_ERR_STATUS_ADR_HI_SHIFT; + addr_hi_mask =3D mc->soc->mc_addr_hi_mask; + break; + + case MC_INT_DECERR_GENERALIZED_CARVEOUT: + status_reg =3D mc->soc->regs->err_gen_co_status; + status1_reg =3D MC_ERR_GENERALIZED_CARVEOUT_STATUS_1_0; + addr_reg =3D mc->soc->regs->err_gen_co_add; + addr_hi_shift =3D MC_ERR_STATUS_GSC_ADR_HI_SHIFT; + addr_hi_mask =3D MC_ERR_STATUS_GSC_ADR_HI_MASK; + break; + + case MC_INT_DECERR_ROUTE_SANITY: + case MC_INT_DECERR_ROUTE_SANITY_GIC_MSI: + status_reg =3D mc->soc->regs->err_route_status; + addr_reg =3D mc->soc->regs->err_route_add; + addr_hi_shift =3D MC_ERR_STATUS_RT_ADR_HI_SHIFT; + addr_hi_mask =3D mc->soc->mc_addr_hi_mask; + mc_sec_bit =3D MC_ERR_ROUTE_SANITY_SEC; + mc_rw_bit =3D MC_ERR_ROUTE_SANITY_RW; + err_type_mask =3D MC_ERR_STATUS_RT_TYPE_MASK; + break; + + default: + dev_err_ratelimited(mc->dev, "Incorrect MC interrupt mask\n"); + return; + } + + value =3D mc_ch_readl(mc, channel, status_reg); + if (addr_hi_reg) { + addr =3D mc_ch_readl(mc, channel, addr_hi_reg); + } else { + if (!status1_reg) { + addr =3D ((value >> addr_hi_shift) & addr_hi_mask); + } else { + status1 =3D mc_ch_readl(mc, channel, status1_reg); + addr =3D ((status1 >> addr_hi_shift) & addr_hi_mask); + } + } + + addr <<=3D 32; + addr |=3D mc_ch_readl(mc, channel, addr_reg); + + client_id =3D value & mc->soc->client_id_mask; + for (i =3D 0; i < mc->soc->num_clients; i++) { + if (mc->soc->clients[i].id =3D=3D client_id) { + client =3D mc->soc->clients[i].name; + break; + } + } + + if (err_type_mask =3D=3D MC_ERR_STATUS_RT_TYPE_MASK) { + type =3D (value & err_type_mask) >> + MC_ERR_STATUS_RT_TYPE_SHIFT; + desc =3D tegra264_rt_error_names[type]; + } else if (err_type_mask) { + type =3D (value & err_type_mask) >> + MC_ERR_STATUS_TYPE_SHIFT; + desc =3D tegra264_mc_error_names[type]; + } + + dev_err_ratelimited(mc->dev, "%s: %s %s @%pa: %s (%s)\n", + client, value & mc_sec_bit ? "secure" : "non-secure", + value & mc_rw_bit ? "write" : "read", &addr, + tegra20_mc_status_names[bit] ?: "unknown", desc); + if (status1_reg) + dev_err_ratelimited(mc->dev, "gsc_apr_id=3D%u gsc_co_apr_id=3D%u\n", + ((status1 >> ERR_GENERALIZED_APERTURE_ID_SHIFT) + & ERR_GENERALIZED_APERTURE_ID_MASK), + ((status1 >> ERR_GENERALIZED_CARVEOUT_APERTURE_ID_SHIFT) + & ERR_GENERALIZED_CARVEOUT_APERTURE_ID_MASK)); + } + + /* clear interrupts */ + mc_ch_writel(mc, channel, mcf_ch_intstatus, MCF_INTSTATUS_0); +} + +static irqreturn_t handle_mcf_irq(int irq, void *data) +{ + struct tegra_mc *mc =3D data; + unsigned long common_intstat, intstatus; + u32 slice; + + /* Read MCF_COMMON_INTSTATUS0_0_0 from MCB block */ + common_intstat =3D mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MCF_COMMON_INTST= ATUS0_0_0); + if (common_intstat =3D=3D 0) { + dev_warn(mc->dev, "No interrupt in MCF\n"); + return IRQ_NONE; + } + + for_each_set_bit(slice, &common_intstat, 32) { + /* Find out the slice number on which interrupt occurred */ + if (slice > 4) { + dev_err(mc->dev, "Slice index out of bounds: %u\n", slice); + return IRQ_NONE; + } + + intstatus =3D mc_ch_readl(mc, slice, MCF_INTSTATUS_0); + if (intstatus !=3D 0) + mcf_log_fault(mc, slice, intstatus); + } + + return IRQ_HANDLED; +} + +static void hub_log_fault(struct tegra_mc *mc, u32 hub, unsigned long hub_= intstat) +{ + unsigned int bit; + + for_each_set_bit(bit, &hub_intstat, 32) { + const char *client =3D "unknown"; + u32 client_id, status_reg, value, i; + phys_addr_t addr =3D 0; + + switch (BIT(bit)) { + case MSS_HUB_COALESCER_ERR_INTMASK: + status_reg =3D MSS_HUB_COALESCE_ERR_STATUS_0; + addr =3D mc_ch_readl(mc, hub, MSS_HUB_COALESCE_ERR_ADR_HI_0); + addr <<=3D 32; + addr |=3D mc_ch_readl(mc, hub, MSS_HUB_COALESCE_ERR_ADR_0); + break; + + case MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK: + status_reg =3D MSS_HUB_SMMU_BYPASS_ALLOW_ERR_STATUS_0; + break; + + case MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK: + status_reg =3D MSS_HUB_ILLEGAL_TBUGRP_ID_ERR_STATUS_0; + break; + + case MSS_HUB_MSI_ERR_INTMASK: + status_reg =3D MSS_HUB_MSI_ERR_STATUS_0; + break; + + case MSS_HUB_POISON_RSP_INTMASK: + status_reg =3D MSS_HUB_POISON_RSP_STATUS_0; + break; + + case MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK: + status_reg =3D MSS_HUB_RESTRICTED_ACCESS_ERR_STATUS_0; + break; + + case MSS_HUB_RESERVED_PA_ERR_INTMASK: + status_reg =3D MSS_HUB_RESERVED_PA_ERR_STATUS_0; + break; + + default: + dev_err_ratelimited(mc->dev, "Incorrect HUB interrupt mask\n"); + return; + } + + value =3D mc_ch_readl(mc, hub, status_reg); + + client_id =3D value & mc->soc->client_id_mask; + for (i =3D 0; i < mc->soc->num_clients; i++) { + if (mc->soc->clients[i].id =3D=3D client_id) { + client =3D mc->soc->clients[i].name; + break; + } + } + + dev_err_ratelimited(mc->dev, "%s: @%pa: %s status: 0x%x\n", + client, &addr, tegra_hub_status_names[bit] ?: "unknown", value); + } + + /* clear interrupts */ + mc_ch_writel(mc, hub, hub_intstat, MSS_HUB_INTRSTATUS_0); +} + +static irqreturn_t handle_hub_irq(int irq, void *data, int mc_hubc_apertur= e_number) +{ + struct tegra_mc *mc =3D data; + u32 global_intstat; + unsigned long hub_interrupt, intstat, hub; + + /* Read MSS_HUB_GLOBAL_INTSTATUS_0 from mc_hubc_aperture_number block */ + global_intstat =3D mc_ch_readl(mc, mc_hubc_aperture_number, MSS_HUB_GLOBA= L_INTSTATUS_0); + if (global_intstat =3D=3D 0) { + dev_warn(mc->dev, "No interrupt in HUB/HUBC\n"); + return IRQ_NONE; + } + + /* Handle interrupt from hubc */ + if (global_intstat & MSS_HUBC_INTR) { + /* Read MSS_HUB_HUBC_INTSTATUS_0 from block mc_hubc_aperture_number */ + intstat =3D mc_ch_readl(mc, mc_hubc_aperture_number, MSS_HUB_HUBC_INTSTA= TUS_0); + if (intstat !=3D 0) { + dev_err_ratelimited(mc->dev, "Scrubber operation status: 0x%lx\n", + intstat); + /* Clear hubc interrupt */ + mc_ch_writel(mc, mc_hubc_aperture_number, intstat, + MSS_HUB_HUBC_INTSTATUS_0); + } + } + + hub_interrupt =3D (global_intstat & MSS_HUB_GLOBAL_MASK) >> MSS_HUB_GLOBA= L_SHIFT; + /* Handle interrupt from hub */ + for_each_set_bit(hub, &hub_interrupt, 32) { + /* Read MSS_HUB_INTRSTATUS_0 from block MCi */ + intstat =3D mc_ch_readl(mc, hub, MSS_HUB_INTRSTATUS_0); + if (intstat !=3D 0) + hub_log_fault(mc, hub, intstat); + } + + /* Clear global interrupt status register */ + mc_ch_writel(mc, mc_hubc_aperture_number, global_intstat, MSS_HUB_GLOBAL_= INTSTATUS_0); + return IRQ_HANDLED; +} + +static irqreturn_t handle_disp_hub_irq(int irq, void *data) +{ + return handle_hub_irq(irq, data, mc_hubc_aperture_number[0]); +} + +static irqreturn_t handle_system_hub_irq(int irq, void *data) +{ + return handle_hub_irq(irq, data, mc_hubc_aperture_number[1]); +} + +static irqreturn_t handle_vision_hub_irq(int irq, void *data) +{ + return handle_hub_irq(irq, data, mc_hubc_aperture_number[2]); +} + +static irqreturn_t handle_uphy_hub_irq(int irq, void *data) +{ + return handle_hub_irq(irq, data, mc_hubc_aperture_number[3]); +} + +static irqreturn_t handle_top_hub_irq(int irq, void *data) +{ + return handle_hub_irq(irq, data, mc_hubc_aperture_number[4]); +} + +static irqreturn_t handle_generic_irq(struct tegra_mc *mc, unsigned long i= ntstat_reg) +{ + u32 intstat, i; + + /* Iterate over all MC blocks to read INTSTATUS */ + for (i =3D 0; i < mc->num_channels; i++) { + intstat =3D mc_ch_readl(mc, i, intstat_reg); + if (intstat) { + dev_err_ratelimited(mc->dev, "channel: %i status: 0x%x\n", i, intstat); + /* Clear interrupt */ + mc_ch_writel(mc, i, intstat, intstat_reg); + } + } + + return IRQ_HANDLED; +} + +static irqreturn_t handle_sbs_irq(int irq, void *data) +{ + return handle_generic_irq((struct tegra_mc *)data, MSS_SBS_INTSTATUS_0); +} + +static irqreturn_t handle_channel_irq(int irq, void *data) +{ + return handle_generic_irq((struct tegra_mc *)data, MC_CH_INTSTATUS_0); +} + +static const irq_handler_t tegra264_mc_irq_handlers[8] =3D { + handle_mcf_irq, handle_disp_hub_irq, handle_vision_hub_irq, + handle_system_hub_irq, handle_uphy_hub_irq, handle_top_hub_irq, + handle_sbs_irq, handle_channel_irq +}; + +static const struct tegra_mc_ops tegra264_mc_ops =3D { + .probe =3D tegra186_mc_probe, + .remove =3D tegra186_mc_remove, + .probe_device =3D tegra186_mc_probe_device, + .resume =3D tegra186_mc_resume, + .handle_irq =3D tegra264_mc_irq_handlers, + .num_interrupts =3D ARRAY_SIZE(tegra264_mc_irq_handlers), +}; + static const struct tegra_mc_icc_ops tegra264_mc_icc_ops =3D { .xlate =3D tegra_mc_icc_xlate, .aggregate =3D tegra264_mc_icc_aggregate, @@ -290,18 +639,80 @@ static const struct tegra_mc_icc_ops tegra264_mc_icc_= ops =3D { .set =3D tegra264_mc_icc_set, }; =20 +static const struct tegra_mc_regs tegra264_mc_regs =3D { + .cfg_channel_enable =3D 0x8870, + .err_status =3D 0xbc00, + .err_add =3D 0xbc04, + .err_add_hi =3D 0xbc08, + .err_vpr_status =3D 0xbc20, + .err_vpr_add =3D 0xbc24, + .err_sec_status =3D 0xbc3c, + .err_sec_add =3D 0xbc40, + .err_mts_status =3D 0xbc5c, + .err_mts_add =3D 0xbc60, + .err_gen_co_status =3D 0xbc78, + .err_gen_co_add =3D 0xbc7c, + .err_route_status =3D 0xbc64, + .err_route_add =3D 0xbc68, +}; + +static const struct tegra_mc_intmask tegra264_mc_intmasks[] =3D { + { + .reg =3D MCF_INTMASK_0, + .mask =3D MC_INT_DECERR_ROUTE_SANITY_GIC_MSI | MC_INT_DECERR_ROUTE_SANIT= Y | + MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | MC_INT_SECURITY_VIOLATION | + MC_INT_DECERR_EMEM, + }, + { + .reg =3D MCF_INTPRIORITY_0, + .mask =3D MC_INT_DECERR_ROUTE_SANITY_GIC_MSI | MC_INT_DECERR_ROUTE_SANIT= Y | + MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | MC_INT_SECURITY_VIOLATION | + MC_INT_DECERR_EMEM, + }, + { + .reg =3D MSS_HUB_INTRMASK_0, + .mask =3D MSS_HUB_COALESCER_ERR_INTMASK | MSS_HUB_SMMU_BYPASS_ALLOW_ERR_= INTMASK | + MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK | MSS_HUB_MSI_ERR_INTMASK | + MSS_HUB_POISON_RSP_INTMASK | MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK | + MSS_HUB_RESERVED_PA_ERR_INTMASK, + }, + { + .reg =3D MSS_HUB_INTRPRIORITY_0, + .mask =3D MSS_HUB_COALESCER_ERR_INTMASK | MSS_HUB_SMMU_BYPASS_ALLOW_ERR_= INTMASK | + MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK | MSS_HUB_MSI_ERR_INTMASK | + MSS_HUB_POISON_RSP_INTMASK | MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK | + MSS_HUB_RESERVED_PA_ERR_INTMASK, + }, + { + .reg =3D MSS_HUB_HUBC_INTMASK_0, + .mask =3D MSS_HUB_HUBC_SCRUB_DONE_INTMASK, + }, + { + .reg =3D MSS_HUB_HUBC_INTPRIORITY_0, + .mask =3D MSS_HUB_HUBC_SCRUB_DONE_INTMASK, + }, + { + .reg =3D MSS_SBS_INTMASK_0, + .mask =3D MSS_SBS_FILL_FIFO_ISO_OVERFLOW_INTMASK | + MSS_SBS_FILL_FIFO_SISO_OVERFLOW_INTMASK | + MSS_SBS_FILL_FIFO_NISO_OVERFLOW_INTMASK, + }, + { + .reg =3D MC_CH_INTMASK_0, + .mask =3D WCAM_ERR_INTMASK, + } +}; + const struct tegra_mc_soc tegra264_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra264_mc_clients), .clients =3D tegra264_mc_clients, .num_address_bits =3D 40, .num_channels =3D 16, .client_id_mask =3D 0x1ff, - .intmask =3D MC_INT_DECERR_ROUTE_SANITY | - MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | - MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | - MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .has_addr_hi_reg =3D true, - .ops =3D &tegra186_mc_ops, + .ops =3D &tegra264_mc_ops, .icc_ops =3D &tegra264_mc_icc_ops, .ch_intmask =3D 0x0000ff00, .global_intstatus_channel_shift =3D 8, @@ -310,4 +721,9 @@ const struct tegra_mc_soc tegra264_mc_soc =3D { * supported. */ .num_carveouts =3D 32, + .regs =3D &tegra264_mc_regs, + .mc_addr_hi_mask =3D 0xff, + .mc_err_status_type_mask =3D (0x3 << 28), + .intmasks =3D tegra264_mc_intmasks, + .num_intmasks =3D ARRAY_SIZE(tegra264_mc_intmasks), }; diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index 3f3c7d996b49..936f127b6f4f 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -1384,6 +1384,14 @@ static const struct tegra_mc_icc_ops tegra30_mc_icc_= ops =3D { .set =3D tegra30_mc_icc_set, }; =20 +static const struct tegra_mc_intmask tegra30_mc_intmasks[] =3D { + { + .reg =3D MC_INTMASK, + .mask =3D MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION | + MC_INT_DECERR_EMEM, + }, +}; + const struct tegra_mc_soc tegra30_mc_soc =3D { .clients =3D tegra30_mc_clients, .num_clients =3D ARRAY_SIZE(tegra30_mc_clients), @@ -1393,12 +1401,13 @@ const struct tegra_mc_soc tegra30_mc_soc =3D { .smmu =3D &tegra30_smmu_soc, .emem_regs =3D tegra30_mc_emem_regs, .num_emem_regs =3D ARRAY_SIZE(tegra30_mc_emem_regs), - .intmask =3D MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION | - MC_INT_DECERR_EMEM, + .intmasks =3D tegra30_mc_intmasks, + .num_intmasks =3D ARRAY_SIZE(tegra30_mc_intmasks), .reset_ops =3D &tegra_mc_reset_ops_common, .resets =3D tegra30_mc_resets, .num_resets =3D ARRAY_SIZE(tegra30_mc_resets), .icc_ops =3D &tegra30_mc_icc_ops, .ops =3D &tegra30_mc_ops, .regs =3D &tegra20_mc_regs, + .mc_err_status_type_mask =3D (0x7 << 28), }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 89f94abfaada..f263eb5b446c 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -187,6 +187,11 @@ struct tegra_mc_regs { unsigned int err_route_add; }; =20 +struct tegra_mc_intmask { + u32 reg; + u32 mask; +}; + struct tegra_mc_soc { const struct tegra_mc_client *clients; unsigned int num_clients; @@ -204,7 +209,6 @@ struct tegra_mc_soc { =20 const struct tegra_smmu_soc *smmu; =20 - u32 intmask; u32 ch_intmask; u32 global_intstatus_channel_shift; bool has_addr_hi_reg; @@ -216,6 +220,10 @@ struct tegra_mc_soc { const struct tegra_mc_icc_ops *icc_ops; const struct tegra_mc_ops *ops; const struct tegra_mc_regs *regs; + unsigned int mc_addr_hi_mask; + unsigned int mc_err_status_type_mask; + const struct tegra_mc_intmask *intmasks; + const unsigned int num_intmasks; }; =20 struct tegra_mc { --=20 2.17.1