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Fri, 30 Jan 2026 06:34:59 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:bd64:2984:fe71:7633]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-658b4256a92sm4268188a12.5.2026.01.30.06.34.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jan 2026 06:34:58 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH] clk: renesas: rzg2l: Drop DMA driver dependency for system boot Date: Fri, 30 Jan 2026 14:34:49 +0000 Message-ID: <20260130143456.256813-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Biju Das As per section 4.6.1.7.1 of the RZ/G3L hardware manual "Precaution when use the peripheral modules which can initiate DMA Controller", it is stated that it needs the below register settings even if DMA controller is not used: - Set CPG_CLKON_DMAC_REG register to supply a clock for DMA Controller. - Set CPG_RST_DMAC register to release a reset for DMA Controller. Currently, the serial IRQ is not routed to the CPU if the DMA ACLK is off, or if DMA resets being in the asserted state result in not getting serial IRQs for the console. Fix the issue by explicitly deasserting the DMA resets during probe, and since the DMA clk is a critical clock, it will be turned on forever. This will allow booting system without DMA driver. RZ/G2L SoC loses power during s2ram. Explicitly turn on clk/deassert resets to get the console during wakeup. The DMA driver is used by both RZ/G2L and RZ/V2H family SoCs. The latter does not have any issue related to serial IRQ routing. The reset assert in DMA driver will impact wakeup using serial IRQ on RZ/G2L SoCs. The cpg_suspend() is suspend-no-irq which suspends later than DMA driver. So, deassert thereset in cpg_suspend() for making available the serial IRQ as a wakeup source for s2idle. With these changes, the RZ/G2L-based systems: =C2=A01) can boot without the DMA driver =C2=A02) get serial IRQ available as wakeup source for s2idle =C2=A03) get serial console prompt during wakeup of s2ram. =C2=A04) has no dependency on bootloaders for turning on DMA clks/releasing =C2=A0 the resets. Signed-off-by: Biju Das --- drivers/clk/renesas/rzg2l-cpg.c | 35 ++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index f4deb5d3b837..16771a0101bd 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -86,6 +86,12 @@ #define PLL5_HSCLK_MIN 10000000 #define PLL5_HSCLK_MAX 187500000 =20 +/* Critical clk/resets to route serial IRQ to CPU by default */ +#define CPG_CLKON_DMAC_REG 0x52c +#define CPG_RST_DMAC 0x82c +#define CPG_CLKON_DMAC_REG_ACLK_ON ((BIT(0) << 16) | BIT(0)) +#define CPG_RST_DMAC_DEASSERTED_ALL ((GENMASK(1, 0) << 16) | GENMASK(1, 0)) + /** * struct clk_hw_data - clock hardware data * @hw: clock hw @@ -2051,21 +2057,48 @@ static int __init rzg2l_cpg_probe(struct platform_d= evice *pdev) if (error) return error; =20 + /* + * Deassert DMA resets to route the serial IRQ to CPU for serial + * console during boot. DMA clk is critical clk and it will be + * turned on forever. + */ + writel(CPG_RST_DMAC_DEASSERTED_ALL, priv->base + CPG_RST_DMAC); + debugfs_create_file("mstop", 0444, NULL, priv, &rzg2l_mod_clock_mstop_fop= s); return 0; } =20 +static int rzg2l_cpg_suspend(struct device *dev) +{ + struct rzg2l_cpg_priv *priv =3D dev_get_drvdata(dev); + + /* + * Deassert DMA resets to route the serial IRQ to CPU for making + * serial IRQ available as wakeup source for s2idle. + */ + writel(CPG_RST_DMAC_DEASSERTED_ALL, priv->base + CPG_RST_DMAC); + return 0; +} + static int rzg2l_cpg_resume(struct device *dev) { struct rzg2l_cpg_priv *priv =3D dev_get_drvdata(dev); =20 rzg2l_mod_clock_init_mstop(priv); =20 + /* + * Deassert DMA resets and enable clk to route serial IRQ to CPU for + * serial console during wakeup from s2ram as the SoC is in DDR + * retention mode. + */ + writel(CPG_CLKON_DMAC_REG_ACLK_ON, priv->base + CPG_CLKON_DMAC_REG); + writel(CPG_RST_DMAC_DEASSERTED_ALL, priv->base + CPG_RST_DMAC); + return 0; } =20 static const struct dev_pm_ops rzg2l_cpg_pm_ops =3D { - NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, rzg2l_cpg_resume) + NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_cpg_suspend, rzg2l_cpg_resume) }; =20 static const struct of_device_id rzg2l_cpg_match[] =3D { --=20 2.43.0