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Peter Anvin" , Peter Zijlstra , Pawan Gupta , Josh Poimboeuf , linux-kernel@vger.kernel.org, Joongsun Moon-Lee Subject: [PATCH v2 2/2] x86/cpu/intel: Add implicit RFDS mitigation for Goldmont and Tremont-D Date: Fri, 30 Jan 2026 21:33:40 +0900 Message-ID: <20260130123340.1544-3-moontorise@cfg.kr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260130123340.1544-1-moontorise@cfg.kr> References: <20260129154342.3867-1-moontorise@cfg.kr> <20260130123340.1544-1-moontorise@cfg.kr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Goldmont and Tremont-D CPUs support RFDS mitigation via VERW but do not enumerate the RFDS_CLEAR bit in the IA32_ARCH_CAPABILITIES MSR. Force X86_FEATURE_RFDS_CLEAR for these models in init_intel() to enable the mitigation automatically. For Tremont-D, limit the quirk to stepping 7, as stepping 5 does not support mitigation according to Intel's guidance [1]. To ensure safety, only enable this quirk when X86_BUG_OLD_MICROCODE is not set, guaranteeing the microcode implements the VERW side-effect. Verification was performed on an Intel NUC8CCHKR (Celeron N3350 / Goldmont) with microcode 0x48, confirming the status change from "Vulnerable: No microcode" to "Mitigation: Clear Register File". [1] https://www.intel.com/content/www/us/en/developer/topic-technology/soft= ware-security-guidance/processors-affected-consolidated-product-cpu-model.h= tml#tab-blade-1-1 Suggested-by: Dave Hansen Link: https://lore.kernel.org/all/20260129154342.3867-1-moontorise@cfg.kr/ Signed-off-by: Joongsun Moon-Lee --- arch/x86/kernel/cpu/intel.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 646ff33c4651..9867ca383621 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -531,6 +531,16 @@ static const struct x86_cpu_id zmm_exclusion_list[] = =3D { {}, }; =20 +/* + * These CPUs mitigate RFDS via VERW but do not enumerate the RFDS_CLEAR b= it + * in IA32_ARCH_CAPABILITIES MSR. + */ +static const struct x86_cpu_id implicit_rfds_list[] =3D { + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, 0), + X86_MATCH_VFM_STEPS(INTEL_ATOM_TREMONT_D, 7, 7, 0), + {}, +}; + static void init_intel(struct cpuinfo_x86 *c) { early_init_intel(c); @@ -612,6 +622,10 @@ static void init_intel(struct cpuinfo_x86 *c) if (x86_match_cpu(zmm_exclusion_list)) set_cpu_cap(c, X86_FEATURE_PREFER_YMM); =20 + if (x86_match_cpu(implicit_rfds_list) && + !boot_cpu_has_bug(X86_BUG_OLD_MICROCODE)) + setup_force_cpu_cap(X86_FEATURE_RFDS_CLEAR); + /* Work around errata */ srat_detect_node(c); =20 --=20 2.52.0