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Peter Anvin" , Peter Zijlstra , Pawan Gupta , Josh Poimboeuf , linux-kernel@vger.kernel.org, Joongsun Moon-Lee Subject: [PATCH v2 1/2] x86/cpu: Refactor RFDS mitigation to use X86_FEATURE_RFDS_CLEAR Date: Fri, 30 Jan 2026 21:33:39 +0900 Message-ID: <20260130123340.1544-2-moontorise@cfg.kr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260130123340.1544-1-moontorise@cfg.kr> References: <20260129154342.3867-1-moontorise@cfg.kr> <20260130123340.1544-1-moontorise@cfg.kr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current RFDS mitigation logic relies on verw_clears_cpu_reg_file(), which directly checks the RFDS_CLEAR bit in the IA32_ARCH_CAPABILITIES MSR. To support quirks for CPUs that mitigate RFDS but do not enumerate it, transition to using the synthetic feature flag X86_FEATURE_RFDS_CLEAR. Replace the MSR-bit-based check with boot_cpu_has(X86_FEATURE_RFDS_CLEAR) and synthesize this feature bit in rfds_select_mitigation() if the architectural RFDS_CLEAR bit is present. Suggested-by: Dave Hansen Link: https://lore.kernel.org/all/20260129154342.3867-1-moontorise@cfg.kr/ Signed-off-by: Joongsun Moon-Lee --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/bugs.c | 12 +++++------- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 63b0f9aa9b3e..3480d9ddc046 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -513,6 +513,7 @@ * and purposes if CLEAR_CPU_BUF_VM is set). */ #define X86_FEATURE_X2AVIC_EXT (21*32+20) /* AMD SVM x2AVIC support for 4= k vCPUs */ +#define X86_FEATURE_RFDS_CLEAR (21*32+21) /* Clear register file via VERW= */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 83f51cab0b1e..479702bc9c00 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -648,11 +648,6 @@ static const char * const rfds_strings[] =3D { [RFDS_MITIGATION_UCODE_NEEDED] =3D "Vulnerable: No microcode", }; =20 -static inline bool __init verw_clears_cpu_reg_file(void) -{ - return (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR); -} - static void __init rfds_select_mitigation(void) { if (!boot_cpu_has_bug(X86_BUG_RFDS)) { @@ -670,7 +665,10 @@ static void __init rfds_select_mitigation(void) if (rfds_mitigation =3D=3D RFDS_MITIGATION_OFF) return; =20 - if (verw_clears_cpu_reg_file()) + if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR) + setup_force_cpu_cap(X86_FEATURE_RFDS_CLEAR); + + if (boot_cpu_has(X86_FEATURE_RFDS_CLEAR)) verw_clear_cpu_buf_mitigation_selected =3D true; } =20 @@ -683,7 +681,7 @@ static void __init rfds_update_mitigation(void) rfds_mitigation =3D RFDS_MITIGATION_VERW; =20 if (rfds_mitigation =3D=3D RFDS_MITIGATION_VERW) { - if (!verw_clears_cpu_reg_file()) + if (!boot_cpu_has(X86_FEATURE_RFDS_CLEAR)) rfds_mitigation =3D RFDS_MITIGATION_UCODE_NEEDED; } =20 --=20 2.52.0 From nobody Sun Feb 8 17:03:57 2026 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BF2323EAA1 for ; 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Fri, 30 Jan 2026 04:33:58 -0800 (PST) Received: from cfg.kr ([211.244.25.5]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-82379b1bc1asm8436249b3a.9.2026.01.30.04.33.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jan 2026 04:33:58 -0800 (PST) From: Joongsun Moon-Lee To: x86@kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen Cc: "H . Peter Anvin" , Peter Zijlstra , Pawan Gupta , Josh Poimboeuf , linux-kernel@vger.kernel.org, Joongsun Moon-Lee Subject: [PATCH v2 2/2] x86/cpu/intel: Add implicit RFDS mitigation for Goldmont and Tremont-D Date: Fri, 30 Jan 2026 21:33:40 +0900 Message-ID: <20260130123340.1544-3-moontorise@cfg.kr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260130123340.1544-1-moontorise@cfg.kr> References: <20260129154342.3867-1-moontorise@cfg.kr> <20260130123340.1544-1-moontorise@cfg.kr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Goldmont and Tremont-D CPUs support RFDS mitigation via VERW but do not enumerate the RFDS_CLEAR bit in the IA32_ARCH_CAPABILITIES MSR. Force X86_FEATURE_RFDS_CLEAR for these models in init_intel() to enable the mitigation automatically. For Tremont-D, limit the quirk to stepping 7, as stepping 5 does not support mitigation according to Intel's guidance [1]. To ensure safety, only enable this quirk when X86_BUG_OLD_MICROCODE is not set, guaranteeing the microcode implements the VERW side-effect. Verification was performed on an Intel NUC8CCHKR (Celeron N3350 / Goldmont) with microcode 0x48, confirming the status change from "Vulnerable: No microcode" to "Mitigation: Clear Register File". [1] https://www.intel.com/content/www/us/en/developer/topic-technology/soft= ware-security-guidance/processors-affected-consolidated-product-cpu-model.h= tml#tab-blade-1-1 Suggested-by: Dave Hansen Link: https://lore.kernel.org/all/20260129154342.3867-1-moontorise@cfg.kr/ Signed-off-by: Joongsun Moon-Lee --- arch/x86/kernel/cpu/intel.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 646ff33c4651..9867ca383621 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -531,6 +531,16 @@ static const struct x86_cpu_id zmm_exclusion_list[] = =3D { {}, }; =20 +/* + * These CPUs mitigate RFDS via VERW but do not enumerate the RFDS_CLEAR b= it + * in IA32_ARCH_CAPABILITIES MSR. + */ +static const struct x86_cpu_id implicit_rfds_list[] =3D { + X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, 0), + X86_MATCH_VFM_STEPS(INTEL_ATOM_TREMONT_D, 7, 7, 0), + {}, +}; + static void init_intel(struct cpuinfo_x86 *c) { early_init_intel(c); @@ -612,6 +622,10 @@ static void init_intel(struct cpuinfo_x86 *c) if (x86_match_cpu(zmm_exclusion_list)) set_cpu_cap(c, X86_FEATURE_PREFER_YMM); =20 + if (x86_match_cpu(implicit_rfds_list) && + !boot_cpu_has_bug(X86_BUG_OLD_MICROCODE)) + setup_force_cpu_cap(X86_FEATURE_RFDS_CLEAR); + /* Work around errata */ srat_detect_node(c); =20 --=20 2.52.0