From nobody Tue Feb 10 08:26:56 2026 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08C26371057 for ; Fri, 30 Jan 2026 11:58:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769774338; cv=none; b=mLxKtu85MwlOIB3rmSRtpMCLE8CBko8VAgaJXnAoiXxWPbQVS5Qaepvvz8C1l/OQeiRQ2p3hFyaU0RBnhe2B9dzB2ZjifN71DUsj+6IIUC111Xvs3CEbwCbgtXsUH9VZXMZpM492rkfb1l7ZoCoR/1nH3x0479Akcr7U5SPmB5k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769774338; c=relaxed/simple; bh=Wt36PN5bHjGIsRQN727yxFJttOtyQJFgvRYzNsGZ+a8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SpL8dP11u4PvReZ1N0HH/7C/pCgF01t9k/wWuhpV9OO9vuuUTNLN6DGUggT6tkm9fsvIIMx1aYjfxQfAPqfrz7H7nht0kSVjqKFhc8mVsb8s1+tWjILmYGiJs/YfpmgwOkDgfQ3qzQzPDNzC10lzM8cu3FGUkUJv9RHuae2r9wk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=bo6JAlP/; arc=none smtp.client-ip=209.85.208.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bo6JAlP/" Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-65812261842so4675398a12.1 for ; Fri, 30 Jan 2026 03:58:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769774334; x=1770379134; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=na+ZDw0eAD/iSJmU7KFtSfYJdxr1nTFE8Fh4OeAd1ss=; b=bo6JAlP/ry7dpAEeJEZAviKVOtOi8llSR60XOIIJ0EGyrnWcJo4joG6BL+BAGdIqW/ a60Ps/K1HtXREqjiJO7eNopTOpAOkhj/CBS7mNx7fr9ad+OjHKKu3cOG7511uJDaiNIl UtWsyiDMGKryyB5X+BBbXSBF+aKJ8du1oikSmnUxPVFLPjigwHhBhSVAhdfjFYaH+WZu 5hy+wCGpVf6swijZ3OMqJXfc7Awd/ou/eF/6mleMHzg7Lo3sjuytHHgBNizQ1AMiS45A /W0jkmHoafvjxQAV2YsoxcyN/m2OMTrSEirmYIu276v5S+EREn6riW7ZTLGoGpH9G1nb 7h+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769774334; x=1770379134; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=na+ZDw0eAD/iSJmU7KFtSfYJdxr1nTFE8Fh4OeAd1ss=; b=SEbJzelhqbo/jQpaY3Hy5CIehMuavzJAwSPTstMe8kBEbPj43z7tztwFZnikbAClt6 NfAJ0zHSaapJ8MMj7GEhIZ7JSXr8RZs362fprP4fZ1hlftLCXvgZCdG3UASWXPVlJuTK QyOakb/dJaw53tJO754tTh0X1Mk5an6CkOJJXx7cz1k0uUaij4rSSTMA04Mh/+7GKtRR zH4O2+7FNaEOhQyVanBq87LYeEIRxUUSgRUIKF/d4Ew10XeduJhRQeCGE07vLORwuorI 4rCinAAVO6ysBS2DwTciYNPO5Bip4SN1DJrshuUdgJOVxepOiBHTqHSQAykSPGfXpHB6 1x9Q== X-Forwarded-Encrypted: i=1; AJvYcCXI1A8MQYAi34BdN7eVBzJtWORM4ngBd6TD5sGdTnQwnkX1gT3FL+QHDfkd7IZhomZcVhIycSS9J4av8Pk=@vger.kernel.org X-Gm-Message-State: AOJu0Yxvpq7dUxnzJKwcV9kEbLUAbmvaJCKfk7DPNhE5b8SZH5mpr764 QYOpPgmCVGqbc5PcUcioqQn9jKMsSppZ8dt/3oGz6OQqmWWF7FEe2gAL X-Gm-Gg: AZuq6aLcynurblS+ZJDMTQZ9MFpwR+g31pFKvtoQ23V6O0KTVcj8hmU7i52NMzK1z4r UfPlrMgqabR1A8vBJRhew+shYyF0olpQhO5bzoMeb7OrUOIZCMnnccivvITFwVwcNS5Xe6IN+Kw Xc5AYi763HwHwyfrl56U53i4eyuR5x43lm0M/Kw4eZsjJ31vgcuGJ3ThMNk23YXgqWtPlqeOswT 0Yx94HFgsnX09uIpFRQgx1gLzRBr+ycNPJEIm/T3n8baR1f94aW6nR5acB3dfZM/5grNrWekSkX p2DvYU9D063q6PmX+Ji8MgyV+BIhM7YTVrU8ySjkss7PUDpId8PaWiEKMqK1FPTNBG9Jnx1DQIZ fnwdqQ8DGR8y3O91TIbY2fVsZumQTQaJml3XOFbunqmJSSJmA/oZWMUNHXgzF2dsAAkkdsb9A/O M64CjAr5spGJDGi58KIKCqH2gTAAcwiIpC7uE= X-Received: by 2002:a17:907:2d0e:b0:b88:1e2:ed49 with SMTP id a640c23a62f3a-b8dff22f549mr177830866b.8.1769774334208; Fri, 30 Jan 2026 03:58:54 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:bd64:2984:fe71:7633]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbeffed15sm404671566b.31.2026.01.30.03.58.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jan 2026 03:58:53 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 4/4] clk: renesas: r9a08g046: Add clock and reset signals for the GBETH IPs Date: Fri, 30 Jan 2026 11:58:45 +0000 Message-ID: <20260130115850.253555-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260130115850.253555-1-biju.das.jz@bp.renesas.com> References: <20260130115850.253555-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1) IPs found on the RZ/G3L SoC. This includes various dividers and mux clocks needed by these two GBETH IPs. Signed-off-by: Biju Das --- v1->v2: * No change --- drivers/clk/renesas/r9a08g046-cpg.c | 114 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 6 ++ 2 files changed, 120 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index cc7d3872e9e4..e74bab2df29a 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -18,17 +18,35 @@ #define G3L_CPG_PL2_DDIV (0x204) #define G3L_CPG_PL3_DDIV (0x208) #define G3L_CLKDIVSTATUS (0x280) +#define G3L_CPG_ETH_SSEL (0x410) +#define G3L_CPG_ETH_SDIV (0x434) =20 /* RZ/G3L Specific division configuration. */ #define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2) #define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2) #define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2) +#define G3L_SDIV_ETH_A DDIV_PACK(G3L_CPG_ETH_SDIV, 0, 2) +#define G3L_SDIV_ETH_B DDIV_PACK(G3L_CPG_ETH_SDIV, 4, 1) +#define G3L_SDIV_ETH_C DDIV_PACK(G3L_CPG_ETH_SDIV, 8, 2) +#define G3L_SDIV_ETH_D DDIV_PACK(G3L_CPG_ETH_SDIV, 12, 1) =20 /* RZ/G3L Clock status configuration. */ #define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1) #define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1) #define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1) =20 +/* RZ/G3L Specific clocks select. */ +#define G3L_SEL_ETH0_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 0, 1) +#define G3L_SEL_ETH0_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 1, 1) +#define G3L_SEL_ETH0_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 2, 1) +#define G3L_SEL_ETH0_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 3, 1) +#define G3L_SEL_ETH0_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 4, 1) +#define G3L_SEL_ETH1_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 8, 1) +#define G3L_SEL_ETH1_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 9, 1) +#define G3L_SEL_ETH1_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 10, 1) +#define G3L_SEL_ETH1_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 11, 1) +#define G3L_SEL_ETH1_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 12, 1) + /* PLL 1/4/6/7 configuration registers macro. */ #define G3L_PLL1467_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12= | (setting)) =20 @@ -49,12 +67,29 @@ enum clk_ids { CLK_PLL3, CLK_PLL3_DIV2, CLK_PLL6, + CLK_PLL6_DIV10, + CLK_SEL_ETH0_TX, + CLK_SEL_ETH0_RX, + CLK_SEL_ETH0_RM, + CLK_SEL_ETH1_TX, + CLK_SEL_ETH1_RX, + CLK_SEL_ETH1_RM, + CLK_ETH0_TR, + CLK_ETH0_RM, + CLK_ETH1_TR, + CLK_ETH1_RM, =20 /* Module Clocks */ MOD_CLK_BASE, }; =20 /* Divider tables */ +static const struct clk_div_table dtable_2_20[] =3D { + { 0, 2 }, + { 1, 20 }, + { 0, 0 }, +}; + static const struct clk_div_table dtable_4_128[] =3D { { 0, 4 }, { 1, 2 }, @@ -63,6 +98,13 @@ static const struct clk_div_table dtable_4_128[] =3D { { 0, 0 }, }; =20 +static const struct clk_div_table dtable_4_200[] =3D { + { 0, 4 }, + { 1, 20 }, + { 2, 200 }, + { 0, 0 }, +}; + static const struct clk_div_table dtable_8_256[] =3D { { 0, 8 }, { 1, 16 }, @@ -71,6 +113,18 @@ static const struct clk_div_table dtable_8_256[] =3D { { 0, 0 }, }; =20 +/* Mux clock names tables. */ +static const char * const sel_eth0_tx[] =3D { ".div_eth0_tr", "eth0_txc_tx= _clk" }; +static const char * const sel_eth0_rx[] =3D { ".div_eth0_tr", "eth0_rxc_rx= _clk" }; +static const char * const sel_eth0_rm[] =3D { ".pll6_div10", "eth0_rxc_rx_= clk" }; +static const char * const sel_eth1_tx[] =3D { ".div_eth1_tr", "eth1_txc_tx= _clk" }; +static const char * const sel_eth1_rx[] =3D { ".div_eth1_tr", "eth1_rxc_rx= _clk" }; +static const char * const sel_eth1_rm[] =3D { ".pll6_div10", "eth1_rxc_rx_= clk" }; +static const char * const sel_eth0_clk_tx_i[] =3D { ".sel_eth0_tx", ".div_= eth0_rm" }; +static const char * const sel_eth0_clk_rx_i[] =3D { ".sel_eth0_rx", ".div_= eth0_rm" }; +static const char * const sel_eth1_clk_tx_i[] =3D { ".sel_eth1_tx", ".div_= eth1_rm" }; +static const char * const sel_eth1_clk_rx_i[] =3D { ".sel_eth1_rx", ".div_= eth1_rm" }; + static const struct cpg_core_clk r9a08g046_core_clks[] __initconst =3D { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -86,6 +140,17 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { 500000000UL), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll6_div10", CLK_PLL6_DIV10, CLK_PLL6, 1, 10), + DEF_MUX(".sel_eth0_tx", CLK_SEL_ETH0_TX, G3L_SEL_ETH0_TX, sel_eth0_tx), + DEF_MUX(".sel_eth0_rx", CLK_SEL_ETH0_RX, G3L_SEL_ETH0_RX, sel_eth0_rx), + DEF_MUX(".sel_eth0_rm", CLK_SEL_ETH0_RM, G3L_SEL_ETH0_RM, sel_eth0_rm), + DEF_MUX(".sel_eth1_tx", CLK_SEL_ETH1_TX, G3L_SEL_ETH1_TX, sel_eth1_tx), + DEF_MUX(".sel_eth1_rx", CLK_SEL_ETH1_RX, G3L_SEL_ETH1_RX, sel_eth1_rx), + DEF_MUX(".sel_eth1_rm", CLK_SEL_ETH1_RM, G3L_SEL_ETH1_RM, sel_eth1_rm), + DEF_DIV(".div_eth0_tr", CLK_ETH0_TR, CLK_PLL6, G3L_SDIV_ETH_A, dtable_4_2= 00), + DEF_DIV(".div_eth1_tr", CLK_ETH1_TR, CLK_PLL6, G3L_SDIV_ETH_C, dtable_4_2= 00), + DEF_DIV(".div_eth0_rm", CLK_ETH0_RM, CLK_SEL_ETH0_RM, G3L_SDIV_ETH_B, dta= ble_2_20), + DEF_DIV(".div_eth1_rm", CLK_ETH1_RM, CLK_SEL_ETH1_RM, G3L_SDIV_ETH_D, dta= ble_2_20), =20 /* Core output clk */ DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL= 2B_STS, @@ -94,6 +159,21 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { dtable_4_128, 0, 0, 0, NULL), DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL= 2A_STS, dtable_4_128, 0, 0, 0, NULL), + DEF_FIXED("HP", R9A08G046_CLK_HP, CLK_PLL6_DIV10, 1, 1), + DEF_MUX_FLAGS("ETHTX01", R9A08G046_CLK_ETHTX01, G3L_SEL_ETH0_CLK_TX_I, se= l_eth0_clk_tx_i, + CLK_SET_RATE_PARENT), + DEF_MUX_FLAGS("ETHRX01", R9A08G046_CLK_ETHRX01, G3L_SEL_ETH0_CLK_RX_I, se= l_eth0_clk_rx_i, + CLK_SET_RATE_PARENT), + DEF_MUX_FLAGS("ETHTX11", R9A08G046_CLK_ETHTX11, G3L_SEL_ETH1_CLK_TX_I, se= l_eth1_clk_tx_i, + CLK_SET_RATE_PARENT), + DEF_MUX_FLAGS("ETHRX11", R9A08G046_CLK_ETHRX11, G3L_SEL_ETH1_CLK_RX_I, se= l_eth1_clk_rx_i, + CLK_SET_RATE_PARENT), + DEF_FIXED("ETHRM0", R9A08G046_CLK_ETHRM0, CLK_ETH0_RM, 1, 1), + DEF_FIXED("ETHTX02", R9A08G046_CLK_ETHTX02, CLK_SEL_ETH0_TX, 1, 1), + DEF_FIXED("ETHRX02", R9A08G046_CLK_ETHRX02, CLK_SEL_ETH0_RX, 1, 1), + DEF_FIXED("ETHRM1", R9A08G046_CLK_ETHRM1, CLK_ETH1_RM, 1, 1), + DEF_FIXED("ETHTX12", R9A08G046_CLK_ETHTX12, CLK_SEL_ETH1_TX, 1, 1), + DEF_FIXED("ETHRX12", R9A08G046_CLK_ETHRX12, CLK_SEL_ETH1_RX, 1, 1), }; =20 static const struct rzg2l_mod_clk r9a08g046_mod_clks[] =3D { @@ -107,6 +187,38 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[]= =3D { MSTOP(BUS_REG1, BIT(2))), DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1, MSTOP(BUS_REG1, BIT(3))), + DEF_MOD("eth0_clk_axi", R9A08G046_ETH0_CLK_AXI, R9A08G046_CLK_P1, 0x57c,= 0, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_MOD("eth1_clk_axi", R9A08G046_ETH1_CLK_AXI, R9A08G046_CLK_P1, 0x57c,= 1, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_MOD("eth0_clk_chi", R9A08G046_ETH0_CLK_CHI, R9A08G046_CLK_P1, 0x57c,= 2, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_MOD("eth1_clk_chi", R9A08G046_ETH1_CLK_CHI, R9A08G046_CLK_P1, 0x57c,= 3, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth0_tx_i", R9A08G046_ETH0_CLK_TX_I, R9A08G046_CLK_ETHTX01, = 0x57c, 4, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth0_tx_180_i", R9A08G046_ETH0_CLK_TX_180_I, R9A08G046_CLK_E= THTX02, 0x57c, 4, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth1_tx_i", R9A08G046_ETH1_CLK_TX_I, R9A08G046_CLK_ETHTX11, = 0x57c, 5, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_COUPLED("eth1_tx_180_i", R9A08G046_ETH1_CLK_TX_180_I, R9A08G046_CLK_E= THTX12, 0x57c, 5, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_COUPLED("eth0_rx_i", R9A08G046_ETH0_CLK_RX_I, R9A08G046_CLK_ETHRX01, = 0x57c, 6, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth0_rx_180_i", R9A08G046_ETH0_CLK_RX_180_I, R9A08G046_CLK_E= THRX02, 0x57c, 6, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth1_rx_i", R9A08G046_ETH1_CLK_RX_I, R9A08G046_CLK_ETHRX11, = 0x57c, 7, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_COUPLED("eth1_rx_180_i", R9A08G046_ETH1_CLK_RX_180_I, R9A08G046_CLK_E= THRX12, 0x57c, 7, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_MOD("eth0_ptp_ref_i", R9A08G046_ETH0_CLK_PTP_REF_I, R9A08G046_CLK_HP,= 0x57c, 8, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_MOD("eth1_ptp_ref_i", R9A08G046_ETH1_CLK_PTP_REF_I, R9A08G046_CLK_HP,= 0x57c, 9, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_MOD("eth0_rmii_i", R9A08G046_ETH0_CLK_RMII_I, R9A08G046_CLK_ETHRM0, = 0x57c, 10, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_MOD("eth1_rmii_i", R9A08G046_ETH1_CLK_RMII_I, R9A08G046_CLK_ETHRM1, = 0x57c, 11, + MSTOP(BUS_PERI_COM, BIT(3))), DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584= , 0, MSTOP(BUS_MCPU2, BIT(1))), }; @@ -117,6 +229,8 @@ static const struct rzg2l_reset r9a08g046_resets[] =3D { DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0), DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0), + DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1), DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0), }; =20 diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 7de4cb7af1cc..9abb53483759 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -188,6 +188,12 @@ enum clk_types { .parent_names =3D _parent_names, \ .num_parents =3D ARRAY_SIZE(_parent_names), \ .mux_flags =3D CLK_MUX_READ_ONLY) +#define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flag) \ + DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf =3D _conf, \ + .parent_names =3D _parent_names, \ + .num_parents =3D ARRAY_SIZE(_parent_names), \ + .mux_flags =3D CLK_MUX_HIWORD_MASK, \ + .flag =3D _flag) #define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk= _flags, _notifier) \ DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf =3D _conf, .sconf =3D _sconf,= \ .parent_names =3D _parent_names, \ --=20 2.43.0