From nobody Mon Feb 9 14:00:26 2026 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81222301704 for ; Fri, 30 Jan 2026 11:58:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769774335; cv=none; b=I0jHQgXfDMJByvoz5UthDNXo+EBoZWaku6HOJGSRUru36MUyo29NMBts0Y1JV+OY9kCbVvCQbmoNrVBYqXWWl9F03UWXzfUTzo9l1ptF6qXFJigpTXz/N2NZ74gqh/ji3Od1nZYOCBx2DsEQl3yz39cqI7SZDv1tnlOIDRKFZZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769774335; c=relaxed/simple; bh=wUvy3QQiQeAOG1bMC0djoJvJvuxkTXceaEm1ZvLPvV4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u//vEAniyOUu+L2lKKoFioRqG3OOJJf+Izr29G4a4WhK648myHPFqud4UAOs1MnvXzMynl2c/di0FGSqsF1p3O/LK+i73/OL6k7+3mzl7lpTFQ/a/WpPnlqRwg7If/eFRi+jyGURnLxbNWDwFlrTorDp4Pf42t5beqFfs80BZrE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=mSGxCtJ1; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mSGxCtJ1" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-b8845cb5862so310759566b.3 for ; Fri, 30 Jan 2026 03:58:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769774333; x=1770379133; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hrk2D5glHxinFpEivMEobZUHDU8krg32pwTF1WkjNCk=; b=mSGxCtJ1tG4lBO8X8fD6W8fQ3b/pz4jZY3JZk7qNuJxdSLRbFqaQs0NfAsSoSgbh0N ugLJQTxfmr0D2eIR0/+S3pPRDRuFKQpIibCxg0BRAku7WDY/L7EV4L3B5Jsr1qHWKA8a V0gukHT7wYD4JJLGFlNj4TD3QntnSUFLbIR1KqdVYXo/vfutB1lnLwaYUaWUC8MROdYo W1NE3vdfPQukQPV8Qo3SZY6/DejKKLYbvrV3hWW5J+iJp7JD+WtHSF+Og1kYeg7qeZfi O5v1bvkIbp+2lAd8phU0AKlZw6RpPvMBRWbL+sX1N4rbnnxs296WmtVn7sIH05Kccb5q jPiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769774333; x=1770379133; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=hrk2D5glHxinFpEivMEobZUHDU8krg32pwTF1WkjNCk=; b=VfORzOJRM/3WLbwlMN1aHZhrCVwJCz4CghNK0dC9rsVV2v3wys8PhXEjlmcS1rYxb9 sqcDG7UqK5e4X0R/om/ryrn3EEc4FiqPyW0V+QV6YPCEpg/GeQH7sIxIxThWZl4yqcy9 aaMrlQ04jOGrOGdG8Ici7fUnpLJJNbYd/H2jNkwF4SM2m8GkzgLIGbGdO5F/FWs6YJIO V7F1/JnIpL5F6VY28AmD0Ejq9YvJyuKemFc3gmqpJ6C10hupF+orq+AapHIMHjRhOpiz yRQg9iupMW+xMjUAYm838mMMvKwuUJBiyxoV1FAhSq5qaABy03OJYXvBR64YgDhMoHUc W0uA== X-Forwarded-Encrypted: i=1; AJvYcCWHCaT7o4QLBp/DHC7gMX/3DYmA3N0R9K/aPQRAIABUrHTsks/z4zZo+qbdTVou6IAnbUh1ONf1OmCB2MM=@vger.kernel.org X-Gm-Message-State: AOJu0YyKGPgdMNY9oXanG4tpmbI3hfpTSTeHk3mkiABlEnDKgcLLXZZz PYuAcr9IWdz7F4VqmckEjRJMZfwaDegDTDTqIaZDNtLJHf7pI453dpcu X-Gm-Gg: AZuq6aI6Jy058GECFsAvvw4GyJ+KPFd1mYtWdhFoq5BSHdm/gBDpRGcNuxNKwvfogfF cfj2Q8PYVHXBCcn8bdjmXVbG5usZMhPguK9xrJuvwxwnGu7NTUpOuiuf+PACe020rp4BqQoltSa G018c2NBmPckw5ZOc1Ez+aN/sUo3Q8Zbcenb5nbxzGM3mwcmm9+hHwcwPm2+2BGldxiYX1B+YU3 xAzUji1OlgmjrWEyL+khdqLreUmNs1cGj1XqwX63h9j3l4KirsBLAE4lfA2/xo4ug2CsnkrWi1H oPtS1HqvLyPxlmtrIceTkknhB+O3swj/2HgrxJ7BodC91uJVErdOYREx3gY4MA/6pROf7Sdru/p 8n6Ox5pYfiAF7SlhXKgALMTROZaklm8pG1c5LOwbc+/dkDwC3TXurWOzfMrinS+HxAff5Zo56dn bSSpCwzgHs6cGnpGw04uecQ25loc0+vghiZG8= X-Received: by 2002:a17:907:3d43:b0:b84:40e1:c1c8 with SMTP id a640c23a62f3a-b8dff6678c1mr156980666b.33.1769774332758; Fri, 30 Jan 2026 03:58:52 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:bd64:2984:fe71:7633]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbeffed15sm404671566b.31.2026.01.30.03.58.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jan 2026 03:58:52 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 1/4] clk: renesas: rzg2l: Drop a check in rzg3s_cpg_pll_clk_recalc_rate() Date: Fri, 30 Jan 2026 11:58:42 +0000 Message-ID: <20260130115850.253555-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260130115850.253555-1-biju.das.jz@bp.renesas.com> References: <20260130115850.253555-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Drop the unwanted check in rzg3s_cpg_pll_clk_recalc_rate() as the function is SoC specific. Signed-off-by: Biju Das Reviewed-by: Claudiu Beznea --- v1->v2: * No change --- drivers/clk/renesas/rzg2l-cpg.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 16771a0101bd..ee92d07c6ff7 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1113,9 +1113,6 @@ static unsigned long rzg3s_cpg_pll_clk_recalc_rate(st= ruct clk_hw *hw, u32 nir, nfr, mr, pr, val, setting; u64 rate; =20 - if (pll_clk->type !=3D CLK_TYPE_G3S_PLL) - return parent_rate; - setting =3D GET_REG_SAMPLL_SETTING(pll_clk->conf); if (setting) { val =3D readl(priv->base + setting); --=20 2.43.0 From nobody Mon Feb 9 14:00:26 2026 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0B7F36C0BB for ; Fri, 30 Jan 2026 11:58:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769774336; cv=none; b=FLBVrmFP1YKw3r5m3BnFdlmayMBQhuXupZiBpzKma+gRWcLjiD6d9sCXVI0yJlOWUs864NlHk8OPpQ0k/4cB+FbC4arw0mnYKK22AoVgXAuyI6vs2A5z32qx9/GaTBIY4koSJK+hTT3Y13yaXUi7FbAed1gqlYmihctL+lHEr5o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769774336; c=relaxed/simple; bh=RFS3L+HoKH/ZpUq4IYPiZn2EYx+MJ9MMW1dc0w7GCLw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ll9RhevTLPu6cZkl76l6cNp8mh7/tYOFtlZ1RdBByOiFCvlSez74FiRcEmn8A2/L+U5chPijB4L1Ja9sh4ijsnDysYKbPXVxqyxUhx20++wVPjrgYi2INH72n7Bgg0AX2YOZyTMTbG12e8mN0Ox37jmGxjGCBrDASa3G+bu3slg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=aXTiwbgZ; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aXTiwbgZ" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-b8876d1a39bso291593366b.1 for ; Fri, 30 Jan 2026 03:58:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769774333; x=1770379133; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HGMFI6tCot74p730gmYxB0ganfKY4B4oFGS/FHtw0j4=; b=aXTiwbgZVk5XMABOxFNKhCMNg6zjF0PYYeZi6KQJziMeRfgDl8RiWo1L0ipNXunSuj mX3g6bBv+e4vT5b39bbYoSwq1oGZLiHw6K3VSWZXVzUwpRLw+8taX4Ek+kHVTZmXeQxm ajBzdzOgZJkVKtQFZPlLlzg9M7Nnzcc76Vls21a88Q28x0bOOPWMTLJmg5emQHaE1g48 Qv/oRFdLpqYEwrwWG8HSK6zFN86OB1dbWWDGapzR76nwzKwRI+HtIl65xSpSFq7IASN3 AeoqiAdqJ5EI+DcqqBBgf3CTsF2EACNev3yjVpWVkoz3eK7r1q0LnT0wmcQOgbFjIP0X C+ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769774333; x=1770379133; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=HGMFI6tCot74p730gmYxB0ganfKY4B4oFGS/FHtw0j4=; b=fgPMiujQhDnK8vstv8wVQenvV/mA5ZF5tKMmumoip25xBCBjLqjlHyDpGx8CfrAxFV mPxnvO8B5ao61I4TEyaddahrhu768J+ADHapdLeALZr0xuFGOmSzbqPWze6pCWUrpwwb CjxRfrhKoOWaGaTosas9z6yJYldjjgUNd111rklfgD6QCmLVQNsddpcJcBCuWir+dNn9 Gk99/nbQbh8+QLVScDp7ajumiV5jtYrderm5CFJekR9DxEPCnzZhMln1bCZUCgdP2Vnh R6+IwaZZdMNZbjy6/vvKCs4+uHVP+TLV/ldQ6DKGEbDUuzr/RjaR18A0rRGShBURKzTc 7tlg== X-Forwarded-Encrypted: i=1; AJvYcCVTRnP8rX5cd1kYUQP/q3w8K4leo5cUY57FSRluy2rld9TNUP2dAZaSX5aXhpDYxIdP8fWy4YNe8OXqzbs=@vger.kernel.org X-Gm-Message-State: AOJu0Yz64cpwHby6e6YvVZ1nGOmrp4OKqmmVOi4q/YYTBFp5/hgZlvAl 2L64STpnAypOG3xdl0XJae7VV+rnDWmDIwtIbIXQW7wpCz+AWcSM0aRZ X-Gm-Gg: AZuq6aJutXWeRSybbK9aCInhsOwhKPkPncR3wzwiFKQRdEraLYkGZPSQjrJTSrIBAgy zzZeuItl/DuNNSeYohFUrHjF5R1hG7jdnlJyi0SunB8uJnITHQ7UhRXnbv45DWTMm5hhJJvWhFw bFIQwiBwoyCMVm3e9E5leYVXyWHgN2mdNDHLe1vjC/u93si0exkeBIUjHddES9UL/VhrzF7pkUV oOqLok5WsdkY5QevDYiqi8bJsI2xprUcMaCVihFEz3ibQ8A2DMJ2WPpV6AA248AJzmQ+9KJKIHZ rGn25f6xU8M86lnAvutOsj/Jleyi7CJoNyFw8LpO6ZSVb1qTnTh5rw9MJfJGvC7pqATZ8XlyVAx iXCkdPq7PDotEiWx9vdOOYw0idPhI1tRAjjSEXQKd49uEFNYxNWpzgFIKwEm97QFwNNNWpDp5iQ ne5exAi9ouwQP8r+desb/oiiVYu7WJW4bIc4kHrvMzPUFzag== X-Received: by 2002:a17:906:d554:b0:b88:5722:700 with SMTP id a640c23a62f3a-b8dff52ba80mr155016866b.5.1769774333210; Fri, 30 Jan 2026 03:58:53 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:bd64:2984:fe71:7633]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbeffed15sm404671566b.31.2026.01.30.03.58.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jan 2026 03:58:53 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 2/4] clk: renesas: rzg2l: Add support for enabling PLLs Date: Fri, 30 Jan 2026 11:58:43 +0000 Message-ID: <20260130115850.253555-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260130115850.253555-1-biju.das.jz@bp.renesas.com> References: <20260130115850.253555-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for enabling PLL clocks in the RZ/G3L CPG driver to turn off some PLLs, if they are not in use(eg: PLL6, PLL7) Introduce `is_enabled` and `enable` callbacks to handle PLL state transitions. With the `enable` callback, PLL will be turned ON only when the PLL consumer device is enabled; otherwise, it will remain off. Define new macros for PLL standby and monitor registers to facilitate this process. Signed-off-by: Biju Das --- v1->v2: * No change --- drivers/clk/renesas/rzg2l-cpg.c | 67 +++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 4 ++ 2 files changed, 71 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index ee92d07c6ff7..dfb36e6e6a7b 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -58,6 +58,13 @@ #define RZG3S_DIV_NF GENMASK(12, 1) #define RZG3S_SEL_PLL BIT(0) =20 +#define RZG3L_PLL_STBY_OFFSET(x) (GET_REG_SAMPLL_CLK1(x) - 0x4) +#define RZG3L_PLL_STBY_RESETB BIT(0) +#define RZG3L_PLL_STBY_RESETB_WEN BIT(16) +#define RZG3L_PLL_MON_OFFSET(x) (GET_REG_SAMPLL_CLK1(x) + 0x8) +#define RZG3L_PLL_MON_RESETB BIT(0) +#define RZG3L_PLL_MON_LOCK BIT(4) + #define CLK_ON_R(reg) (reg) #define CLK_MON_R(reg) (0x180 + (reg)) #define CLK_RST_R(reg) (reg) @@ -1181,6 +1188,63 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk= *core, return pll_clk->hw.clk; } =20 +static int rzg3l_cpg_pll_clk_is_enabled(struct clk_hw *hw) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + struct rzg2l_cpg_priv *priv =3D pll_clk->priv; + u32 val =3D readl(priv->base + RZG3L_PLL_MON_OFFSET(pll_clk->conf)); + u32 mon_val =3D RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK; + + /* Ensure both RESETB and LOCK bits are set */ + return (mon_val =3D=3D (val & mon_val)); +} + +static int rzg3l_cpg_pll_clk_endisable(struct clk_hw *hw, bool enable) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + struct rzg2l_cpg_priv *priv =3D pll_clk->priv; + u32 stby_offset, mon_offset; + u32 val, mon_val; + int ret; + + stby_offset =3D RZG3L_PLL_STBY_OFFSET(pll_clk->conf); + mon_offset =3D RZG3L_PLL_MON_OFFSET(pll_clk->conf); + + if (enable) { + val =3D RZG3L_PLL_STBY_RESETB_WEN | RZG3L_PLL_STBY_RESETB; + mon_val =3D RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK; + } else { + val =3D RZG3L_PLL_STBY_RESETB_WEN; + mon_val =3D 0; + } + + writel(val, priv->base + stby_offset); + + /* ensure PLL is in normal/stanby mode */ + ret =3D readl_poll_timeout_atomic(priv->base + mon_offset, val, mon_val = =3D=3D + (val & (RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK)), + 10, 100); + if (ret) + dev_err(priv->dev, "Failed to %s PLL 0x%x/%pC\n", enable ? + "enable" : "disable", stby_offset, hw->clk); + + return ret; +} + +static int rzg3l_cpg_pll_clk_enable(struct clk_hw *hw) +{ + if (rzg3l_cpg_pll_clk_is_enabled(hw)) + return 0; + + return rzg3l_cpg_pll_clk_endisable(hw, true); +} + +static const struct clk_ops rzg3l_cpg_pll_ops =3D { + .is_enabled =3D rzg3l_cpg_pll_clk_is_enabled, + .enable =3D rzg3l_cpg_pll_clk_enable, + .recalc_rate =3D rzg3s_cpg_pll_clk_recalc_rate, +}; + static struct clk *rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec, void *data) @@ -1264,6 +1328,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk= *core, case CLK_TYPE_SAM_PLL: clk =3D rzg2l_cpg_pll_clk_register(core, priv, &rzg2l_cpg_pll_ops); break; + case CLK_TYPE_G3L_PLL: + clk =3D rzg2l_cpg_pll_clk_register(core, priv, &rzg3l_cpg_pll_ops); + break; case CLK_TYPE_G3S_PLL: clk =3D rzg2l_cpg_pll_clk_register(core, priv, &rzg3s_cpg_pll_ops); break; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 1db413bb433d..7de4cb7af1cc 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -123,6 +123,7 @@ enum clk_types { CLK_TYPE_IN, /* External Clock Input */ CLK_TYPE_FF, /* Fixed Factor Clock */ CLK_TYPE_SAM_PLL, + CLK_TYPE_G3L_PLL, CLK_TYPE_G3S_PLL, =20 /* Clock with divider */ @@ -152,6 +153,9 @@ enum clk_types { DEF_TYPE(_name, _id, _type, .parent =3D _parent) #define DEF_SAMPLL(_name, _id, _parent, _conf) \ DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent =3D _parent, .conf =3D _co= nf) +#define DEF_G3L_PLL(_name, _id, _parent, _conf, _default_rate) \ + DEF_TYPE(_name, _id, CLK_TYPE_G3L_PLL, .parent =3D _parent, .conf =3D _co= nf, \ + .default_rate =3D _default_rate) #define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \ DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent =3D _parent, .conf =3D _co= nf, \ .default_rate =3D _default_rate) --=20 2.43.0 From nobody Mon Feb 9 14:00:26 2026 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA4D936EA9D for ; Fri, 30 Jan 2026 11:58:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769774337; cv=none; b=KWe0L0ZJ8EocKkBwNL4CwJx6KUJdAw0ZF3NnhgJYo6WPJ+PcEvp0NBaFvVj8lXP/uSei8s1nZZmYqxqPXslqYnMr00+fjJNV3pzV/UzucDhCtGt2xBv3/gbjv4q55qKxysQFAAmKiy+P4TA/ck5LKzhnCYS3q1CAvfTG0lioPpg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769774337; c=relaxed/simple; bh=KefAlO+NM/X4AH06AuNLpw4gAKi3rKcm5QO5l2tyg3M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QCPK/o1Cc6zN9LEMUC9ngSzLs7pH6aDlF5HCVrGW3IfX+dmlJB3vvX+1/3wDbjUQB6puz05+eYiGO4yb1L+/f4PKCx/jDHD/6u6fy6isKTtlNitGF26URvjFUeckqTUbHeV6vI0DIsTVAEoCU+W5J9+BQQhqcZXC4xAPxmEOpJQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=RqIRWMFY; arc=none smtp.client-ip=209.85.208.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RqIRWMFY" Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-658381b28e8so2857354a12.0 for ; Fri, 30 Jan 2026 03:58:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769774334; x=1770379134; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JyG64XmyWIdVs7sZ4Rn6fZ3iJE9VgCVPcmxB8ieVcgI=; b=RqIRWMFYY2mlK92hrDZ4SYRSNxv+liMz7/9I09nkgnzU8l+njgNgfomp0lmqXyqIf8 ww0se3gIvxAIltmwxCOjt4PjIhklMUyoWJFeQz1NLcmtVClXRxcysX80EyZ6qDdgiA5y lpWkLy7ngAlxvIiL2Gsq8VXdb79NCJQanDGDkSDkXVUVBDnQFdC+q7uBQRoCD65lMjU/ G8UClom5x1FQQrIOv+a72IDpylXLpvkmuG+q2Diw8ss7irm4yaxcvu6rXwb9lonBFAff i787+ZjANTGLXVnN9VzU37e7ub/gc6xEUV3J4U+Bg2AhbnbeBjKeNsmqINh6iSEJxTyL fyUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769774334; x=1770379134; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=JyG64XmyWIdVs7sZ4Rn6fZ3iJE9VgCVPcmxB8ieVcgI=; b=GhhN8ScHUSk+JznkRKVvrKXivo8DWEhTHvk7XPDEEhBmpnj/ufNlF3NASYIoDg1amx /gA8gL5QSDYllXJWI7JvGC3j/a6Xa3MAg7aUWjCsJvXnzrOZRZjylDVwy7TxW0nfxZNv hOl0FOYjBLixHLBDhDuotG6+Dll5sUNYYUgeGd9pIrSD/M1xpA98esFdQD6MzJQ26kiu OIic9NmF4rrkQGMHS0dVzkIHrPFYZUDr0HlUqIkJ1lrGowUsJTfZ3kz0sjVU0dsnptoS x70DtCcr48ttpfuJnxl23kE9BqMynEXn+Q4NOh3Az3ueO6ahlDahoAzhBz4iWXx+NK/J Nf+A== X-Forwarded-Encrypted: i=1; AJvYcCVjNeO4mocVwmQi2/x0ppcMnFjB23B3DvR1mQzyImFIC014ZHpKvejJFUyPRJH69lv8aLV3BM2Xv4ascVY=@vger.kernel.org X-Gm-Message-State: AOJu0YxMl1bSD1ZNEf8uRqssPhuGcddnoD5AbT0zitwoVT/p39+xYjT0 IwfAlxYUoqRa21utknL6dNQ7gAmaD5hmfIxSOOsDOZ1G++uyKXfHGOO1 X-Gm-Gg: AZuq6aKZyZE2ux/aHi53j5Mradqbs1ick4gbQCjqxRww9KlolQqVdC/LMCLDqG7vyb+ ILfHko2PkrycmBJww/ZQwWdmKihRfUEFt0tn6xEhrSBWsy4s01yjtpBC/ErG4MsmZZbpsIS39ro px74qZ392B4gPwb+4MFT+bUnPJqMcPnpl8OWlUSCdCVa97V53sw44Dp5EWMFCuhGQFQNAY3ChIW ewddmn3luOSP945Tc4/WUA+dJyIdbrwb+XjN/YAIFflDT+QcXv3bBl8odmnQ6NLI/UsSBmk5D1h Hs5XviN74agUmMmU4y10Dw9Gekx77RyE36v7Ix0a7B6v5bOsOBKSL84z7yr2jhjG0RxaUH8gA91 pnp3o5B2eCvnj1XkeUOMgx34cPN1nV9qZ4MKf4FsRVNinqfnqUIQvYZyYPng21zjezOasL3c1N9 esJBcnEgXMqJ5WVUyrowHYF6dYfws211yqkOI= X-Received: by 2002:a17:906:fd89:b0:b87:711f:97a3 with SMTP id a640c23a62f3a-b8dff73a356mr143900366b.35.1769774333695; Fri, 30 Jan 2026 03:58:53 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:bd64:2984:fe71:7633]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbeffed15sm404671566b.31.2026.01.30.03.58.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jan 2026 03:58:53 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 3/4] clk: renesas: r8a08g046: Add support for PLL6 clk Date: Fri, 30 Jan 2026 11:58:44 +0000 Message-ID: <20260130115850.253555-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260130115850.253555-1-biju.das.jz@bp.renesas.com> References: <20260130115850.253555-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for PLL6 clk by registering with rzg2l-cpg driver. Signed-off-by: Biju Das --- v1->v2: * No change --- drivers/clk/renesas/r9a08g046-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index d77934872cf4..cc7d3872e9e4 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -29,6 +29,9 @@ #define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1) #define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1) =20 +/* PLL 1/4/6/7 configuration registers macro. */ +#define G3L_PLL1467_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12= | (setting)) + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK =3D R9A08G046_CLK_P4_DIV2, @@ -45,6 +48,7 @@ enum clk_ids { CLK_PLL2_DIV2, CLK_PLL3, CLK_PLL3_DIV2, + CLK_PLL6, =20 /* Module Clocks */ MOD_CLK_BASE, @@ -78,6 +82,8 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __= initconst =3D { /* Internal Core Clocks */ DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), + DEF_G3L_PLL(".pll6", CLK_PLL6, CLK_EXTAL, G3L_PLL1467_CONF(0x54, 0x58, 0), + 500000000UL), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), =20 --=20 2.43.0 From nobody Mon Feb 9 14:00:26 2026 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08C26371057 for ; Fri, 30 Jan 2026 11:58:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769774338; cv=none; b=mLxKtu85MwlOIB3rmSRtpMCLE8CBko8VAgaJXnAoiXxWPbQVS5Qaepvvz8C1l/OQeiRQ2p3hFyaU0RBnhe2B9dzB2ZjifN71DUsj+6IIUC111Xvs3CEbwCbgtXsUH9VZXMZpM492rkfb1l7ZoCoR/1nH3x0479Akcr7U5SPmB5k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769774338; c=relaxed/simple; bh=Wt36PN5bHjGIsRQN727yxFJttOtyQJFgvRYzNsGZ+a8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SpL8dP11u4PvReZ1N0HH/7C/pCgF01t9k/wWuhpV9OO9vuuUTNLN6DGUggT6tkm9fsvIIMx1aYjfxQfAPqfrz7H7nht0kSVjqKFhc8mVsb8s1+tWjILmYGiJs/YfpmgwOkDgfQ3qzQzPDNzC10lzM8cu3FGUkUJv9RHuae2r9wk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=bo6JAlP/; arc=none smtp.client-ip=209.85.208.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bo6JAlP/" Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-65812261842so4675398a12.1 for ; Fri, 30 Jan 2026 03:58:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769774334; x=1770379134; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=na+ZDw0eAD/iSJmU7KFtSfYJdxr1nTFE8Fh4OeAd1ss=; b=bo6JAlP/ry7dpAEeJEZAviKVOtOi8llSR60XOIIJ0EGyrnWcJo4joG6BL+BAGdIqW/ a60Ps/K1HtXREqjiJO7eNopTOpAOkhj/CBS7mNx7fr9ad+OjHKKu3cOG7511uJDaiNIl UtWsyiDMGKryyB5X+BBbXSBF+aKJ8du1oikSmnUxPVFLPjigwHhBhSVAhdfjFYaH+WZu 5hy+wCGpVf6swijZ3OMqJXfc7Awd/ou/eF/6mleMHzg7Lo3sjuytHHgBNizQ1AMiS45A /W0jkmHoafvjxQAV2YsoxcyN/m2OMTrSEirmYIu276v5S+EREn6riW7ZTLGoGpH9G1nb 7h+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769774334; x=1770379134; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=na+ZDw0eAD/iSJmU7KFtSfYJdxr1nTFE8Fh4OeAd1ss=; b=SEbJzelhqbo/jQpaY3Hy5CIehMuavzJAwSPTstMe8kBEbPj43z7tztwFZnikbAClt6 NfAJ0zHSaapJ8MMj7GEhIZ7JSXr8RZs362fprP4fZ1hlftLCXvgZCdG3UASWXPVlJuTK QyOakb/dJaw53tJO754tTh0X1Mk5an6CkOJJXx7cz1k0uUaij4rSSTMA04Mh/+7GKtRR zH4O2+7FNaEOhQyVanBq87LYeEIRxUUSgRUIKF/d4Ew10XeduJhRQeCGE07vLORwuorI 4rCinAAVO6ysBS2DwTciYNPO5Bip4SN1DJrshuUdgJOVxepOiBHTqHSQAykSPGfXpHB6 1x9Q== X-Forwarded-Encrypted: i=1; AJvYcCXI1A8MQYAi34BdN7eVBzJtWORM4ngBd6TD5sGdTnQwnkX1gT3FL+QHDfkd7IZhomZcVhIycSS9J4av8Pk=@vger.kernel.org X-Gm-Message-State: AOJu0Yxvpq7dUxnzJKwcV9kEbLUAbmvaJCKfk7DPNhE5b8SZH5mpr764 QYOpPgmCVGqbc5PcUcioqQn9jKMsSppZ8dt/3oGz6OQqmWWF7FEe2gAL X-Gm-Gg: AZuq6aLcynurblS+ZJDMTQZ9MFpwR+g31pFKvtoQ23V6O0KTVcj8hmU7i52NMzK1z4r UfPlrMgqabR1A8vBJRhew+shYyF0olpQhO5bzoMeb7OrUOIZCMnnccivvITFwVwcNS5Xe6IN+Kw Xc5AYi763HwHwyfrl56U53i4eyuR5x43lm0M/Kw4eZsjJ31vgcuGJ3ThMNk23YXgqWtPlqeOswT 0Yx94HFgsnX09uIpFRQgx1gLzRBr+ycNPJEIm/T3n8baR1f94aW6nR5acB3dfZM/5grNrWekSkX p2DvYU9D063q6PmX+Ji8MgyV+BIhM7YTVrU8ySjkss7PUDpId8PaWiEKMqK1FPTNBG9Jnx1DQIZ fnwdqQ8DGR8y3O91TIbY2fVsZumQTQaJml3XOFbunqmJSSJmA/oZWMUNHXgzF2dsAAkkdsb9A/O M64CjAr5spGJDGi58KIKCqH2gTAAcwiIpC7uE= X-Received: by 2002:a17:907:2d0e:b0:b88:1e2:ed49 with SMTP id a640c23a62f3a-b8dff22f549mr177830866b.8.1769774334208; Fri, 30 Jan 2026 03:58:54 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:bd64:2984:fe71:7633]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbeffed15sm404671566b.31.2026.01.30.03.58.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jan 2026 03:58:53 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 4/4] clk: renesas: r9a08g046: Add clock and reset signals for the GBETH IPs Date: Fri, 30 Jan 2026 11:58:45 +0000 Message-ID: <20260130115850.253555-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260130115850.253555-1-biju.das.jz@bp.renesas.com> References: <20260130115850.253555-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1) IPs found on the RZ/G3L SoC. This includes various dividers and mux clocks needed by these two GBETH IPs. Signed-off-by: Biju Das --- v1->v2: * No change --- drivers/clk/renesas/r9a08g046-cpg.c | 114 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 6 ++ 2 files changed, 120 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index cc7d3872e9e4..e74bab2df29a 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -18,17 +18,35 @@ #define G3L_CPG_PL2_DDIV (0x204) #define G3L_CPG_PL3_DDIV (0x208) #define G3L_CLKDIVSTATUS (0x280) +#define G3L_CPG_ETH_SSEL (0x410) +#define G3L_CPG_ETH_SDIV (0x434) =20 /* RZ/G3L Specific division configuration. */ #define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2) #define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2) #define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2) +#define G3L_SDIV_ETH_A DDIV_PACK(G3L_CPG_ETH_SDIV, 0, 2) +#define G3L_SDIV_ETH_B DDIV_PACK(G3L_CPG_ETH_SDIV, 4, 1) +#define G3L_SDIV_ETH_C DDIV_PACK(G3L_CPG_ETH_SDIV, 8, 2) +#define G3L_SDIV_ETH_D DDIV_PACK(G3L_CPG_ETH_SDIV, 12, 1) =20 /* RZ/G3L Clock status configuration. */ #define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1) #define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1) #define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1) =20 +/* RZ/G3L Specific clocks select. */ +#define G3L_SEL_ETH0_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 0, 1) +#define G3L_SEL_ETH0_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 1, 1) +#define G3L_SEL_ETH0_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 2, 1) +#define G3L_SEL_ETH0_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 3, 1) +#define G3L_SEL_ETH0_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 4, 1) +#define G3L_SEL_ETH1_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 8, 1) +#define G3L_SEL_ETH1_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 9, 1) +#define G3L_SEL_ETH1_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 10, 1) +#define G3L_SEL_ETH1_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 11, 1) +#define G3L_SEL_ETH1_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 12, 1) + /* PLL 1/4/6/7 configuration registers macro. */ #define G3L_PLL1467_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12= | (setting)) =20 @@ -49,12 +67,29 @@ enum clk_ids { CLK_PLL3, CLK_PLL3_DIV2, CLK_PLL6, + CLK_PLL6_DIV10, + CLK_SEL_ETH0_TX, + CLK_SEL_ETH0_RX, + CLK_SEL_ETH0_RM, + CLK_SEL_ETH1_TX, + CLK_SEL_ETH1_RX, + CLK_SEL_ETH1_RM, + CLK_ETH0_TR, + CLK_ETH0_RM, + CLK_ETH1_TR, + CLK_ETH1_RM, =20 /* Module Clocks */ MOD_CLK_BASE, }; =20 /* Divider tables */ +static const struct clk_div_table dtable_2_20[] =3D { + { 0, 2 }, + { 1, 20 }, + { 0, 0 }, +}; + static const struct clk_div_table dtable_4_128[] =3D { { 0, 4 }, { 1, 2 }, @@ -63,6 +98,13 @@ static const struct clk_div_table dtable_4_128[] =3D { { 0, 0 }, }; =20 +static const struct clk_div_table dtable_4_200[] =3D { + { 0, 4 }, + { 1, 20 }, + { 2, 200 }, + { 0, 0 }, +}; + static const struct clk_div_table dtable_8_256[] =3D { { 0, 8 }, { 1, 16 }, @@ -71,6 +113,18 @@ static const struct clk_div_table dtable_8_256[] =3D { { 0, 0 }, }; =20 +/* Mux clock names tables. */ +static const char * const sel_eth0_tx[] =3D { ".div_eth0_tr", "eth0_txc_tx= _clk" }; +static const char * const sel_eth0_rx[] =3D { ".div_eth0_tr", "eth0_rxc_rx= _clk" }; +static const char * const sel_eth0_rm[] =3D { ".pll6_div10", "eth0_rxc_rx_= clk" }; +static const char * const sel_eth1_tx[] =3D { ".div_eth1_tr", "eth1_txc_tx= _clk" }; +static const char * const sel_eth1_rx[] =3D { ".div_eth1_tr", "eth1_rxc_rx= _clk" }; +static const char * const sel_eth1_rm[] =3D { ".pll6_div10", "eth1_rxc_rx_= clk" }; +static const char * const sel_eth0_clk_tx_i[] =3D { ".sel_eth0_tx", ".div_= eth0_rm" }; +static const char * const sel_eth0_clk_rx_i[] =3D { ".sel_eth0_rx", ".div_= eth0_rm" }; +static const char * const sel_eth1_clk_tx_i[] =3D { ".sel_eth1_tx", ".div_= eth1_rm" }; +static const char * const sel_eth1_clk_rx_i[] =3D { ".sel_eth1_rx", ".div_= eth1_rm" }; + static const struct cpg_core_clk r9a08g046_core_clks[] __initconst =3D { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -86,6 +140,17 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { 500000000UL), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll6_div10", CLK_PLL6_DIV10, CLK_PLL6, 1, 10), + DEF_MUX(".sel_eth0_tx", CLK_SEL_ETH0_TX, G3L_SEL_ETH0_TX, sel_eth0_tx), + DEF_MUX(".sel_eth0_rx", CLK_SEL_ETH0_RX, G3L_SEL_ETH0_RX, sel_eth0_rx), + DEF_MUX(".sel_eth0_rm", CLK_SEL_ETH0_RM, G3L_SEL_ETH0_RM, sel_eth0_rm), + DEF_MUX(".sel_eth1_tx", CLK_SEL_ETH1_TX, G3L_SEL_ETH1_TX, sel_eth1_tx), + DEF_MUX(".sel_eth1_rx", CLK_SEL_ETH1_RX, G3L_SEL_ETH1_RX, sel_eth1_rx), + DEF_MUX(".sel_eth1_rm", CLK_SEL_ETH1_RM, G3L_SEL_ETH1_RM, sel_eth1_rm), + DEF_DIV(".div_eth0_tr", CLK_ETH0_TR, CLK_PLL6, G3L_SDIV_ETH_A, dtable_4_2= 00), + DEF_DIV(".div_eth1_tr", CLK_ETH1_TR, CLK_PLL6, G3L_SDIV_ETH_C, dtable_4_2= 00), + DEF_DIV(".div_eth0_rm", CLK_ETH0_RM, CLK_SEL_ETH0_RM, G3L_SDIV_ETH_B, dta= ble_2_20), + DEF_DIV(".div_eth1_rm", CLK_ETH1_RM, CLK_SEL_ETH1_RM, G3L_SDIV_ETH_D, dta= ble_2_20), =20 /* Core output clk */ DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL= 2B_STS, @@ -94,6 +159,21 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { dtable_4_128, 0, 0, 0, NULL), DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL= 2A_STS, dtable_4_128, 0, 0, 0, NULL), + DEF_FIXED("HP", R9A08G046_CLK_HP, CLK_PLL6_DIV10, 1, 1), + DEF_MUX_FLAGS("ETHTX01", R9A08G046_CLK_ETHTX01, G3L_SEL_ETH0_CLK_TX_I, se= l_eth0_clk_tx_i, + CLK_SET_RATE_PARENT), + DEF_MUX_FLAGS("ETHRX01", R9A08G046_CLK_ETHRX01, G3L_SEL_ETH0_CLK_RX_I, se= l_eth0_clk_rx_i, + CLK_SET_RATE_PARENT), + DEF_MUX_FLAGS("ETHTX11", R9A08G046_CLK_ETHTX11, G3L_SEL_ETH1_CLK_TX_I, se= l_eth1_clk_tx_i, + CLK_SET_RATE_PARENT), + DEF_MUX_FLAGS("ETHRX11", R9A08G046_CLK_ETHRX11, G3L_SEL_ETH1_CLK_RX_I, se= l_eth1_clk_rx_i, + CLK_SET_RATE_PARENT), + DEF_FIXED("ETHRM0", R9A08G046_CLK_ETHRM0, CLK_ETH0_RM, 1, 1), + DEF_FIXED("ETHTX02", R9A08G046_CLK_ETHTX02, CLK_SEL_ETH0_TX, 1, 1), + DEF_FIXED("ETHRX02", R9A08G046_CLK_ETHRX02, CLK_SEL_ETH0_RX, 1, 1), + DEF_FIXED("ETHRM1", R9A08G046_CLK_ETHRM1, CLK_ETH1_RM, 1, 1), + DEF_FIXED("ETHTX12", R9A08G046_CLK_ETHTX12, CLK_SEL_ETH1_TX, 1, 1), + DEF_FIXED("ETHRX12", R9A08G046_CLK_ETHRX12, CLK_SEL_ETH1_RX, 1, 1), }; =20 static const struct rzg2l_mod_clk r9a08g046_mod_clks[] =3D { @@ -107,6 +187,38 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[]= =3D { MSTOP(BUS_REG1, BIT(2))), DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1, MSTOP(BUS_REG1, BIT(3))), + DEF_MOD("eth0_clk_axi", R9A08G046_ETH0_CLK_AXI, R9A08G046_CLK_P1, 0x57c,= 0, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_MOD("eth1_clk_axi", R9A08G046_ETH1_CLK_AXI, R9A08G046_CLK_P1, 0x57c,= 1, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_MOD("eth0_clk_chi", R9A08G046_ETH0_CLK_CHI, R9A08G046_CLK_P1, 0x57c,= 2, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_MOD("eth1_clk_chi", R9A08G046_ETH1_CLK_CHI, R9A08G046_CLK_P1, 0x57c,= 3, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth0_tx_i", R9A08G046_ETH0_CLK_TX_I, R9A08G046_CLK_ETHTX01, = 0x57c, 4, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth0_tx_180_i", R9A08G046_ETH0_CLK_TX_180_I, R9A08G046_CLK_E= THTX02, 0x57c, 4, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth1_tx_i", R9A08G046_ETH1_CLK_TX_I, R9A08G046_CLK_ETHTX11, = 0x57c, 5, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_COUPLED("eth1_tx_180_i", R9A08G046_ETH1_CLK_TX_180_I, R9A08G046_CLK_E= THTX12, 0x57c, 5, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_COUPLED("eth0_rx_i", R9A08G046_ETH0_CLK_RX_I, R9A08G046_CLK_ETHRX01, = 0x57c, 6, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth0_rx_180_i", R9A08G046_ETH0_CLK_RX_180_I, R9A08G046_CLK_E= THRX02, 0x57c, 6, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth1_rx_i", R9A08G046_ETH1_CLK_RX_I, R9A08G046_CLK_ETHRX11, = 0x57c, 7, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_COUPLED("eth1_rx_180_i", R9A08G046_ETH1_CLK_RX_180_I, R9A08G046_CLK_E= THRX12, 0x57c, 7, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_MOD("eth0_ptp_ref_i", R9A08G046_ETH0_CLK_PTP_REF_I, R9A08G046_CLK_HP,= 0x57c, 8, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_MOD("eth1_ptp_ref_i", R9A08G046_ETH1_CLK_PTP_REF_I, R9A08G046_CLK_HP,= 0x57c, 9, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_MOD("eth0_rmii_i", R9A08G046_ETH0_CLK_RMII_I, R9A08G046_CLK_ETHRM0, = 0x57c, 10, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_MOD("eth1_rmii_i", R9A08G046_ETH1_CLK_RMII_I, R9A08G046_CLK_ETHRM1, = 0x57c, 11, + MSTOP(BUS_PERI_COM, BIT(3))), DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584= , 0, MSTOP(BUS_MCPU2, BIT(1))), }; @@ -117,6 +229,8 @@ static const struct rzg2l_reset r9a08g046_resets[] =3D { DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0), DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0), + DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1), DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0), }; =20 diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 7de4cb7af1cc..9abb53483759 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -188,6 +188,12 @@ enum clk_types { .parent_names =3D _parent_names, \ .num_parents =3D ARRAY_SIZE(_parent_names), \ .mux_flags =3D CLK_MUX_READ_ONLY) +#define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flag) \ + DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf =3D _conf, \ + .parent_names =3D _parent_names, \ + .num_parents =3D ARRAY_SIZE(_parent_names), \ + .mux_flags =3D CLK_MUX_HIWORD_MASK, \ + .flag =3D _flag) #define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk= _flags, _notifier) \ DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf =3D _conf, .sconf =3D _sconf,= \ .parent_names =3D _parent_names, \ --=20 2.43.0