From nobody Sun Feb 8 16:34:10 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CD6A37105B for ; Fri, 30 Jan 2026 11:54:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769774100; cv=none; b=lVyJ+koXuiNTPm655D3X8bYW2dm3I8udwaHZeJpn6XNtwb7UMqpqALuSL2/nBfEQIMIQ+/t07fKDVA6ZMj1+YX5XIYj7Rzz6rAjOZtktPD1n/9Ooc2JaBRKkb192lnF0IjNEums/0/IMR3iWR89vPpINdf8Vglv5gPklvy1M+D8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769774100; c=relaxed/simple; bh=CbgzOaYDkc3bXhiSUZkzlP8DjhXVBP0eRFGEsmWlQbQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hUbXHI15wns28da55Wyf7BDp7F3TMD23z2emTaN7Lzjq/5Z2umx3iUH6oXOx17B5FdgKT4OEXHhxuj+g8Hr9+XLIUXXaAJOwkh3qFz36lKRSKIZ0wVHpjY+NpkkRyLm+kh4MTUQSZIMiQsPVLCdvE5LDgqgntNEm2NpK7IJFPVU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=nkdPfs8d; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Z81s+T9o; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="nkdPfs8d"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Z81s+T9o" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60UB5WHN890991 for ; Fri, 30 Jan 2026 11:54:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=yRCNcS5A6Eu GBIPJ6FqXwxvOo4jjK2JrobpZz5iBr1c=; b=nkdPfs8dgdIKJth9mytG0eIkkSk FcgGiTyfFD40VDfFsZhxfH6iwVUhX1UGP0XQ8Ga202JncUwrIn80TYBMQitfIn/m J1W9nQ7ELfBBHk+y1k9DvyT6qGG1deJtd1OdcroHMqeci2DTatuokoDdOWgtZzN4 FboeIxPKpKQdbicNm1IyZLHnG9CZAanBju1KTZQSiSZQhJLQDHcvotFszQKF8OVs 0r+zMRh78R8pr4/5RZfy7D34P8nGisU2gRKs3fmmgXgUOgbHGNCSJp6pfgUfPAIE L2BUJDgKmwjVeGNwOG2gOuVnXncKQOc5W8q7BJ4lTsJQzxMHtZHm/g0GhoA== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4c0gs7t1dh-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 30 Jan 2026 11:54:54 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-34c704d5d15so3932772a91.1 for ; Fri, 30 Jan 2026 03:54:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1769774094; x=1770378894; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yRCNcS5A6EuGBIPJ6FqXwxvOo4jjK2JrobpZz5iBr1c=; b=Z81s+T9omi3gs2rt/0vDiz6ibL07FzpavokSqc/DNJ74CcpIw6uUQPs+AmsNQ5GPAM YelSUeavgQjb2dmOTPW8uwd5JefeHHv4BYJ6IOht2I65EoCjqwXr5KquwaWm4zpgvuIw /sHZX5hPMDolETLLAEt4r48Fi4Ygq1AKdwVFEZOEi9M1tA/MmBBQyNYYUGP4d0DZjCvG 6B/0rGE2x5qzAdFOHVAqwQ/Jz+offn/VEnA5Jr33SbyLxHuZWPp4T9RANjWYsRKoaakg PX4no7IDETYs6c3lz9TWymgZtQdqk+JWSFpD+Otb+KcR7LGGH39skOm/zA6hZ922FI5a CLxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769774094; x=1770378894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=yRCNcS5A6EuGBIPJ6FqXwxvOo4jjK2JrobpZz5iBr1c=; b=M/kHsKx3Z1rWWdnvSioUefwv09xFsrMffnv23CaH6tMZVEI9jvfjJUcD1hW2DrnJVB 8VlVBnHsyXj3T2Iq4IjGhIu+q2djPgwsuW0CSniavFxon6go/yqgiayNUwxr0ZS6N7nM fnnBmj/Ys8t78StQfhFjtQHZwXmWYjyBBLp8s4uQs82p9eCGMgFNeTFlk/jsGn6t6E+C siqYje4z4oXkG+TpV5XYEUvXMEFql0socU1gInXFXcMMOvCL7QgtESTlsFS3AHA/zqNB gUR802zFbmQKn91iXMR7pAsgX99GilqsRTmBbnRJPR31NN+rYIpu0daYHQGITm0gW+aG 3Vdg== X-Forwarded-Encrypted: i=1; AJvYcCV591RvHKoiI4YsUhWzZ4HgciG78FNsKQNpUNefGsj5I5WwH0shuFQZHZmkI8+yrPxEpsfoAbyvs3uXHUU=@vger.kernel.org X-Gm-Message-State: AOJu0YzuYAQOKCatW7d3ueOKQrbPHstHz8V+GC/Jszvb1LSFYwoAbEB6 3WofIzp77C9ImeOeHj3JKc3OB6kKvtUQfdnCNpdoV+62FQTIzgNkIH3a5JeuS/70OOIvLyzpeoK MfceLhE7bubAWs9bymALEes/+1e12mxALzGSxOShLo7q2raJtIKasOLmpacmCwfVCgdI= X-Gm-Gg: AZuq6aKvXZr2cH2Ct76l9FS+Ks6mnG0P4EP/y1eeU7d3q63AUYXdQ9hfO85NxKquw17 IPV+oxSTbfcjvfcREbxMJQRWiEN/M1lv+fX/0cBjseB4WeEI6P/C2pSLyiTkltqlR09tLvUI2kS eDs554CSYGFFhUcuvAfjR3XI2tQGtxr47wdQpXEFbEJ1fRSzYr0jcRsVUzDk3/eg2gqokFESax9 hij6QTDj/DPT2QyZV2wRn8w6d9Jck2i/IES0QxqyAqEXIiKu4Q6j7rJ79YCMqfcibDNlywzIc8n IXbaapUslpG72M/JDFkr1LS+fLeDGFa7frr+dvZ7OA1WmYgxh0wjqlIJXdHkAYK+5/Itn8XC9WV e2nHMLUzDJIu5x4OizelcZeF1KuLz6W/oOmbOTnINheg5 X-Received: by 2002:a17:90b:2fc5:b0:33b:b020:597a with SMTP id 98e67ed59e1d1-3543b185498mr2599986a91.0.1769774094071; Fri, 30 Jan 2026 03:54:54 -0800 (PST) X-Received: by 2002:a17:90b:2fc5:b0:33b:b020:597a with SMTP id 98e67ed59e1d1-3543b185498mr2599969a91.0.1769774093547; Fri, 30 Jan 2026 03:54:53 -0800 (PST) Received: from hu-jprakash-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3540f2f24ccsm10431278a91.8.2026.01.30.03.54.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jan 2026 03:54:53 -0800 (PST) From: Jishnu Prakash To: jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org, daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org, subbaraman.narayanamurthy@oss.qualcomm.com, david.collins@oss.qualcomm.com, anjelique.melendez@oss.qualcomm.com, kamal.wadhwa@oss.qualcomm.com Cc: rui.zhang@intel.com, lukasz.luba@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, jishnu.prakash@oss.qualcomm.com, quic_kotarake@quicinc.com, neil.armstrong@linaro.org, stephan.gerhold@linaro.org, Jonathan Cameron , Krzysztof Kozlowski Subject: [PATCH V10 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC Date: Fri, 30 Jan 2026 17:24:19 +0530 Message-Id: <20260130115421.2197892-3-jishnu.prakash@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260130115421.2197892-1-jishnu.prakash@oss.qualcomm.com> References: <20260130115421.2197892-1-jishnu.prakash@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTMwMDA5NyBTYWx0ZWRfXwLPmbsQW9Nju 7Fik2AITmegMKj3RVK57WGMtH490v3Dx7R54NHhOcPQPnTGVm4Y08oedkfnrs/6AJKgZnC5LMx2 5C1aR+MHYs9t/Y+uA3HFDE7N9OK+ZZCRhBatsZuimPjRIrWg8egOeqxiMqUbJWb4iTjDFlX5RRh MqQDV+MCzldP0t3ziE1+tUD4uJmmggErpB1VpIyfTUkvCuDv3/22Xp7XSrj4kEmbTdHMeNGgJSi lOIDTGMPvDI1eszU451aD0Y/ieBoLkiOByVr7F5bwRZnNH07dZjHLZP1JDqNUIQvzUomHEnkVKc YgpEeB6iyce2CGZ5mx5k3vrRjbgaWm9ndiWlRJXX38tO0xfQ1sdOPDm865B7gpD8anP2aDsCM9n AJIwGrY+IMaIValYpu+GL1N27t1VjtZ/Q5Uw6BLKQ3os62YOcKpxh6rELmGDFK5u+mvSDfe3W9S VzaXZFhMS6SXZN9tFeg== X-Proofpoint-ORIG-GUID: VViURIrE3AU1Kqnl9O8D0b648aLyZVa5 X-Proofpoint-GUID: VViURIrE3AU1Kqnl9O8D0b648aLyZVa5 X-Authority-Analysis: v=2.4 cv=UPLQ3Sfy c=1 sm=1 tr=0 ts=697c9c0e cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=gEfo2CItAAAA:8 a=i0EeH86SAAAA:8 a=YrMGt2jeDSw4g2R_97MA:9 a=uKXjsCUrEbL0IQVhDsJ9:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-30_01,2026-01-29_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 adultscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 spamscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601300097 Content-Type: text/plain; charset="utf-8" For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs going through PBS(Programmable Boot Sequence) firmware through a single register interface. This interface is implemented on SDAM (Shared Direct Access Memory) peripherals on the master PMIC PMK8550 rather than a dedicated ADC peripheral. Add documentation for PMIC5 Gen3 ADC and update SPMI PMIC bindings to allow ADC5 Gen3 as adc@ subnode. Acked-by: Jonathan Cameron Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jishnu Prakash --- Changes since v7: - Dropped ADC5 GEN3 channel macro definitions from bindings, based on discussion with Krzysztof concluded here:=20 https://lore.kernel.org/all/d10e2eea-4b86-4e1a-b7a0-54c55907a605@oss.qual= comm.com/, to be added separately in other patches. - Fixed quotes to use only double quotes for "#address-cells", "#size-cells" and "#io-channel-cells" properties, to address Krzysztof's comment. - Removed inclusion of ADC channel macro header files from ADC5 Gen3 example and replaced the macros used in the "reg" properties in channel nodes with the actual hex values. - Removed update made under `reg` property in Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc-common.yaml which referenced ADC macro binding files, to align with change made in patch 1 of this series. Changes since v6: - Updated SPMI PMIC bindings to allow ADC5 Gen3 as adc@ subnode, to address Neil's comment. - Replaced 2025 copyright in newly added files with yearless copyright, following new internal guidelines. - Collected Acked-by tag from Jonathan. Changes since v5: - Addressed following comments from Krzysztof: - Increased line wrap length for top-level device description. - Added more details in binding description explaining how number of SDAM peripherals used for ADC is allocated per SoC. - Dropped "interrupt-names" property. - Moved `required` block to after the list of all properties. - Dropped | from patternProperties description. - Renamed per-PMIC binding files listing ADC channel macro names. - Addressed following comments from Jonathan: - Moved ref before description, under patternProperties. - Arranged enum under qcom,hw-settle-time as groups of 8. Changes since v4: - Added ADC5 Gen3 documentation in a separate new file to avoid complicating existing VADC documentation file further to accomodate this device, as suggested by reviewers. Changes since v3: - Added ADC5 Gen3 documentation changes in existing qcom,spmi-vadc.yaml file instead of adding separate file and updated top-level constraints in docu= mentation file based on discussion with reviewers. - Dropped default SID definitions. - Addressed other reviewer comments. Changes since v2: - Moved ADC5 Gen3 documentation into a separate new file. Changes since v1: - Updated properties separately for all compatibles to clarify usage of new properties and updates in usage of old properties for ADC5 Gen3. - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment mentioning this convention. - Used predefined channel IDs in individual PMIC channel definitions instead of numeric IDs. - Addressed other comments from reviewers. .../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml | 151 ++++++++++++++++++ .../bindings/iio/adc/qcom,spmi-vadc.yaml | 2 + .../bindings/mfd/qcom,spmi-pmic.yaml | 1 + 3 files changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc= 5-gen3.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.= yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml new file mode 100644 index 000000000000..149f4af8f4b8 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC ADC5 Gen3 + +maintainers: + - Jishnu Prakash + +description: | + SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to clients to read + voltage. It is a 16-bit sigma-delta ADC. It also performs the same therm= al + monitoring function as the existing ADC_TM devices. + + The interface is implemented on SDAM (Shared Direct Access Memory) perip= herals + on the master PMIC rather than a dedicated ADC peripheral. The number of= PMIC + SDAM peripherals allocated for ADC is not correlated with the PMIC used,= it is + programmed in FW (PBS) and is fixed per SOC, based on the SOC requiremen= ts. + All boards using a particular (SOC + master PMIC) combination will have = the + same number of ADC SDAMs supported on that PMIC. + +properties: + compatible: + const: qcom,spmi-adc5-gen3 + + reg: + items: + - description: SDAM0 base address in the SPMI PMIC register map + - description: SDAM1 base address + minItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#io-channel-cells": + const: 1 + + "#thermal-sensor-cells": + const: 1 + + interrupts: + items: + - description: SDAM0 end of conversion (EOC) interrupt + - description: SDAM1 EOC interrupt + minItems: 1 + +patternProperties: + "^channel@[0-9a-f]+$": + type: object + unevaluatedProperties: false + $ref: /schemas/iio/adc/qcom,spmi-vadc-common.yaml + description: + Represents the external channels which are connected to the ADC. + + properties: + qcom,decimation: + enum: [ 85, 340, 1360 ] + default: 1360 + + qcom,hw-settle-time: + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, + 1000, 2000, 4000, 8000, 16000, 32000, 64000, 128000 ] + default: 15 + + qcom,avg-samples: + enum: [ 1, 2, 4, 8, 16 ] + default: 1 + + qcom,adc-tm: + description: + ADC_TM is a threshold monitoring feature in HW which can be enab= led + on any ADC channel, to trigger an IRQ for threshold violation. In + earlier ADC generations, it was implemented in a separate device + (documented in Documentation/devicetree/bindings/thermal/qcom-sp= mi-adc-tm5.yaml.) + In Gen3, this feature can be enabled in the same ADC device for = any + channel and threshold monitoring and IRQ triggering are handled = in FW + (PBS) instead of another dedicated HW block. + This property indicates ADC_TM monitoring is done on this channe= l. + type: boolean + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - "#io-channel-cells" + - interrupts + +additionalProperties: false + +examples: + - | + #include + + pmic { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@9000 { + compatible =3D "qcom,spmi-adc5-gen3"; + reg =3D <0x9000>, <0x9100>; + interrupts =3D <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + #thermal-sensor-cells =3D <1>; + + /* PMK8550 Channel nodes */ + channel@3 { + reg =3D <0x3>; + label =3D "pmk8550_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@44 { + reg =3D <0x44>; + label =3D "pmk8550_xo_therm"; + qcom,pre-scaling =3D <1 1>; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + /* PM8550 Channel nodes */ + channel@103 { + reg =3D <0x103>; + label =3D "pm8550_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@78f { + reg =3D <0x78f>; + label =3D "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling =3D <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg =3D <0x203>; + label =3D "pm8550vs_c_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml = b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml index 16c80709a3ee..72188041e8b5 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -15,6 +15,8 @@ description: | voltage. The VADC is a 15-bit sigma-delta ADC. SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read voltage. The VADC is a 16-bit sigma-delta ADC. + Note that PMIC7 ADC is the generation between PMIC5 and PMIC5 Gen3 ADC, + it can be considered like PMIC5 Gen2. =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Do= cumentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index 65c80e3b4500..cc5de26bbf57 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -129,6 +129,7 @@ patternProperties: "^adc@[0-9a-f]+$": type: object oneOf: + - $ref: /schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# - $ref: /schemas/iio/adc/qcom,spmi-iadc.yaml# - $ref: /schemas/iio/adc/qcom,spmi-rradc.yaml# - $ref: /schemas/iio/adc/qcom,spmi-vadc.yaml# --=20 2.25.1