From nobody Mon Feb 9 06:25:40 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B990242D6C for ; Fri, 30 Jan 2026 11:36:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769773008; cv=none; b=ISej5mH0g+n7qsrqE9NpKXzPLYloDCn6Ka01Ck9q/5fiLuNQjCzZ0MFgbqcfFsTWLXSBBf7zU1qwOs7YGAP6g9rJgiOu6HKTK1zkSe/2TBh6dDFmdt049GzpfGo700WZz+QRPXpLUqgKlmejtXfHTOaMQIa2MaS7DNsyMoLoRXs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769773008; c=relaxed/simple; bh=W0C3APLi4li8HiYOML4rZyGmR1k49qqeIQYJoYVIhKs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BTtDDkec0BPxPkZ6CNTGvi5O5KmQf65rKFFln3KG2mIhSIhgjqScw3nNcriD2YCgj5SDfxxB1rM2un3DJHKYdDOVNTJgibZ+RyPpmCuBILsqRmS8giB/XoNz2THaEzhIxOrvZU4mAbPx1xNXFu8+5Ce0hYKE2KkfnTXq32I/oeU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id CB9D25BCE2; Fri, 30 Jan 2026 11:36:44 +0000 (UTC) Authentication-Results: smtp-out2.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 851E13EA61; Fri, 30 Jan 2026 11:36:44 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 3Ac9H8yXfGlXHgAAD6G6ig (envelope-from ); Fri, 30 Jan 2026 11:36:44 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v2 3/4] x86/mtrr: Add a prepare_set hook to mtrr_ops Date: Fri, 30 Jan 2026 12:36:24 +0100 Message-ID: <20260130113625.599305-4-jgross@suse.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260130113625.599305-1-jgross@suse.com> References: <20260130113625.599305-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Spam-Flag: NO X-Spam-Score: -4.00 X-Rspamd-Queue-Id: CB9D25BCE2 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spam-Level: Content-Type: text/plain; charset="utf-8" In order to prepare dropping the cache_disable_lock add a new hook to struct mtrr_ops, allowing to set some global state before calling the .set hook on all active CPUs. Move setting of mtrr_state.var_ranges[] from generic_set_mtrr() to the new prepare hook. Note that doing that only once outside the cache_disable_lock is fine, as generic_set_mtrr() is called via set_mtrr() only and this call is protected by mtrr_mutex. Signed-off-by: Juergen Gross --- arch/x86/kernel/cpu/mtrr/generic.c | 32 ++++++++++++++++++++++++------ arch/x86/kernel/cpu/mtrr/mtrr.c | 3 +++ arch/x86/kernel/cpu/mtrr/mtrr.h | 2 ++ 3 files changed, 31 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index 7d9e582a4048..d49e1837a7af 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -1059,6 +1059,31 @@ void mtrr_generic_set_state(void) cache_enable(&state); } =20 +/** + * generic_prepare_set_mtrr - set variable MTRR register data in mtrr_state + * + * @reg: The register to set. + * @base: The base address of the region. + * @size: The size of the region. If this is 0 the region is disabled. + * @type: The type of the region. + * + * Returns nothing. + */ +static void generic_prepare_set_mtrr(unsigned int reg, unsigned long base, + unsigned long size, mtrr_type type) +{ + struct mtrr_var_range *vr =3D &mtrr_state.var_ranges[reg]; + + if (size =3D=3D 0) { + memset(vr, 0, sizeof(struct mtrr_var_range)); + } else { + vr->base_lo =3D base << PAGE_SHIFT | type; + vr->base_hi =3D (base >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; + vr->mask_lo =3D -size << PAGE_SHIFT | MTRR_PHYSMASK_V; + vr->mask_hi =3D (-size >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; + } +} + /** * generic_set_mtrr - set variable MTRR register on the local CPU. * @@ -1087,13 +1112,7 @@ static void generic_set_mtrr(unsigned int reg, unsig= ned long base, * clear the relevant mask register to disable a range. */ mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0); - memset(vr, 0, sizeof(struct mtrr_var_range)); } else { - vr->base_lo =3D base << PAGE_SHIFT | type; - vr->base_hi =3D (base >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; - vr->mask_lo =3D -size << PAGE_SHIFT | MTRR_PHYSMASK_V; - vr->mask_hi =3D (-size >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; - mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); } @@ -1158,6 +1177,7 @@ int positive_have_wrcomb(void) const struct mtrr_ops generic_mtrr_ops =3D { .get =3D generic_get_mtrr, .get_free_region =3D generic_get_free_region, + .prepare_set =3D generic_prepare_set_mtrr, .set =3D generic_set_mtrr, .validate_add_page =3D generic_validate_add_page, .have_wrcomb =3D generic_have_wrcomb, diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 4b3d492afe17..32948fb4e742 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -175,6 +175,9 @@ static void set_mtrr(unsigned int reg, unsigned long ba= se, unsigned long size, .smp_type =3D type }; =20 + if (mtrr_if->prepare_set) + mtrr_if->prepare_set(reg, base, size, type); + stop_machine_cpuslocked(mtrr_rendezvous_handler, &data, cpu_online_mask); =20 generic_rebuild_map(); diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtr= r.h index 2de3bd2f95d1..4d32c095cfc5 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.h +++ b/arch/x86/kernel/cpu/mtrr/mtrr.h @@ -17,6 +17,8 @@ extern unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; =20 struct mtrr_ops { u32 var_regs; + void (*prepare_set)(unsigned int reg, unsigned long base, + unsigned long size, mtrr_type type); void (*set)(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type); void (*get)(unsigned int reg, unsigned long *base, --=20 2.52.0