From nobody Mon Feb 9 05:40:07 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D7D036C0D9 for ; Fri, 30 Jan 2026 11:36:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769773003; cv=none; b=aRpEGX3z7XuEvOoik6Mm1mzQmJbf3iNjOLKSXftKNIYQpfPkT6c0zdBg2PYBKr4N942VbXImOjfd/I7EVH3mcqfw6U9lvgpFAYGR7eWOC15d7nuEkMDHeN/hTWBORyTHwu3/+c4ttlBCNpS6flkuC68qV0jKXyJJHsMRStVQu3M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769773003; c=relaxed/simple; bh=yNGdYUk2EXwzFDzR5TYecDEyFxfOdywkX3lirC6lR2I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Eh59sroiu2Vdob8gnqLSaXkpaX4Hh7OBqXXTQzJdT1NTwGcUwmIaDOcUMNNKecJi1gtQ2I4cO7cujZ3cAuWyIVH7320b+Bjz1lf5sDnTFN6BEFjVQAlUh0LoW7DiNn6IcLtWZyJrVdbjAoq6uLJWhVzkBpjPUs1SNrZmRj7A2Zk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 3D13D3468F; Fri, 30 Jan 2026 11:36:39 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id F1E973EA61; Fri, 30 Jan 2026 11:36:38 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 8v3TOcaXfGm0HQAAD6G6ig (envelope-from ); Fri, 30 Jan 2026 11:36:38 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v2 2/4] x86/mtrr: Introduce MTRR work state structure Date: Fri, 30 Jan 2026 12:36:23 +0100 Message-ID: <20260130113625.599305-3-jgross@suse.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260130113625.599305-1-jgross@suse.com> References: <20260130113625.599305-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Spam-Flag: NO X-Spam-Score: -4.00 X-Rspamd-Queue-Id: 3D13D3468F X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spam-Level: Content-Type: text/plain; charset="utf-8" Instead of using static variables for storing local state across cache_disable() ... cache_enable(), use a structure allocated on the stack for the same purpose. Signed-off-by: Juergen Gross --- V2: - add parameter description to set_mtrr_state() (kernel test robot) --- arch/x86/kernel/cpu/mtrr/generic.c | 60 ++++++++++++++++-------------- 1 file changed, 33 insertions(+), 27 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index 2c874b88e12c..7d9e582a4048 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -905,18 +905,21 @@ static bool set_mtrr_var_ranges(unsigned int index, s= truct mtrr_var_range *vr) return changed; } =20 -static u32 deftype_lo, deftype_hi; +struct mtrr_work_state { + unsigned long cr4; + u32 lo; + u32 hi; +}; =20 /** * set_mtrr_state - Set the MTRR state for this CPU. * - * NOTE: The CPU must already be in a safe state for MTRR changes, includi= ng - * measures that only a single CPU can be active in set_mtrr_state()= in - * order to not be subject to races for usage of deftype_lo. This is - * accomplished by taking cache_disable_lock. + * NOTE: The CPU must already be in a safe state for MTRR changes. + * + * @state: pointer to mtrr_work_state * RETURNS: 0 if no changes made, else a mask indicating what was changed. */ -static unsigned long set_mtrr_state(void) +static unsigned long set_mtrr_state(struct mtrr_work_state *state) { unsigned long change_mask =3D 0; unsigned int i; @@ -933,10 +936,10 @@ static unsigned long set_mtrr_state(void) * Set_mtrr_restore restores the old value of MTRRdefType, * so to set it we fiddle with the saved value: */ - if ((deftype_lo & MTRR_DEF_TYPE_TYPE) !=3D mtrr_state.def_type || - ((deftype_lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT) !=3D mtrr_s= tate.enabled) { + if ((state->lo & MTRR_DEF_TYPE_TYPE) !=3D mtrr_state.def_type || + ((state->lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT) !=3D mtrr_st= ate.enabled) { =20 - deftype_lo =3D (deftype_lo & MTRR_DEF_TYPE_DISABLE) | + state->lo =3D (state->lo & MTRR_DEF_TYPE_DISABLE) | mtrr_state.def_type | (mtrr_state.enabled << MTRR_STATE_SHIFT); change_mask |=3D MTRR_CHANGE_MASK_DEFTYPE; @@ -945,19 +948,19 @@ static unsigned long set_mtrr_state(void) return change_mask; } =20 -static void mtrr_disable(void) +static void mtrr_disable(struct mtrr_work_state *state) { /* Save MTRR state */ - rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); + rdmsr(MSR_MTRRdefType, state->lo, state->hi); =20 /* Disable MTRRs, and set the default type to uncached */ - mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & MTRR_DEF_TYPE_DISABLE, deftype_h= i); + mtrr_wrmsr(MSR_MTRRdefType, state->lo & MTRR_DEF_TYPE_DISABLE, state->hi); } =20 -static void mtrr_enable(void) +static void mtrr_enable(struct mtrr_work_state *state) { /* Intel (P6) standard MTRRs */ - mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); + mtrr_wrmsr(MSR_MTRRdefType, state->lo, state->hi); } =20 /* @@ -969,7 +972,6 @@ static void mtrr_enable(void) * The caller must ensure that local interrupts are disabled and * are reenabled after cache_enable() has been called. */ -static unsigned long saved_cr4; static DEFINE_RAW_SPINLOCK(cache_disable_lock); =20 /* @@ -983,7 +985,8 @@ static void maybe_flush_caches(void) wbinvd(); } =20 -static void cache_disable(void) __acquires(cache_disable_lock) +static void cache_disable(struct mtrr_work_state *state) + __acquires(cache_disable_lock) { unsigned long cr0; =20 @@ -1002,8 +1005,8 @@ static void cache_disable(void) __acquires(cache_disa= ble_lock) =20 /* Save value of CR4 and clear Page Global Enable (bit 7) */ if (cpu_feature_enabled(X86_FEATURE_PGE)) { - saved_cr4 =3D __read_cr4(); - __write_cr4(saved_cr4 & ~X86_CR4_PGE); + state->cr4 =3D __read_cr4(); + __write_cr4(state->cr4 & ~X86_CR4_PGE); } =20 /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */ @@ -1011,26 +1014,27 @@ static void cache_disable(void) __acquires(cache_di= sable_lock) flush_tlb_local(); =20 if (cpu_feature_enabled(X86_FEATURE_MTRR)) - mtrr_disable(); + mtrr_disable(state); =20 maybe_flush_caches(); } =20 -static void cache_enable(void) __releases(cache_disable_lock) +static void cache_enable(struct mtrr_work_state *state) + __releases(cache_disable_lock) { /* Flush TLBs (no need to flush caches - they are disabled) */ count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); flush_tlb_local(); =20 if (cpu_feature_enabled(X86_FEATURE_MTRR)) - mtrr_enable(); + mtrr_enable(state); =20 /* Enable caches */ write_cr0(read_cr0() & ~X86_CR0_CD); =20 /* Restore value of CR4 */ if (cpu_feature_enabled(X86_FEATURE_PGE)) - __write_cr4(saved_cr4); + __write_cr4(state->cr4); =20 raw_spin_unlock(&cache_disable_lock); } @@ -1038,11 +1042,12 @@ static void cache_enable(void) __releases(cache_dis= able_lock) void mtrr_generic_set_state(void) { unsigned long mask, count; + struct mtrr_work_state state; =20 - cache_disable(); + cache_disable(&state); =20 /* Actually set the state */ - mask =3D set_mtrr_state(); + mask =3D set_mtrr_state(&state); =20 /* Use the atomic bitops to update the global mask */ for (count =3D 0; count < sizeof(mask) * 8; ++count) { @@ -1051,7 +1056,7 @@ void mtrr_generic_set_state(void) mask >>=3D 1; } =20 - cache_enable(); + cache_enable(&state); } =20 /** @@ -1069,11 +1074,12 @@ static void generic_set_mtrr(unsigned int reg, unsi= gned long base, { unsigned long flags; struct mtrr_var_range *vr; + struct mtrr_work_state state; =20 vr =3D &mtrr_state.var_ranges[reg]; =20 local_irq_save(flags); - cache_disable(); + cache_disable(&state); =20 if (size =3D=3D 0) { /* @@ -1092,7 +1098,7 @@ static void generic_set_mtrr(unsigned int reg, unsign= ed long base, mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); } =20 - cache_enable(); + cache_enable(&state); local_irq_restore(flags); } =20 --=20 2.52.0