From nobody Sun Feb 8 23:35:09 2026 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDC96376BFA for ; Thu, 29 Jan 2026 23:29:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769729345; cv=none; b=XhzIpn34SK+Edk0BbdCe8zaootj2zCS7g0hPsmYNLN6jE5fr8gFde/BQm4Pi2E+h+lD1RbH5DEVht1EFpFbRdvVjU6a1gyXWNJYAeWuW45WKI5j1fzRQjE2RliGoPMX4WHaIP/6g1whRZY1AZXuGVq3WTqGtYe3FcH0UB2HfVAo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769729345; c=relaxed/simple; bh=rxUIt+q7usKdyM83oKGeQOrRZ8jjXQg7Zut/P6eD5vQ=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=pr2zBRcUgaW5pJnqk+N3qpOZEKhBXce1/tALBw9XKQfqtkllO8YULxsJOYmWixtO/0nUy1KoL2RO3pbSpJuMdn2aXjjp/hNkEFsMiioctHBmQg54cTCCVqluMNWuaznfKiglzTM+0L+scvwyj4nN+ZoClHWj72idmUjE51QkxzQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=iYXjNALK; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--jmattson.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="iYXjNALK" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-352c7924ebcso1510434a91.3 for ; Thu, 29 Jan 2026 15:29:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1769729343; x=1770334143; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=kJF3W6JKHBnrv8F/Fuh9dIOMXuUt3tlkhxE5lP4gDnc=; b=iYXjNALKQ8O1HQZYHDQ0LHCC0KceNhjV2qSJkGPmIvgbrCPwCtV51TaB61q07UztNz +5lkzS3/VULs1EuR3EMS1Xcc9MuM+21OwyTXNr05gbMxNncjiAfZqi3pYuDw9v2WvLJu zQOjaXiD2c5UvXiyzzLJ3YiANbOgOnFMboo9ZyH23f0LX3U4UOiVdYWWMGpaVSzZv2jB vftLHxN6kqRrCbwEB7Uo39senSQPnfVc74luO/HkAKYy8nUzTuEEGAYmjUq1QNrT8yr0 LRZlkM40PWVvnES7MXFkhBwq1LpLTB2t+ajELA9jvSvV1TQRG/Pe9XKJyogkxhCrsqbB XpNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769729343; x=1770334143; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=kJF3W6JKHBnrv8F/Fuh9dIOMXuUt3tlkhxE5lP4gDnc=; b=wbOO934LrE5Mb+c78xCi3RSrBwpQa26d8gTosT4ZwYgmXeNKqmbBqoskRXAMQwp1pP swvHZGL5B1g5mxyPtJwAxGZYhjgBG9H3eXpqLFNUgVSVULYdgK5ynpRC34GGb4xGP88D K0tNgcPPruHnFISc5nwxPdUxczdUNf5Y7hwW68PZJO478W0CwIK0A4eGQjR7PwtIRwAR 1NLiWoGlbUlQeURgYuJTJcI4gc5XqKnZq3i2mOFRwd4pclBqRrHvdonP43WB56DqZ1bK IuGxR08ttUEtZ6YcPVTcvlWE7e0AkZDj+Rg87sxoXZLExmr/Ejhe44Na5BXKmjC176wV oZxA== X-Forwarded-Encrypted: i=1; AJvYcCUJiDH9+oYTRn/fO4weQNiiVOU/ZgbYtg1lWphePkHRB1Q+7dONGXFk8ItCss4IXzeMxW9DhGMGOIErITo=@vger.kernel.org X-Gm-Message-State: AOJu0YzQdRF+0MrZMJiVOu6/aKgBdsjzTiQDZ5P6VB0tMW2rhsyJl/1m j5UllBHEQdEf6wmcM9XrmIua9rrF08HioRzW7tzgT4aT0qqsgsCU9BQNWlHmGmQecsBibSm/AyN Q93P6dM6zmPzM4A== X-Received: from pjvf5.prod.google.com ([2002:a17:90a:da85:b0:352:d19a:6739]) (user=jmattson job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:518e:b0:34f:62e7:4cec with SMTP id 98e67ed59e1d1-3543b2e00c9mr820536a91.5.1769729343203; Thu, 29 Jan 2026 15:29:03 -0800 (PST) Date: Thu, 29 Jan 2026 15:28:07 -0800 In-Reply-To: <20260129232835.3710773-1-jmattson@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260129232835.3710773-1-jmattson@google.com> X-Mailer: git-send-email 2.53.0.rc1.225.gd81095ad13-goog Message-ID: <20260129232835.3710773-3-jmattson@google.com> Subject: [PATCH v2 2/5] KVM: x86/pmu: Disable Host-Only/Guest-Only events as appropriate for vCPU state From: Jim Mattson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Thomas Gleixner , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Sean Christopherson , Paolo Bonzini , Shuah Khan , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: mizhang@google.com, yosryahmed@google.com, sandipan.das@amd.com, Jim Mattson Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update amd_pmu_set_eventsel_hw() to clear the event selector's hardware enable bit when the PMC should not count based on the guest's Host-Only and Guest-Only event selector bits and the current vCPU state. Signed-off-by: Jim Mattson --- arch/x86/include/asm/perf_event.h | 2 ++ arch/x86/kvm/svm/pmu.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 0d9af4135e0a..4dfe12053c09 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -58,6 +58,8 @@ #define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36) #define AMD64_EVENTSEL_GUESTONLY (1ULL << 40) #define AMD64_EVENTSEL_HOSTONLY (1ULL << 41) +#define AMD64_EVENTSEL_HOST_GUEST_MASK \ + (AMD64_EVENTSEL_HOSTONLY | AMD64_EVENTSEL_GUESTONLY) =20 #define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37 #define AMD64_EVENTSEL_INT_CORE_SEL_MASK \ diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index d9ca633f9f49..8d451110a94d 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -149,8 +149,26 @@ static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, stru= ct msr_data *msr_info) =20 static void amd_pmu_set_eventsel_hw(struct kvm_pmc *pmc) { + struct kvm_vcpu *vcpu =3D pmc->vcpu; + u64 host_guest_bits; + pmc->eventsel_hw =3D (pmc->eventsel & ~AMD64_EVENTSEL_HOSTONLY) | AMD64_EVENTSEL_GUESTONLY; + + if (!(pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE)) + return; + + if (!(vcpu->arch.efer & EFER_SVME)) + return; + + host_guest_bits =3D pmc->eventsel & AMD64_EVENTSEL_HOST_GUEST_MASK; + if (!host_guest_bits || host_guest_bits =3D=3D AMD64_EVENTSEL_HOST_GUEST_= MASK) + return; + + if (!!(host_guest_bits & AMD64_EVENTSEL_GUESTONLY) =3D=3D is_guest_mode(v= cpu)) + return; + + pmc->eventsel_hw &=3D ~ARCH_PERFMON_EVENTSEL_ENABLE; } =20 static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_inf= o) --=20 2.53.0.rc1.225.gd81095ad13-goog