From nobody Mon Feb 9 04:29:28 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A10432BF41 for ; Thu, 29 Jan 2026 21:20:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769721652; cv=none; b=a+h0nKMMUrOzPEmWMkmO+vBNCgFPcKYfCiXP7NvPKaBcJHh8EJrjrkQK1ywvLOK4FKfU/5zrntchEkBrO2t8Yp7+MeLprgW2LIf1sDaVjZgMw0xWWhgiv6SvmFyI+V/1fbh3eFMyk+McuvCT5OaO/8uIEJSrtrGobD+fPdaXDIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769721652; c=relaxed/simple; bh=UEJlX4J/2boPxUiReU5shp9ksK4e3wEpbVT9jC6jVMM=; h=Date:Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type; b=Mh/klGWDRCxl+GqnSBoEqAIc3NG/DY5+LnJJ1RSno3Vw4mlZC7tl8n2kKuX1dRbP6snKHfy1fSYwYi9eNUjAHdpi3gNNRwM0s9xH/mNiZWBs3ovPandGmJjKMzx8dk4Vv9F/zrHeNBMYyec7UgEOBEyeoLwUKCFhkLU+vZUGi3g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=kernel.org; spf=pass smtp.mailfrom=linutronix.de; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=kernel.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Date: Thu, 29 Jan 2026 22:20:48 +0100 Message-ID: <20260129211557.678686545@kernel.org> From: Thomas Gleixner To: LKML Cc: Ihor Solodrai , Shrikanth Hegde , Peter Zijlstra , Mathieu Desnoyers , Michael Jeanson Subject: [patch 1/4] sched/mmcid: Prevent live lock on task to CPU mode transition References: <20260129210219.452851594@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ihor reported a BPF CI failure which turned out to be a live lock in the MM_CID management. The scenario is: A test program creates the 4th child, which means the MM_CID users become more than the number of CPUs (four in this example), so it switches to per CPU ownership mode. At this point each live task of the program has a CID associated. Assume thread creation order assignment for simplicity. T0 (main thread) CID0 runs fork() and creates T4 T1 (1st child) CID1 T2 (2nd child) CID2 T3 (3rd child) CID3 T4 (4th child) --- not visible yet T0 sets mm_cid::percpu =3D true and transfers it's own CID to CPU0 where it runs on and then starts the fixup which walks through the threads to transfer the per task CIDs either to the CPU the task is running on or drop it back into the pool if the task is not on a CPU. During that T1 - T3 are free to schedule in and out before the fixup caught up with them. Going through all possible permutations with a python script revealed a few problematic cases. The most trivial one is: T1 schedules in on CPU1 and observes percpu =3D=3D true, so it transfers it's CID to CPU1 T1 is migrated to CPU1 and schedule in observes percpu =3D=3D true, but CPU2 does not have a CID associated and T1 transferred it's own to CPU1 So it has to allocate one with CPU2 runqueue lock held, but the pool is empty, so it keeps looping in mm_get_cid(). Now T0 reaches T1 in the thread walk and tries to lock the corresponding runqueue lock, which is held causing a full live lock. There is a similar scenario in the reverse direction of switching from per CPU to task mode which is way more obvious and got therefore addressed by an intermediate mode. In this mode the CIDs are marked with MM_CID_TRANSIT, which means that they are neither owned by the CPU nor by the task. When a task schedules out with a transit CID it drops the CID back into the pool making it available for others to use temporarily. Once the task which initiated the mode switch finished the fixup it clears the transit mode and the process goes back into per task ownership mode. Unfortunately this insight was not mapped back to the task to CPU mode switch as the above described scenario was not considered in the analysis. Apply the same transit mechanism to the task to CPU mode switch to handle these problematic cases correctly. As with the CPU to task transition this results in a potential temporary contention on the CID bitmap, but that's only for the time it takes to complete the transition. After that it stays in steady mode which does not touch the bitmap at all. Fixes: fbd0e71dc370 ("sched/mmcid: Provide CID ownership mode fixup functio= ns") Reported-by: Ihor Solodrai Signed-off-by: Thomas Gleixner Closes: https://lore.kernel.org/2b7463d7-0f58-4e34-9775-6e2115cfb971@linux.= dev --- kernel/sched/core.c | 118 ++++++++++++++++++++++++++++++++--------------= ----- kernel/sched/sched.h | 4 + 2 files changed, 80 insertions(+), 42 deletions(-) --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -10269,7 +10269,8 @@ void call_trace_sched_update_nr_running( * Serialization rules: * * mm::mm_cid::mutex: Serializes fork() and exit() and therefore - * protects mm::mm_cid::users. + * protects mm::mm_cid::users and mode switch + * transitions * * mm::mm_cid::lock: Serializes mm_update_max_cids() and * mm_update_cpus_allowed(). Nests in mm_cid::mutex @@ -10285,14 +10286,61 @@ void call_trace_sched_update_nr_running( * * A CID is either owned by a task (stored in task_struct::mm_cid.cid) or * by a CPU (stored in mm::mm_cid.pcpu::cid). CIDs owned by CPUs have the - * MM_CID_ONCPU bit set. During transition from CPU to task ownership mode, - * MM_CID_TRANSIT is set on the per task CIDs. When this bit is set the - * task needs to drop the CID into the pool when scheduling out. Both bits - * (ONCPU and TRANSIT) are filtered out by task_cid() when the CID is - * actually handed over to user space in the RSEQ memory. + * MM_CID_ONCPU bit set. + * + * During the transition of ownership mode, the MM_CID_TRANSIT bit is set + * on the CIDs. When this bit is set the tasks drop the CID back into the + * pool when scheduling out. + * + * Both bits (ONCPU and TRANSIT) are filtered out by task_cid() when the + * CID is actually handed over to user space in the RSEQ memory. * * Mode switching: * + * All transitions of ownership mode happen in two phases: + * + * 1) mm:mm_cid.transit contains MM_CID_TRANSIT. This is OR'ed on the CIDs + * and denotes that the CID is only temporarily owned by a task. When + * the task schedules out it drops the CID back into the pool if this + * bit is set. + * + * 2) The initiating context walks the per CPU space or the tasks to fixup + * or drop the CIDs and after completion it clears mm:mm_cid.transit. + * After that point the CIDs are strictly task or CPU owned again. + * + * This two phase transition is required to prevent CID space exhaustion + * during the transition as a direct transfer of ownership would fail: + * + * - On task to CPU mode switch if a task is scheduled in on one CPU and + * then migrated to another CPU before the fixup freed enough per task + * CIDs. + * + * - On CPU to task mode switch if two tasks are scheduled in on the same + * CPU before the fixup freed per CPU CIDs. + * + * Both scenarios can result in a live lock because sched_in() is invoked + * with runqueue lock held and loops in search of a CID and the fixup + * thread can't make progress freeing them up because it is stuck on the + * same runqueue lock. + * + * While MM_CID_TRANSIT is active during the transition phase the MM_CID + * bitmap can be contended, but that's a temporary contention bound to the + * transition period. After that everything goes back into steady state and + * nothing except fork() and exit() will touch the bitmap. This is an + * acceptable tradeoff as it completely avoids complex serialization, + * memory barriers and atomic operations for the common case. + * + * Aside of that this mechanism also ensures RT compability: + * + * - The task which runs the fixup is fully preemptible except for the + * short runqueue lock held sections. + * + * - The transient impact of the bitmap contention is only problematic + * when there is a thundering herd scenario of tasks scheduling in and + * out concurrently. There is not much which can be done about that + * except for avoiding mode switching by a proper overall system + * configuration. + * * Switching to per CPU mode happens when the user count becomes greater * than the maximum number of CIDs, which is calculated by: * @@ -10306,12 +10354,13 @@ void call_trace_sched_update_nr_running( * * At the point of switching to per CPU mode the new user is not yet * visible in the system, so the task which initiated the fork() runs the - * fixup function: mm_cid_fixup_tasks_to_cpu() walks the thread list and - * either transfers each tasks owned CID to the CPU the task runs on or - * drops it into the CID pool if a task is not on a CPU at that point in - * time. Tasks which schedule in before the task walk reaches them do the - * handover in mm_cid_schedin(). When mm_cid_fixup_tasks_to_cpus() complet= es - * it's guaranteed that no task related to that MM owns a CID anymore. + * fixup function. mm_cid_fixup_tasks_to_cpu() walks the thread list and + * either marks each task owned CID with MM_CID_TRANSIT if the task is + * running on a CPU or drops it into the CID pool if a task is not on a + * CPU. Tasks which schedule in before the task walk reaches them do the + * handover in mm_cid_schedin(). When mm_cid_fixup_tasks_to_cpus() + * completes it is guaranteed that no task related to that MM owns a CID + * anymore. * * Switching back to task mode happens when the user count goes below the * threshold which was recorded on the per CPU mode switch: @@ -10327,28 +10376,11 @@ void call_trace_sched_update_nr_running( * run either in the deferred update function in context of a workqueue or * by a task which forks a new one or by a task which exits. Whatever * happens first. mm_cid_fixup_cpus_to_task() walks through the possible - * CPUs and either transfers the CPU owned CIDs to a related task which - * runs on the CPU or drops it into the pool. Tasks which schedule in on a - * CPU which the walk did not cover yet do the handover themself. - * - * This transition from CPU to per task ownership happens in two phases: - * - * 1) mm:mm_cid.transit contains MM_CID_TRANSIT This is OR'ed on the task - * CID and denotes that the CID is only temporarily owned by the - * task. When it schedules out the task drops the CID back into the - * pool if this bit is set. - * - * 2) The initiating context walks the per CPU space and after completion - * clears mm:mm_cid.transit. So after that point the CIDs are strictly - * task owned again. - * - * This two phase transition is required to prevent CID space exhaustion - * during the transition as a direct transfer of ownership would fail if - * two tasks are scheduled in on the same CPU before the fixup freed per - * CPU CIDs. - * - * When mm_cid_fixup_cpus_to_tasks() completes it's guaranteed that no CID - * related to that MM is owned by a CPU anymore. + * CPUs and either marks the CPU owned CIDs with MM_CID_TRANSIT if a + * related task is running on the CPU or drops it into the pool. Tasks + * which are scheduled in before the fixup covered them do the handover + * themself. When mm_cid_fixup_cpus_to_tasks() completes it is guaranteed + * that no CID related to that MM is owned by a CPU anymore. */ =20 /* @@ -10400,9 +10432,9 @@ static bool mm_update_max_cids(struct mm /* Mode change required? */ if (!!mc->percpu =3D=3D !!mc->pcpu_thrs) return false; - /* When switching back to per TASK mode, set the transition flag */ - if (!mc->pcpu_thrs) - WRITE_ONCE(mc->transit, MM_CID_TRANSIT); + + /* Set the transition flag to bridge the transfer */ + WRITE_ONCE(mc->transit, MM_CID_TRANSIT); WRITE_ONCE(mc->percpu, !!mc->pcpu_thrs); return true; } @@ -10493,10 +10525,10 @@ static void mm_cid_fixup_cpus_to_tasks(s WRITE_ONCE(mm->mm_cid.transit, 0); } =20 -static inline void mm_cid_transfer_to_cpu(struct task_struct *t, struct mm= _cid_pcpu *pcp) +static inline void mm_cid_transit_to_cpu(struct task_struct *t, struct mm_= cid_pcpu *pcp) { if (cid_on_task(t->mm_cid.cid)) { - t->mm_cid.cid =3D cid_to_cpu_cid(t->mm_cid.cid); + t->mm_cid.cid =3D cid_to_transit_cid(t->mm_cid.cid); pcp->cid =3D t->mm_cid.cid; } } @@ -10509,9 +10541,9 @@ static bool mm_cid_fixup_task_to_cpu(str if (!t->mm_cid.active) return false; if (cid_on_task(t->mm_cid.cid)) { - /* If running on the CPU, transfer the CID, otherwise drop it */ + /* If running on the CPU, put the CID in transit mode, otherwise drop it= */ if (task_rq(t)->curr =3D=3D t) - mm_cid_transfer_to_cpu(t, per_cpu_ptr(mm->mm_cid.pcpu, task_cpu(t))); + mm_cid_transit_to_cpu(t, per_cpu_ptr(mm->mm_cid.pcpu, task_cpu(t))); else mm_unset_cid_on_task(t); } @@ -10596,11 +10628,13 @@ void sched_mm_cid_fork(struct task_struc if (!percpu) mm_cid_transit_to_task(current, pcp); else - mm_cid_transfer_to_cpu(current, pcp); + mm_cid_transit_to_cpu(current, pcp); } =20 if (percpu) { mm_cid_fixup_tasks_to_cpus(); + /* Clear the transition bit */ + WRITE_ONCE(mm->mm_cid.transit, 0); } else { mm_cid_fixup_cpus_to_tasks(mm); t->mm_cid.cid =3D mm_get_cid(mm); --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -3841,6 +3841,10 @@ static __always_inline void mm_cid_from_ /* Still nothing, allocate a new one */ if (!cid_on_cpu(cpu_cid)) cpu_cid =3D cid_to_cpu_cid(mm_get_cid(mm)); + + /* Set the transition mode flag if required */ + if (READ_ONCE(mm->mm_cid.transit)) + cpu_cid =3D cpu_cid_to_cid(cpu_cid) | MM_CID_TRANSIT; } mm_cid_update_pcpu_cid(mm, cpu_cid); mm_cid_update_task_cid(t, cpu_cid); From nobody Mon Feb 9 04:29:28 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E70D3330669 for ; Thu, 29 Jan 2026 21:20:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769721654; cv=none; b=m+cfHaw0l5/8LWoe/THE9Bb7mMbq7Gh9xSuYbgmv98QX9jmiYG/LO0NVmly5VpONiRTWFHP0ae1y0u74KTBWgxU0QRimIQLOLTVWl3VCYUhP1qiAE7vwIvQZutrvRj8oId7J7ndHXT7Mu8yTyJuwO97oFNADy8XCU0zaD6BFU44= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769721654; c=relaxed/simple; bh=G1s2Cf9dZFJEaaNqVr80DfyAnGNRgB9BFSiHi2icO4I=; h=Date:Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type; b=Vj86uuVqUAr/lSv211HzwQpsq/nBkMMEL1iub0cqH2r39EOSwEFjPExp8qUt/rsokpISnEoj7PzUAO1eimPIhNti3JsOYxLnS4+8Gy0SLyj7FckFl1ju7MAR//k3W7gkukIGXnEY6qHAP9x9sdkVO60sArm4ENCra8+dR7SKlI0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=kernel.org; spf=pass smtp.mailfrom=linutronix.de; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=kernel.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Date: Thu, 29 Jan 2026 22:20:50 +0100 Message-ID: <20260129211557.746946556@kernel.org> From: Thomas Gleixner To: LKML Cc: Ihor Solodrai , Shrikanth Hegde , Peter Zijlstra , Mathieu Desnoyers , Michael Jeanson Subject: [patch 2/4] sched/mmcid: Protect transition on weakly ordered systems References: <20260129210219.452851594@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Shrikanth reported a hard lockup which he observed once. The stack trace shows the following CID related participants: watchdog: CPU 23 self-detected hard LOCKUP @ mm_get_cid+0xe8/0x188 NIP: mm_get_cid+0xe8/0x188 LR: mm_get_cid+0x108/0x188 mm_cid_switch_to+0x3c4/0x52c __schedule+0x47c/0x700 schedule_idle+0x3c/0x64 do_idle+0x160/0x1b0 cpu_startup_entry+0x48/0x50 start_secondary+0x284/0x288 start_secondary_prolog+0x10/0x14 watchdog: CPU 11 self-detected hard LOCKUP @ plpar_hcall_norets_notrace+0= x18/0x2c NIP: plpar_hcall_norets_notrace+0x18/0x2c LR: queued_spin_lock_slowpath+0xd88/0x15d0 _raw_spin_lock+0x80/0xa0 raw_spin_rq_lock_nested+0x3c/0xf8 mm_cid_fixup_cpus_to_tasks+0xc8/0x28c sched_mm_cid_exit+0x108/0x22c do_exit+0xf4/0x5d0 make_task_dead+0x0/0x178 system_call_exception+0x128/0x390 system_call_vectored_common+0x15c/0x2ec The task on CPU11 is running the CID ownership mode change fixup function and is stuck on a runqueue lock. The task on CPU23 is trying to get a CID from the pool with the same runqueue lock held, but the pool is empty. After decoding a similar issue in the opposite direction switching from per task to per CPU mode the tool which models the possible scenarios failed to come up with a similar loop hole. This showed up only once, was not reproducible and according to tooling not related to a overlooked scheduling scenario permutation. But the fact that it was observed on a PowerPC system gave the right hint: PowerPC is a weakly ordered architecture. The transition mechanism does: WRITE_ONCE(mm->mm_cid.transit, MM_CID_TRANSIT); WRITE_ONCE(mm->mm_cid.percpu, new_mode); fixup() =20 WRITE_ONCE(mm->mm_cid.transit, 0); mm_cid_schedin() does: if (!READ_ONCE(mm->mm_cid.percpu)) ... cid |=3D READ_ONCE(mm->mm_cid.transit); so weakly ordered systems can observe percpu =3D=3D false and transit =3D= =3D 0 even if the fixup function has not yet completed. As a consequence the task will not drop the CID when scheduling out before the fixup is completed, which means the CID space can be exhausted and the next task scheduling in will loop in mm_get_cid() and the fixup thread can livelock on the held runqueue lock as above. This could obviously be solved by using: smp_store_release(&mm->mm_cid.percpu, true); and =20 smp_load_acquire(&mm->mm_cid.percpu); but that brings a memory barrier back into the scheduler hotpath, which was just designed out by the CID rewrite. That can be completely avoided by combining the per CPU mode and the transit storage into a single mm_cid::mode member. That makes the update of both states atomic and a concurrent read observes always consistent state. The price is an additional AND operation in mm_cid_schedin() to evaluate the per CPU or the per task path, but that's in the noise even on strongly ordered architectures as the actual load can be significantly more expensive and the conditional branch evaluation is there anyway. Fixes: fbd0e71dc370 ("sched/mmcid: Provide CID ownership mode fixup functio= ns") Reported-by: Shrikanth Hegde Signed-off-by: Thomas Gleixner Closes: https://lore.kernel.org/bdfea828-4585-40e8-8835-247c6a8a76b0@linux.= ibm.com --- include/linux/rseq_types.h | 7 ++--- kernel/sched/core.c | 62 +++++++++++++++++++++++++++-------------= ----- kernel/sched/sched.h | 21 ++++++++------- 3 files changed, 53 insertions(+), 37 deletions(-) --- a/include/linux/rseq_types.h +++ b/include/linux/rseq_types.h @@ -121,8 +121,7 @@ struct mm_cid_pcpu { /** * struct mm_mm_cid - Storage for per MM CID data * @pcpu: Per CPU storage for CIDs associated to a CPU - * @percpu: Set, when CIDs are in per CPU mode - * @transit: Set to MM_CID_TRANSIT during a mode change transition phase + * @mode: Indicates per CPU and transition mode * @max_cids: The exclusive maximum CID value for allocation and converge= nce * @irq_work: irq_work to handle the affinity mode change case * @work: Regular work to handle the affinity mode change case @@ -134,13 +133,13 @@ struct mm_cid_pcpu { * as that is modified by mmget()/mm_put() by other entities which * do not actually share the MM. * @pcpu_thrs: Threshold for switching back from per CPU mode + * @mode_change: Mode change in progress * @update_deferred: A deferred switch back to per task mode is pending. */ struct mm_mm_cid { /* Hotpath read mostly members */ struct mm_cid_pcpu __percpu *pcpu; - unsigned int percpu; - unsigned int transit; + unsigned int mode; unsigned int max_cids; =20 /* Rarely used. Moves @lock and @mutex into the second cacheline */ --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -10297,16 +10297,25 @@ void call_trace_sched_update_nr_running( * * Mode switching: * + * The ownership mode is per process and stored in mm:mm_cid::mode with the + * following possible states: + * + * 0: Per task ownership + * 0 | MM_CID_TRANSIT: Transition from per CPU to per task + * MM_CID_ONCPU: Per CPU ownership + * MM_CID_ONCPU | MM_CID_TRANSIT: Transition from per task to per CPU + * * All transitions of ownership mode happen in two phases: * - * 1) mm:mm_cid.transit contains MM_CID_TRANSIT. This is OR'ed on the CIDs - * and denotes that the CID is only temporarily owned by a task. When - * the task schedules out it drops the CID back into the pool if this - * bit is set. + * 1) mm:mm_cid::mode has the MM_CID_TRANSIT bit set. This is OR'ed on the + * CIDs and denotes that the CID is only temporarily owned by a + * task. When the task schedules out it drops the CID back into the + * pool if this bit is set. * * 2) The initiating context walks the per CPU space or the tasks to fixup - * or drop the CIDs and after completion it clears mm:mm_cid.transit. - * After that point the CIDs are strictly task or CPU owned again. + * or drop the CIDs and after completion it clears MM_CID_TRANSIT in + * mm:mm_cid::mode. After that point the CIDs are strictly task or CPU + * owned again. * * This two phase transition is required to prevent CID space exhaustion * during the transition as a direct transfer of ownership would fail: @@ -10411,6 +10420,7 @@ static inline unsigned int mm_cid_calc_p static bool mm_update_max_cids(struct mm_struct *mm) { struct mm_mm_cid *mc =3D &mm->mm_cid; + bool percpu =3D cid_on_cpu(mc->mode); =20 lockdep_assert_held(&mm->mm_cid.lock); =20 @@ -10419,7 +10429,7 @@ static bool mm_update_max_cids(struct mm __mm_update_max_cids(mc); =20 /* Check whether owner mode must be changed */ - if (!mc->percpu) { + if (!percpu) { /* Enable per CPU mode when the number of users is above max_cids */ if (mc->users > mc->max_cids) mc->pcpu_thrs =3D mm_cid_calc_pcpu_thrs(mc); @@ -10430,12 +10440,11 @@ static bool mm_update_max_cids(struct mm } =20 /* Mode change required? */ - if (!!mc->percpu =3D=3D !!mc->pcpu_thrs) + if (percpu =3D=3D !!mc->pcpu_thrs) return false; =20 - /* Set the transition flag to bridge the transfer */ - WRITE_ONCE(mc->transit, MM_CID_TRANSIT); - WRITE_ONCE(mc->percpu, !!mc->pcpu_thrs); + /* Flip the mode and set the transition flag to bridge the transfer */ + WRITE_ONCE(mc->mode, mc->mode ^ (MM_CID_TRANSIT | MM_CID_ONCPU)); return true; } =20 @@ -10460,7 +10469,7 @@ static inline void mm_update_cpus_allowe =20 WRITE_ONCE(mc->nr_cpus_allowed, weight); __mm_update_max_cids(mc); - if (!mc->percpu) + if (!cid_on_cpu(mc->mode)) return; =20 /* Adjust the threshold to the wider set */ @@ -10521,8 +10530,8 @@ static void mm_cid_fixup_cpus_to_tasks(s } } } - /* Clear the transition bit */ - WRITE_ONCE(mm->mm_cid.transit, 0); + /* Clear the transition bit in the mode */ + WRITE_ONCE(mm->mm_cid.mode, 0); } =20 static inline void mm_cid_transit_to_cpu(struct task_struct *t, struct mm_= cid_pcpu *pcp) @@ -10550,9 +10559,8 @@ static bool mm_cid_fixup_task_to_cpu(str return true; } =20 -static void mm_cid_fixup_tasks_to_cpus(void) +static void mm_cid_do_fixup_tasks_to_cpus(struct mm_struct *mm) { - struct mm_struct *mm =3D current->mm; struct task_struct *p, *t; unsigned int users; =20 @@ -10590,6 +10598,15 @@ static void mm_cid_fixup_tasks_to_cpus(v } } =20 +static void mm_cid_fixup_tasks_to_cpus(void) +{ + struct mm_struct *mm =3D current->mm; + + mm_cid_do_fixup_tasks_to_cpus(mm); + /* Clear the transition bit in the mode */ + WRITE_ONCE(mm->mm_cid.mode, MM_CID_ONCPU); +} + static bool sched_mm_cid_add_user(struct task_struct *t, struct mm_struct = *mm) { t->mm_cid.active =3D 1; @@ -10618,13 +10635,13 @@ void sched_mm_cid_fork(struct task_struc } =20 if (!sched_mm_cid_add_user(t, mm)) { - if (!mm->mm_cid.percpu) + if (!cid_on_cpu(mm->mm_cid.mode)) t->mm_cid.cid =3D mm_get_cid(mm); return; } =20 /* Handle the mode change and transfer current's CID */ - percpu =3D !!mm->mm_cid.percpu; + percpu =3D cid_on_cpu(mm->mm_cid.mode); if (!percpu) mm_cid_transit_to_task(current, pcp); else @@ -10633,8 +10650,6 @@ void sched_mm_cid_fork(struct task_struc =20 if (percpu) { mm_cid_fixup_tasks_to_cpus(); - /* Clear the transition bit */ - WRITE_ONCE(mm->mm_cid.transit, 0); } else { mm_cid_fixup_cpus_to_tasks(mm); t->mm_cid.cid =3D mm_get_cid(mm); @@ -10665,7 +10680,7 @@ static bool __sched_mm_cid_exit(struct t * affinity change increased the number of allowed CPUs and the * deferred fixup did not run yet. */ - if (WARN_ON_ONCE(mm->mm_cid.percpu)) + if (WARN_ON_ONCE(cid_on_cpu(mm->mm_cid.mode))) return false; /* * A failed fork(2) cleanup never gets here, so @current must have @@ -10756,7 +10771,7 @@ static void mm_cid_work_fn(struct work_s if (!mm_update_max_cids(mm)) return; /* Affinity changes can only switch back to task mode */ - if (WARN_ON_ONCE(mm->mm_cid.percpu)) + if (WARN_ON_ONCE(cid_on_cpu(mm->mm_cid.mode))) return; } mm_cid_fixup_cpus_to_tasks(mm); @@ -10777,8 +10792,7 @@ static void mm_cid_irq_work(struct irq_w void mm_init_cid(struct mm_struct *mm, struct task_struct *p) { mm->mm_cid.max_cids =3D 0; - mm->mm_cid.percpu =3D 0; - mm->mm_cid.transit =3D 0; + mm->mm_cid.mode =3D 0; mm->mm_cid.nr_cpus_allowed =3D p->nr_cpus_allowed; mm->mm_cid.users =3D 0; mm->mm_cid.pcpu_thrs =3D 0; --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -3816,7 +3816,8 @@ static __always_inline void mm_cid_updat __this_cpu_write(mm->mm_cid.pcpu->cid, cid); } =20 -static __always_inline void mm_cid_from_cpu(struct task_struct *t, unsigne= d int cpu_cid) +static __always_inline void mm_cid_from_cpu(struct task_struct *t, unsigne= d int cpu_cid, + unsigned int mode) { unsigned int max_cids, tcid =3D t->mm_cid.cid; struct mm_struct *mm =3D t->mm; @@ -3842,15 +3843,16 @@ static __always_inline void mm_cid_from_ if (!cid_on_cpu(cpu_cid)) cpu_cid =3D cid_to_cpu_cid(mm_get_cid(mm)); =20 - /* Set the transition mode flag if required */ - if (READ_ONCE(mm->mm_cid.transit)) + /* Handle the transition mode flag if required */ + if (mode & MM_CID_TRANSIT) cpu_cid =3D cpu_cid_to_cid(cpu_cid) | MM_CID_TRANSIT; } mm_cid_update_pcpu_cid(mm, cpu_cid); mm_cid_update_task_cid(t, cpu_cid); } =20 -static __always_inline void mm_cid_from_task(struct task_struct *t, unsign= ed int cpu_cid) +static __always_inline void mm_cid_from_task(struct task_struct *t, unsign= ed int cpu_cid, + unsigned int mode) { unsigned int max_cids, tcid =3D t->mm_cid.cid; struct mm_struct *mm =3D t->mm; @@ -3876,7 +3878,7 @@ static __always_inline void mm_cid_from_ if (!cid_on_task(tcid)) tcid =3D mm_get_cid(mm); /* Set the transition mode flag if required */ - tcid |=3D READ_ONCE(mm->mm_cid.transit); + tcid |=3D mode & MM_CID_TRANSIT; } mm_cid_update_pcpu_cid(mm, tcid); mm_cid_update_task_cid(t, tcid); @@ -3885,16 +3887,17 @@ static __always_inline void mm_cid_from_ static __always_inline void mm_cid_schedin(struct task_struct *next) { struct mm_struct *mm =3D next->mm; - unsigned int cpu_cid; + unsigned int cpu_cid, mode; =20 if (!next->mm_cid.active) return; =20 cpu_cid =3D __this_cpu_read(mm->mm_cid.pcpu->cid); - if (likely(!READ_ONCE(mm->mm_cid.percpu))) - mm_cid_from_task(next, cpu_cid); + mode =3D READ_ONCE(mm->mm_cid.mode); + if (likely(!cid_on_cpu(mode))) + mm_cid_from_task(next, cpu_cid, mode); else - mm_cid_from_cpu(next, cpu_cid); + mm_cid_from_cpu(next, cpu_cid, mode); } =20 static __always_inline void mm_cid_schedout(struct task_struct *prev) From nobody Mon Feb 9 04:29:28 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E959933D6D8 for ; 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dmarc=fail (p=quarantine dis=none) header.from=kernel.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Date: Thu, 29 Jan 2026 22:20:52 +0100 Message-ID: <20260129211557.815063341@kernel.org> From: Thomas Gleixner To: LKML Cc: Ihor Solodrai , Shrikanth Hegde , Peter Zijlstra , Mathieu Desnoyers , Michael Jeanson Subject: [patch 3/4] sched/mmcid: Drop per CPU CID immediately when switching to per task mode References: <20260129210219.452851594@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When a exiting task initiates the switch from per CPU back to per task mode, it has already dropped it's CID and marked itself inactive. But a leftover from an earlier iteration of the rework then reassigns the per CPU CID to the exiting task with the transition bit set. That's wrong as the task is already marked CID inactive, which means it is inconsistent state. It's harmless because the CID is marked in transit and therefore dropped back into the pool when the exiting task schedules out either through preemption or the final schedule(). Simply drop the per CPU CID when the exiting task triggered the transition. Fixes: fbd0e71dc370 ("sched/mmcid: Provide CID ownership mode fixup functio= ns") Signed-off-by: Thomas Gleixner Reviewed-by: Mathieu Desnoyers --- kernel/sched/core.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -10713,8 +10713,14 @@ void sched_mm_cid_exit(struct task_struc scoped_guard(raw_spinlock_irq, &mm->mm_cid.lock) { if (!__sched_mm_cid_exit(t)) return; - /* Mode change required. Transfer currents CID */ - mm_cid_transit_to_task(current, this_cpu_ptr(mm->mm_cid.pcpu)); + /* + * Mode change. The task has the CID unset + * already. The CPU CID is still valid and + * does not have MM_CID_TRANSIT set as the + * mode change has just taken effect under + * mm::mm_cid::lock. Drop it. + */ + mm_drop_cid_on_cpu(mm, this_cpu_ptr(mm->mm_cid.pcpu)); } mm_cid_fixup_cpus_to_tasks(mm); return; From nobody Mon Feb 9 04:29:28 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7594832E723 for ; Thu, 29 Jan 2026 21:20:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769721658; cv=none; b=td61hclQSBD48Guh1j0mA8ON8dHKevWrselexm1BguhuzTIapPixSCAmdHeUubN5pHVYMOrd32eZD0m0uOBj+UEVthriUqi90quDM0iyQypfxk8zJ+SBcBaSQHyH89KQTvW9rnETIC0Lv2U7vQ/xWNoj7iJ76MMerm44IkmeX8I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769721658; c=relaxed/simple; bh=/X3LYzgslZlxMvzSRABPEAr+dyyXe4izLfc9wqN4tWw=; h=Date:Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type; b=CvPXJarRb4KecCqYN86kfen7T5eeZf7tL1l6HDOc8qyZu3sf3qldRox9xCnfwt14u6kvvUd+Jp1Yews/k0PxvHAfalzIR/vXyrmNrKSv5105RgMfdL3wu6Vhvq8g1l0G2/iPdaH8WlrlMeyJHb2MaWGvxV4XcCfZ6vZgKLKlPEM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=kernel.org; spf=pass smtp.mailfrom=linutronix.de; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=kernel.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Date: Thu, 29 Jan 2026 22:20:54 +0100 Message-ID: <20260129211557.882759840@kernel.org> From: Thomas Gleixner To: LKML Cc: Ihor Solodrai , Shrikanth Hegde , Peter Zijlstra , Mathieu Desnoyers , Michael Jeanson Subject: [patch 4/4] sched/mmcid: Optimize transitional CIDs when scheduling out References: <20260129210219.452851594@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" During the investigation of the various transition mode issues instrumentation revealed that the amount of bitmap operations can be significantly reduced when a task with a transitional CID schedules out after the fixup function completed and disabled the transition mode. At that point the mode is stable and therefore it is not required to drop the transitional CID back into the pool. As the fixup is complete the potential exhaustion of the CID pool is not longer possible, so the CID can be transferred to the scheduling out task or to the CPU depending on the current ownership mode. This is now possible because mm_cid::mode contains both the ownership state and the transition bit so the racy snapshot is valid under all circumstances because a subsequent modification of the mode is serialized by the corresponding runqueue lock. Assigning the ownership right there not only spares the bitmap access for dropping the CID it also avoids it when the task is scheduled back in as it directly hits the fast path in both modes when the CID is within the optimal range. If it's outside the range the next schedule in will need to converge so dropping it right away is sensible. In the good case this also allows to go into the fast path on the next schedule in operation. With a thread pool benchmark which is configured to cross the mode switch boundaries frequently this reduces the number of bitmap operations by about 30% and increases the fastpath utilization in the low single digit percentage range. Signed-off-by: Thomas Gleixner --- kernel/sched/sched.h | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -3902,12 +3902,32 @@ static __always_inline void mm_cid_sched =20 static __always_inline void mm_cid_schedout(struct task_struct *prev) { + struct mm_struct *mm =3D prev->mm; + unsigned int mode, cid; + /* During mode transitions CIDs are temporary and need to be dropped */ if (likely(!cid_in_transit(prev->mm_cid.cid))) return; =20 - mm_drop_cid(prev->mm, cid_from_transit_cid(prev->mm_cid.cid)); - prev->mm_cid.cid =3D MM_CID_UNSET; + mode =3D READ_ONCE(mm->mm_cid.mode); + cid =3D cid_from_transit_cid(prev->mm_cid.cid); + + /* + * If transition mode is done, transfer ownership when the CID is + * within the convergion range. Otherwise the next schedule in will + * have to allocate or converge + */ + if (!cid_in_transit(mode) && cid < READ_ONCE(mm->mm_cid.max_cids)) { + if (cid_on_cpu(mode)) + cid =3D cid_to_cpu_cid(cid); + + /* Update both so that the next schedule in goes into the fast path */ + mm_cid_update_pcpu_cid(mm, cid); + prev->mm_cid.cid =3D cid; + } else { + mm_drop_cid(mm, cid); + prev->mm_cid.cid =3D MM_CID_UNSET; + } } =20 static inline void mm_cid_switch_to(struct task_struct *prev, struct task_= struct *next)