From nobody Sat Feb 7 13:45:57 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F05F2E7F39; Thu, 29 Jan 2026 18:18:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769710739; cv=none; b=X2+mCF6L2dvo+AF7A91BRjN91TrMdCsyYkDf9wr41QMo0lD2FBMBPyJ0pFZoJ2lEXwFSXA6VVT0qMCL4fxawI8z1SdXLfARcDmRWJQL9sBz+ILzTpp/ywO2haeMU2hUzlFmMJgB6IVykWqoJRIDj71coXS4BNSXbnuwVe4QDzWM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769710739; c=relaxed/simple; bh=QGA7s2M35n/1FOK4su0sUXCzqna1KL1Zl+xDOLqoMB4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=p06jgOuN2OrvzHcBzmoWHaPbEsHqNHoXTwR+mkDoJGMkHsMNEmq7dUKQNR1K/vKZ8fIperf/H0UklNIjL3ILjdH+wNjfldGHVuQL8ghwTQAcFo1AYAFYb+/4XN5jnDQQ2RhYP0NxUCtOfdg99Q4sINlAblgHGoehQByC+hSVvbY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NTy11+8b; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NTy11+8b" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769710738; x=1801246738; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QGA7s2M35n/1FOK4su0sUXCzqna1KL1Zl+xDOLqoMB4=; b=NTy11+8bHTcsFEN6WNDyhHbSLE29tx7KJfYPtDaoPA/O/Ume8cbXv9zf vloT110BhUl93NFS/WaS34CKInLusHavlh9v8NOzRbVjL+0iMp+pLHlEX SSNiOhegQE9QcZzk8YUDtA5RqenLjN6zA9vTL3cMCwfwzCkJx/QmNYLuR vr6ceIfHWFgK0TzwUEQI+c2c+zCN6bPyHY4AtpSx9NjdcvGP/obM/Mj8U lU3qejKWD5J67O9ZnYLVry+VfNlyQDDS6v2Kq1f7NBAfdTkJ0lBwScYGD Zo7h5vVO+ywXz5y6efTxs9RiWZcSQN/lqG53cqkYzDSdPh2e1TqhSkmzr Q==; X-CSE-ConnectionGUID: ErQhjZ9uTWOVbK9mWAQCWA== X-CSE-MsgGUID: gRgpUM4sRrGD9Uv7qBhsnA== X-IronPort-AV: E=McAfee;i="6800,10657,11686"; a="70158275" X-IronPort-AV: E=Sophos;i="6.21,261,1763452800"; d="scan'208";a="70158275" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 10:18:57 -0800 X-CSE-ConnectionGUID: zEFqbPbfRa+kk3Nk8tUvvA== X-CSE-MsgGUID: wf2kJr/yTf+2bXraxa8fpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,261,1763452800"; d="scan'208";a="208255266" Received: from egrumbac-mobl6.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.96]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 10:18:55 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 1/7] i3c: mipi-i3c-hci-pci: Set d3hot_delay to 0 for Intel controllers Date: Thu, 29 Jan 2026 20:18:35 +0200 Message-ID: <20260129181841.130864-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260129181841.130864-1-adrian.hunter@intel.com> References: <20260129181841.130864-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set d3hot_delay to 0 for Intel controllers because a delay is not needed. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i= 3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c index 0f05a15c14c7..bc83caad4197 100644 --- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c +++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c @@ -164,6 +164,7 @@ static int intel_i3c_init(struct mipi_i3c_hci_pci *hci) dma_set_mask_and_coherent(&hci->pci->dev, DMA_BIT_MASK(64)); =20 hci->pci->d3cold_delay =3D 0; + hci->pci->d3hot_delay =3D 0; =20 hci->private =3D host; host->priv =3D priv; --=20 2.51.0 From nobody Sat Feb 7 13:45:57 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A64D2F6181; Thu, 29 Jan 2026 18:18:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769710740; cv=none; b=CLkt95rcp736NK+dhU+7wmNNuBWk2novrECROv5tzkxbOQUJhwiv93PwUrverEILZGFwuYnJPRyBScjhxL0lC2AHU8Gttfl1tvKt6v+UtdoQkwL31d4WExMklZSTSPSVxyLNg3Ny+CPzMFVsHIF0jLUDqmXo7UIjP7LfJWk2S34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769710740; c=relaxed/simple; bh=CLXURq7tlSrIb+QZ2FESlRHc+yoIVSsLvnSsvxf0JUY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GgYB+j3FiybtmFB5DjTNuAnRlqS59Ca9DdAEE2w9tox4tPnaOUn7pQq8XH7A0DU4b1XYkMU80QDklqeKEIEjXaAr6u4IcbKymnlEV8dUMhJc6v02CcmjaPHbpT8YoQcBhBRKPVieaghwV8vqicm2aA16CsOLe+R/F0bxbbf771g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Oi8myQ9y; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Oi8myQ9y" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769710739; x=1801246739; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CLXURq7tlSrIb+QZ2FESlRHc+yoIVSsLvnSsvxf0JUY=; b=Oi8myQ9y8b8vRAsVGvC7JX+h+QI9tuXS40afMFRqCIgEXG4ma5NSfR6p 4jXkQCBQT4QDOm3dYYfW3B52Jj0rVAW7VNSo46LKDySy/fbjgo5yqsrGA HCpLeZcbrf3pJMXSykYc79T52+0u+xodqn8Hvxuk9gaiIzRWI+jAwl6Oe zzRjjxQSWZ0B7w8H1yQrw1Yx37CUgLatw3Y1jctoYQjlzXBJvz/BnPHcC bW2CuEFO5KQyvmB7MNeSkox1wCdb5XokRVDagyjI+WbvHaIw0AaEyJSar QvmqANLjpx4ulJ+SHZE5aFKsRBAWEwOvpBqOAQqnSMgXcciFV9sBI30b7 g==; X-CSE-ConnectionGUID: LamOqH9CQCSnulDkpSzNkA== X-CSE-MsgGUID: KttSY8+nRjOWLufuu2ddNQ== X-IronPort-AV: E=McAfee;i="6800,10657,11686"; a="70158280" X-IronPort-AV: E=Sophos;i="6.21,261,1763452800"; d="scan'208";a="70158280" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 10:18:59 -0800 X-CSE-ConnectionGUID: Xsn2QIhpSoukT7gB2j1Qjg== X-CSE-MsgGUID: 1TcGD0alSmeebOPI8M6rng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,261,1763452800"; d="scan'208";a="208255287" Received: from egrumbac-mobl6.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.96]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 10:18:57 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 2/7] i3c: master: Allow controller drivers to select runtime PM device Date: Thu, 29 Jan 2026 20:18:36 +0200 Message-ID: <20260129181841.130864-3-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260129181841.130864-1-adrian.hunter@intel.com> References: <20260129181841.130864-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some I3C controller drivers need runtime PM to operate on a device other than the parent device. To support that, add an rpm_dev pointer to struct i3c_master_controller so drivers can specify which device should be used for runtime power management. If a driver does not set rpm_dev explicitly, default to using the parent device to maintain existing behaviour. Update the runtime PM helpers to use rpm_dev instead of dev.parent. Signed-off-by: Adrian Hunter --- drivers/i3c/master.c | 9 ++++++--- include/linux/i3c/master.h | 2 ++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 49fb6e30a68e..bcc493dc9d04 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -108,10 +108,10 @@ static struct i3c_master_controller *dev_to_i3cmaster= (struct device *dev) =20 static int __must_check i3c_master_rpm_get(struct i3c_master_controller *m= aster) { - int ret =3D master->rpm_allowed ? pm_runtime_resume_and_get(master->dev.p= arent) : 0; + int ret =3D master->rpm_allowed ? pm_runtime_resume_and_get(master->rpm_d= ev) : 0; =20 if (ret < 0) { - dev_err(master->dev.parent, "runtime resume failed, error %d\n", ret); + dev_err(master->rpm_dev, "runtime resume failed, error %d\n", ret); return ret; } return 0; @@ -120,7 +120,7 @@ static int __must_check i3c_master_rpm_get(struct i3c_m= aster_controller *master) static void i3c_master_rpm_put(struct i3c_master_controller *master) { if (master->rpm_allowed) - pm_runtime_put_autosuspend(master->dev.parent); + pm_runtime_put_autosuspend(master->rpm_dev); } =20 int i3c_bus_rpm_get(struct i3c_bus *bus) @@ -2975,6 +2975,9 @@ int i3c_master_register(struct i3c_master_controller = *master, INIT_LIST_HEAD(&master->boardinfo.i2c); INIT_LIST_HEAD(&master->boardinfo.i3c); =20 + if (!master->rpm_dev) + master->rpm_dev =3D parent; + ret =3D i3c_master_rpm_get(master); if (ret) return ret; diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h index af2bb48363ba..4be67a902dd8 100644 --- a/include/linux/i3c/master.h +++ b/include/linux/i3c/master.h @@ -501,6 +501,7 @@ struct i3c_master_controller_ops { * registered to the I2C subsystem to be as transparent as possible to * existing I2C drivers * @ops: master operations. See &struct i3c_master_controller_ops + * @rpm_dev: Runtime PM device * @secondary: true if the master is a secondary master * @init_done: true when the bus initialization is done * @hotjoin: true if the master support hotjoin @@ -526,6 +527,7 @@ struct i3c_master_controller { struct i3c_dev_desc *this; struct i2c_adapter i2c; const struct i3c_master_controller_ops *ops; + struct device *rpm_dev; unsigned int secondary : 1; unsigned int init_done : 1; unsigned int hotjoin: 1; --=20 2.51.0 From nobody Sat Feb 7 13:45:57 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A5462F690D; Thu, 29 Jan 2026 18:19:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769710743; cv=none; b=iUn1i9MD0d/BH6NzAcS8MFjzQChq/AqFUo5puV/8KZknmstCW/tMJZqk41W9YRkOH4/o2bgBmDu8RkTaVjJ20njGBxSzFAk4oZIwcz3T3+CHpLqvxLKX0/wofHYPhVe3OBFeY9XzhiO8NtgfIaudElAYwoPXzgmaDOzYLi9tRHc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769710743; c=relaxed/simple; bh=D+WHOGKFshiFkAf45pAICzZWD+m0dKpyCxa51cP0wQQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pcgizi0aAZ2l5nAzdPouliX450CsOu1M6DMAzT/eu083cQEh/YvMH+z0RsgdC68BSQYbpPj69yE1CToZtY+tDkzhzuJYoybxmsun8utl2gI33b+hJteDrUnalo6ariLu4TzV/To4W27y4i+eSJgg/H+PhucjVrwFtm8VKypKe3M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=aPqCLxVV; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="aPqCLxVV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769710741; x=1801246741; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D+WHOGKFshiFkAf45pAICzZWD+m0dKpyCxa51cP0wQQ=; b=aPqCLxVV61ETKAaFpYqeApOUoVK+WFA7GeBqur7UQo0vXMVkkUw3sJjI RscCeyBnFzrc3kbEigsaeQ3hNGMhZeRJEL6uAQm8uzor5fKrVWmrfMODz hmyPflB7oNtzrEm99E4/Ql/IUuOnuTwSwDpTmmnMHJn/xhUcDfWHq0+v5 /f1Ib0HohUCucdxbq+FLO2XNlKMRumKbJdNIeEgzNa54CKMWOIiN+gev0 EvfotCf8+7ArkgYrOtW85TQAAJlumTDoLwDQmP1a+T236ye79EZzDrfR0 396gIoMuzUQZygGOEhXq/w8RO+HM0HDe0L56BcJw+NQWGxgJuPLBlhv8V A==; X-CSE-ConnectionGUID: ebjk5kHYQoCyijjLq/k+Xg== X-CSE-MsgGUID: dgUvRErtTDu4QFB9YknzLA== X-IronPort-AV: E=McAfee;i="6800,10657,11686"; a="70158284" X-IronPort-AV: E=Sophos;i="6.21,261,1763452800"; d="scan'208";a="70158284" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 10:19:01 -0800 X-CSE-ConnectionGUID: EvvHSjuSTnK+KcRcB9zE4g== X-CSE-MsgGUID: r5UZsRcyT7KSWmAKjVuHtA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,261,1763452800"; d="scan'208";a="208255292" Received: from egrumbac-mobl6.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.96]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 10:18:59 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 3/7] i3c: master: Mark last_busy on IBI when runtime PM is allowed Date: Thu, 29 Jan 2026 20:18:37 +0200 Message-ID: <20260129181841.130864-4-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260129181841.130864-1-adrian.hunter@intel.com> References: <20260129181841.130864-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable When an IBI can be received after the controller is pm_runtime_put_autosuspend()'ed, the interrupt may occur just before the device is auto=E2=80=91suspended. In such cases, the runtime PM core may n= ot see any recent activity and may suspend the device earlier than intended. Mark the controller as last busy whenever an IBI is queued (when rpm_ibi_allowed is set) so that the auto-suspend delay correctly reflects recent bus activity and avoids premature suspension. Signed-off-by: Adrian Hunter --- drivers/i3c/master.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index bcc493dc9d04..dcc07ebc50a2 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -2721,9 +2721,14 @@ static void i3c_master_unregister_i3c_devs(struct i3= c_master_controller *master) */ void i3c_master_queue_ibi(struct i3c_dev_desc *dev, struct i3c_ibi_slot *s= lot) { + struct i3c_master_controller *master =3D i3c_dev_get_master(dev); + if (!dev->ibi || !slot) return; =20 + if (master->rpm_ibi_allowed) + pm_runtime_mark_last_busy(master->rpm_dev); + atomic_inc(&dev->ibi->pending_ibis); queue_work(dev->ibi->wq, &slot->work); } --=20 2.51.0 From nobody Sat Feb 7 13:45:57 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 517B42F693D; Thu, 29 Jan 2026 18:19:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769710745; cv=none; b=BC87u5aCz3oO7dcm41Z1ammvrSkhy2Yy5Bw5Q+MRhgb6LnGTH0HcpwbgJENx+dDkrYd6tBRlOAJVH+JcCHBuVZkXoRzqsK1yGOHO5w/fzyoZmiUod2LW0+WnXdgbKVQPTACR6wtfI8Aolk9ujd8RLB4QJOshNkssZ46/IiNw9UE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769710745; c=relaxed/simple; bh=Vth7ZQ3l7iGCOJhyGFQCxUbjMiSgkkexgfCMAYp6YQs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=frB50oKMMtUilk43RfZ00Sv3LnvuiTVxMWHizNgBfgqIBBlHCoT0v/mp1X46KLUxGXi9KhDQP0WXKqL0lNX0tp3wsjWrCYfi7xa5davK9wMg4GwI5a+WbIe4Os2Feculwh8yrfKsb8DmMzyqRltOQWoNs7QAcaaNsm2dM8Jn/ak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Y4Lohu0z; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Y4Lohu0z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1769710743; x=1801246743; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Vth7ZQ3l7iGCOJhyGFQCxUbjMiSgkkexgfCMAYp6YQs=; b=Y4Lohu0zPWNnBDHNuDjx6CDWWzwYPMj36ReowZIihWqZnnhfckajz0Mt pGlm1iFU9qCJNPSeC39azGBMr/S2WZu55zhaAQbJfsQIAJB2xtK3qChZq kVNk9PDEedtmi3EWB383whrYBNpq4DeZ8/VHK7XEqtuYcJ07lXtngr+88 atYV9U2H1HiOcf1vBf3Gt9vBvjzgOJ9c/sIxUP7IzoiN1E69zTl54mT7a Z46acgTtf4n/mXxIHmvOjrWNxkaOjTyyR4kTeLY5B4lMNpdx/V/8/eQ9g DRL0VxsZpymBw1hsIsJu7Y9zqF3IuA6QTcxXAwYpBN7SUD5ZA+bkQ4B7a w==; X-CSE-ConnectionGUID: 80BBKQ8QTL6fWjb1chAilw== X-CSE-MsgGUID: 34zcYWm1TkifsGurYztbqQ== X-IronPort-AV: E=McAfee;i="6800,10657,11686"; a="70158289" X-IronPort-AV: E=Sophos;i="6.21,261,1763452800"; d="scan'208";a="70158289" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 10:19:03 -0800 X-CSE-ConnectionGUID: R7wiPTGETneIcE3M7sRjbg== X-CSE-MsgGUID: V3hjQdqDQue9OnI1CA7roQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,261,1763452800"; d="scan'208";a="208255299" Received: from egrumbac-mobl6.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.96]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 10:19:01 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 4/7] i3c: mipi-i3c-hci: Add quirk to allow IBI while runtime suspended Date: Thu, 29 Jan 2026 20:18:38 +0200 Message-ID: <20260129181841.130864-5-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260129181841.130864-1-adrian.hunter@intel.com> References: <20260129181841.130864-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some I3C controllers can be automatically runtime-resumed in order to handle in-band interrupts (IBIs), meaning that runtime suspend does not need to be blocked when IBIs are enabled. For example, a PCI-attached controller in a low-power state may generate a Power Management Event (PME) when the SDA line is pulled low to signal the START condition of an IBI. The PCI subsystem will then runtime-resume the device, allowing the IBI to be received without requiring the controller to remain active. Introduce a new quirk, HCI_QUIRK_RPM_IBI_ALLOWED, so that drivers can opt-in to this capability via driver data. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/core.c | 3 +++ drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index e925584113d1..ec4dbe64c35e 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -959,6 +959,9 @@ static int i3c_hci_probe(struct platform_device *pdev) if (hci->quirks & HCI_QUIRK_RPM_ALLOWED) i3c_hci_rpm_enable(&pdev->dev); =20 + if (hci->quirks & HCI_QUIRK_RPM_IBI_ALLOWED) + hci->master.rpm_ibi_allowed =3D true; + return i3c_master_register(&hci->master, &pdev->dev, &i3c_hci_ops, false); } =20 diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 6035f74212db..819328a85b84 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -146,6 +146,7 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD p= latforms */ #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD= platforms */ #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ +#define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed whil= e runtime suspended */ =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); 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X-CSE-ConnectionGUID: VSH9IuHoTMacdAKI61pEmw== X-CSE-MsgGUID: QhFWryidQe2r5FqNmY/3Vw== X-IronPort-AV: E=McAfee;i="6800,10657,11686"; a="70158297" X-IronPort-AV: E=Sophos;i="6.21,261,1763452800"; d="scan'208";a="70158297" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 10:19:05 -0800 X-CSE-ConnectionGUID: lCsLGKXRSg+yvE8TH/VaqA== X-CSE-MsgGUID: L9t24EcPR8mNFQ934HCgCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,261,1763452800"; d="scan'208";a="208255305" Received: from egrumbac-mobl6.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.96]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 10:19:03 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 5/7] i3c: mipi-i3c-hci: Allow parent to manage runtime PM Date: Thu, 29 Jan 2026 20:18:39 +0200 Message-ID: <20260129181841.130864-6-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260129181841.130864-1-adrian.hunter@intel.com> References: <20260129181841.130864-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Some platforms implement the MIPI I3C HCI Multi-Bus Instance capability, where a single parent device hosts multiple I3C controller instances. In such designs, the parent - not the individual child instances - may need to coordinate runtime PM so that all controllers enter low-power states together, and all runtime suspend callbacks are invoked in a controlled and synchronized manner. For example, if the parent enables IBI-wakeup when transitioning into a low-power state, every bus instance must remain able to receive IBIs up until that point. This requires deferring the individual controllers=E2=80= =99 runtime suspend callbacks (which disable bus activity) until the parent decides it is safe for all instances to suspend together. To support this usage model: * Export the controller's runtime PM suspend/resume callbacks so that the parent can invoke them directly. * Add a new quirk, HCI_QUIRK_RPM_PARENT_MANAGED, which designates the parent device as the controller=E2=80=99s runtime PM device (rpm_dev). = When used without HCI_QUIRK_RPM_ALLOWED, this also prevents the child instance=E2=80=99s system-suspend callbacks from using pm_runtime_force_suspend()/pm_runtime_force_resume(), since runtime PM is managed entirely by the parent. * Move DEFAULT_AUTOSUSPEND_DELAY_MS into the header so it can be shared by parent-managed PM implementations. The new quirk allows platforms with multi-bus parent-managed PM infrastructure to correctly coordinate runtime PM across all I3C HCI instances. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/core.c | 25 ++++++++++++++++--------- drivers/i3c/master/mipi-i3c-hci/hci.h | 6 ++++++ 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index ec4dbe64c35e..cb974b0f9e17 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -733,7 +733,7 @@ static int i3c_hci_reset_and_init(struct i3c_hci *hci) return 0; } =20 -static int i3c_hci_runtime_suspend(struct device *dev) +int i3c_hci_runtime_suspend(struct device *dev) { struct i3c_hci *hci =3D dev_get_drvdata(dev); int ret; @@ -746,8 +746,9 @@ static int i3c_hci_runtime_suspend(struct device *dev) =20 return 0; } +EXPORT_SYMBOL_GPL(i3c_hci_runtime_suspend); =20 -static int i3c_hci_runtime_resume(struct device *dev) +int i3c_hci_runtime_resume(struct device *dev) { struct i3c_hci *hci =3D dev_get_drvdata(dev); int ret; @@ -768,6 +769,7 @@ static int i3c_hci_runtime_resume(struct device *dev) =20 return 0; } +EXPORT_SYMBOL_GPL(i3c_hci_runtime_resume); =20 static int i3c_hci_suspend(struct device *dev) { @@ -784,12 +786,14 @@ static int i3c_hci_resume_common(struct device *dev, = bool rstdaa) struct i3c_hci *hci =3D dev_get_drvdata(dev); int ret; =20 - if (!(hci->quirks & HCI_QUIRK_RPM_ALLOWED)) - return 0; + if (!(hci->quirks & HCI_QUIRK_RPM_PARENT_MANAGED)) { + if (!(hci->quirks & HCI_QUIRK_RPM_ALLOWED)) + return 0; =20 - ret =3D pm_runtime_force_resume(dev); - if (ret) - return ret; + ret =3D pm_runtime_force_resume(dev); + if (ret) + return ret; + } =20 ret =3D i3c_master_do_daa_ext(&hci->master, rstdaa); if (ret) @@ -812,8 +816,6 @@ static int i3c_hci_restore(struct device *dev) return i3c_hci_resume_common(dev, true); } =20 -#define DEFAULT_AUTOSUSPEND_DELAY_MS 1000 - static void i3c_hci_rpm_enable(struct device *dev) { struct i3c_hci *hci =3D dev_get_drvdata(dev); @@ -962,6 +964,11 @@ static int i3c_hci_probe(struct platform_device *pdev) if (hci->quirks & HCI_QUIRK_RPM_IBI_ALLOWED) hci->master.rpm_ibi_allowed =3D true; =20 + if (hci->quirks & HCI_QUIRK_RPM_PARENT_MANAGED) { + hci->master.rpm_dev =3D pdev->dev.parent; + hci->master.rpm_allowed =3D true; + } + return i3c_master_register(&hci->master, &pdev->dev, &i3c_hci_ops, false); } =20 diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 819328a85b84..d0e7ad58ac15 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -147,6 +147,7 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD= platforms */ #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ #define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed whil= e runtime suspended */ +#define HCI_QUIRK_RPM_PARENT_MANAGED BIT(7) /* Runtime PM managed by pare= nt device */ =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); @@ -156,4 +157,9 @@ void amd_set_od_pp_timing(struct i3c_hci *hci); void amd_set_resp_buf_thld(struct i3c_hci *hci); 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d="scan'208";a="208255311" Received: from egrumbac-mobl6.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.96]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 10:19:05 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 6/7] i3c: mipi-i3c-hci-pci: Add optional ability to manage child runtime PM Date: Thu, 29 Jan 2026 20:18:40 +0200 Message-ID: <20260129181841.130864-7-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260129181841.130864-1-adrian.hunter@intel.com> References: <20260129181841.130864-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Some platforms implement the MIPI I3C HCI Multi-Bus Instance capability, where a single parent device hosts multiple I3C controller instances. In such designs, the parent - not the individual child instances - may need to coordinate runtime PM so that all controllers enter low-power states together, and all runtime suspend callbacks are invoked in a controlled and synchronized manner. For example, if the parent enables IBI-wakeup when transitioning into a low-power state, every bus instance must remain able to receive IBIs up until that point. This requires deferring the individual controllers=E2=80= =99 runtime suspend callbacks (which disable bus activity) until the parent decides it is safe for all instances to suspend together. To support this usage model: * Add runtime PM and system PM callbacks in the PCI driver to invoke the mipi-i3c-hci driver=E2=80=99s runtime PM callbacks for each instanc= e. * Introduce a driver-data flag, control_instance_pm, which opts into the new parent-managed PM behaviour. * Ensure the callbacks are only used when the corresponding instance is operational at suspend time. This is reliable because the operational state cannot change while the parent device is undergoing a PM transition, and PCI always performs a runtime resume before system suspend on current configurations, so that suspend and resume alternate irrespective of whether it is runtime or system PM. By that means, parent-managed runtime PM coordination for multi-instance MIPI I3C HCI PCI devices is provided without altering existing behaviour on platforms that do not require it. Signed-off-by: Adrian Hunter --- .../master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 154 +++++++++++++++++- 1 file changed, 150 insertions(+), 4 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i= 3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c index bc83caad4197..f7f776300a0f 100644 --- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c +++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -20,16 +21,24 @@ #include #include =20 +#include "hci.h" + /* * There can up to 15 instances, but implementations have at most 2 at this * time. */ #define INST_MAX 2 =20 +struct mipi_i3c_hci_pci_instance { + struct device *dev; + bool operational; +}; + struct mipi_i3c_hci_pci { struct pci_dev *pci; void __iomem *base; const struct mipi_i3c_hci_pci_info *info; + struct mipi_i3c_hci_pci_instance instance[INST_MAX]; void *private; }; =20 @@ -40,6 +49,7 @@ struct mipi_i3c_hci_pci_info { int id[INST_MAX]; u32 instance_offset[INST_MAX]; int instance_count; + bool control_instance_pm; }; =20 #define INTEL_PRIV_OFFSET 0x2b0 @@ -210,14 +220,148 @@ static const struct mipi_i3c_hci_pci_info intel_si_2= _info =3D { .instance_count =3D 1, }; =20 -static void mipi_i3c_hci_pci_rpm_allow(struct device *dev) +static int mipi_i3c_hci_pci_find_instance(struct mipi_i3c_hci_pci *hci, st= ruct device *dev) +{ + for (int i =3D 0; i < INST_MAX; i++) { + if (!hci->instance[i].dev) + hci->instance[i].dev =3D dev; + if (hci->instance[i].dev =3D=3D dev) + return i; + } + + return -1; +} + +#define HC_CONTROL 0x04 +#define HC_CONTROL_BUS_ENABLE BIT(31) + +static bool __mipi_i3c_hci_pci_is_operational(struct device *dev) +{ + const struct mipi_i3c_hci_platform_data *pdata =3D dev->platform_data; + u32 hc_control =3D readl(pdata->base_regs + HC_CONTROL); + + return hc_control & HC_CONTROL_BUS_ENABLE; +} + +static bool mipi_i3c_hci_pci_is_operational(struct device *dev, bool updat= e) +{ + struct mipi_i3c_hci_pci *hci =3D dev_get_drvdata(dev->parent); + int pos =3D mipi_i3c_hci_pci_find_instance(hci, dev); + + if (pos < 0) { + dev_err(dev, "%s: I3C instance not found\n", __func__); + return false; + } + + if (update) + hci->instance[pos].operational =3D __mipi_i3c_hci_pci_is_operational(dev= ); + + return hci->instance[pos].operational; +} + +struct mipi_i3c_hci_pci_pm_data { + struct device *dev[INST_MAX]; + int dev_cnt; +}; + +static bool mipi_i3c_hci_pci_is_mfd(struct device *dev) +{ + return dev_is_platform(dev) && mfd_get_cell(to_platform_device(dev)); +} + +static int mipi_i3c_hci_pci_suspend_instance(struct device *dev, void *dat= a) +{ + struct mipi_i3c_hci_pci_pm_data *pm_data =3D data; + int ret; + + if (!mipi_i3c_hci_pci_is_mfd(dev) || + !mipi_i3c_hci_pci_is_operational(dev, true)) + return 0; + + ret =3D i3c_hci_runtime_suspend(dev); + if (ret) + return ret; + + pm_data->dev[pm_data->dev_cnt++] =3D dev; + + return 0; +} + +static int mipi_i3c_hci_pci_resume_instance(struct device *dev, void *data) { + struct mipi_i3c_hci_pci_pm_data *pm_data =3D data; + int ret; + + if (!mipi_i3c_hci_pci_is_mfd(dev) || + !mipi_i3c_hci_pci_is_operational(dev, false)) + return 0; + + ret =3D i3c_hci_runtime_resume(dev); + if (ret) + return ret; + + pm_data->dev[pm_data->dev_cnt++] =3D dev; + + return 0; +} + +static int mipi_i3c_hci_pci_suspend(struct device *dev) +{ + struct mipi_i3c_hci_pci *hci =3D dev_get_drvdata(dev); + struct mipi_i3c_hci_pci_pm_data pm_data =3D {}; + int ret; + + if (!hci->info->control_instance_pm) + return 0; + + ret =3D device_for_each_child_reverse(dev, &pm_data, mipi_i3c_hci_pci_sus= pend_instance); + if (ret) { + if (ret =3D=3D -EAGAIN || ret =3D=3D -EBUSY) + pm_runtime_mark_last_busy(&hci->pci->dev); + for (int i =3D 0; i < pm_data.dev_cnt; i++) + i3c_hci_runtime_resume(pm_data.dev[i]); + } + + return ret; +} + +static int mipi_i3c_hci_pci_resume(struct device *dev) +{ + struct mipi_i3c_hci_pci *hci =3D dev_get_drvdata(dev); + struct mipi_i3c_hci_pci_pm_data pm_data =3D {}; + int ret; + + if (!hci->info->control_instance_pm) + return 0; + + ret =3D device_for_each_child(dev, &pm_data, mipi_i3c_hci_pci_resume_inst= ance); + if (ret) + for (int i =3D 0; i < pm_data.dev_cnt; i++) + i3c_hci_runtime_suspend(pm_data.dev[i]); + + return ret; +} + +static void mipi_i3c_hci_pci_rpm_allow(struct mipi_i3c_hci_pci *hci) +{ + struct device *dev =3D &hci->pci->dev; + + if (hci->info->control_instance_pm) { + pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY_MS); + pm_runtime_use_autosuspend(dev); + } + pm_runtime_put(dev); pm_runtime_allow(dev); } =20 -static void mipi_i3c_hci_pci_rpm_forbid(struct device *dev) +static void mipi_i3c_hci_pci_rpm_forbid(struct mipi_i3c_hci_pci *hci) { + struct device *dev =3D &hci->pci->dev; + + if (hci->info->control_instance_pm) + pm_runtime_dont_use_autosuspend(dev); + pm_runtime_forbid(dev); pm_runtime_get_sync(dev); } @@ -299,7 +443,7 @@ static int mipi_i3c_hci_pci_probe(struct pci_dev *pci, =20 pci_set_drvdata(pci, hci); =20 - mipi_i3c_hci_pci_rpm_allow(&pci->dev); + mipi_i3c_hci_pci_rpm_allow(hci); =20 return 0; =20 @@ -316,13 +460,15 @@ static void mipi_i3c_hci_pci_remove(struct pci_dev *p= ci) if (hci->info->exit) hci->info->exit(hci); =20 - mipi_i3c_hci_pci_rpm_forbid(&pci->dev); + mipi_i3c_hci_pci_rpm_forbid(hci); =20 mfd_remove_devices(&pci->dev); } =20 /* PM ops must exist for PCI to put a device to a low power state */ static const struct dev_pm_ops mipi_i3c_hci_pci_pm_ops =3D { + RUNTIME_PM_OPS(mipi_i3c_hci_pci_suspend, mipi_i3c_hci_pci_resume, NULL) + SYSTEM_SLEEP_PM_OPS(mipi_i3c_hci_pci_suspend, mipi_i3c_hci_pci_resume) }; =20 static const struct pci_device_id mipi_i3c_hci_pci_devices[] =3D { --=20 2.51.0 From nobody Sat Feb 7 13:45:57 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51183291C10; Thu, 29 Jan 2026 18:19:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; 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29 Jan 2026 10:19:09 -0800 X-CSE-ConnectionGUID: ewWpuvxqT2qGyQ9n6oBChw== X-CSE-MsgGUID: Q9gkBaHZQ92Qr1PSv7/t/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,261,1763452800"; d="scan'208";a="208255315" Received: from egrumbac-mobl6.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.96]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jan 2026 10:19:06 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 7/7] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers Date: Thu, 29 Jan 2026 20:18:41 +0200 Message-ID: <20260129181841.130864-8-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260129181841.130864-1-adrian.hunter@intel.com> References: <20260129181841.130864-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel LPSS I3C controllers can wake from runtime suspend to receive in-band interrupts (IBIs), and they also implement the MIPI I3C HCI Multi-Bus Instance capability. When multiple I3C bus instances share the same PCI wakeup, the PCI parent must coordinate runtime PM so that all instances suspend together and their mipi-i3c-hci runtime suspend callbacks are invoked in a consistent manner. Enable IBI-based wakeup by setting HCI_QUIRK_RPM_IBI_ALLOWED for the intel-lpss-i3c platform device. Replace HCI_QUIRK_RPM_ALLOWED with HCI_QUIRK_RPM_PARENT_MANAGED so that the mipi-i3c-hci core driver expects runtime PM to be controlled by the PCI parent rather than by individual instances. For all Intel HCI PCI configurations, enable the corresponding control_instance_pm flag in the PCI driver. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/core.c | 2 +- drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index cb974b0f9e17..67ae7441ce97 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -992,7 +992,7 @@ static const struct acpi_device_id i3c_hci_acpi_match[]= =3D { MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); =20 static const struct platform_device_id i3c_hci_driver_ids[] =3D { - { .name =3D "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED }, + { .name =3D "intel-lpss-i3c", HCI_QUIRK_RPM_IBI_ALLOWED | HCI_QUIRK_RPM_P= ARENT_MANAGED }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids); diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i= 3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c index f7f776300a0f..2f72cf48e36c 100644 --- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c +++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c @@ -200,6 +200,7 @@ static const struct mipi_i3c_hci_pci_info intel_mi_1_in= fo =3D { .id =3D {0, 1}, .instance_offset =3D {0, 0x400}, .instance_count =3D 2, + .control_instance_pm =3D true, }; =20 static const struct mipi_i3c_hci_pci_info intel_mi_2_info =3D { @@ -209,6 +210,7 @@ static const struct mipi_i3c_hci_pci_info intel_mi_2_in= fo =3D { .id =3D {2, 3}, .instance_offset =3D {0, 0x400}, .instance_count =3D 2, + .control_instance_pm =3D true, }; =20 static const struct mipi_i3c_hci_pci_info intel_si_2_info =3D { @@ -218,6 +220,7 @@ static const struct mipi_i3c_hci_pci_info intel_si_2_in= fo =3D { .id =3D {2}, .instance_offset =3D {0}, .instance_count =3D 1, + .control_instance_pm =3D true, }; =20 static int mipi_i3c_hci_pci_find_instance(struct mipi_i3c_hci_pci *hci, st= ruct device *dev) --=20 2.51.0