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Thu, 29 Jan 2026 17:52:43 +0000 (GMT) Received: from pps.filterd (iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com [127.0.0.1]) by iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com (8.18.1.2/8.18.1.2) with ESMTP id 60TGSbVM020001; Thu, 29 Jan 2026 17:52:42 GMT Received: from pps.reinject (localhost [127.0.0.1]) by iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTPS id 4bvmhhyfdp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 29 Jan 2026 17:52:42 +0000 Received: from iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com (iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 60THllYf012086; Thu, 29 Jan 2026 17:52:41 GMT Received: from lab61.no.oracle.com (lab61.no.oracle.com [10.172.144.82]) by iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTP id 4bvmhhyfc3-2; Thu, 29 Jan 2026 17:52:41 +0000 From: =?UTF-8?q?H=C3=A5kon=20Bugge?= To: Bjorn Helgaas , Niklas Schnelle Cc: Alex Williamson , Johannes Thumshirn , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, =?UTF-8?q?H=C3=A5kon=20Bugge?= Subject: [PATCH v4 1/2] PCI: Initialize RCB from pci_configure_device() Date: Thu, 29 Jan 2026 18:52:32 +0100 Message-ID: <20260129175237.727059-2-haakon.bugge@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20260129175237.727059-1-haakon.bugge@oracle.com> References: <20260129175237.727059-1-haakon.bugge@oracle.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-29_02,2026-01-29_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 bulkscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 spamscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2601150000 definitions=main-2601290126 X-Proofpoint-GUID: lfcHnOq6APBM-SYcBRnPAJlbWewj5dWq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI5MDEyNiBTYWx0ZWRfX3cOWnU7SoH4c UixHRG4q9tnIlhn2aleG9x3gnr50A+2CEcyJf5CtIYdecKWzP3A2wTI6EEeIUtZCd2HlGm9hA1x /85Zh/vvuXQOjgU5JsCX40t/+qHvKdD77teYnUHoL4VPNd6xBgE9x/wF0s9jVDppG64ZHb4Ea8O e2MIfjyQhC9Np6lRArjPJGcWYuXYWo52JW0P3H/gkbF8myF4gG9Jw8xYKcSDStKa8GrdxieHe/O ASR0WzN9c6PjYjHHmWIeV9sdWim6wfCnQbMSGQWPnkbfdA7LrCUOvF5vqls2DSRqecLlg+bEOuv E49TLp6Ns1ivI7215f1Hn/gSezTjI8Kr94I9TWHJqRWAU/aRbu9QU2vEg6Pb2R2n4k1j2BlvRwJ LX/4UfNxbBfbYNeCmOEINoDwa8T1t9fkMOe7GZj6r0nFH2JEqDtejhVYtzjjXsVXrdXwTCEOdeV aBxogBuXY6SasCD1KgsigYJhUTSvGD/+WQW/1HmA= X-Proofpoint-ORIG-GUID: lfcHnOq6APBM-SYcBRnPAJlbWewj5dWq X-Authority-Analysis: v=2.4 cv=a7s9NESF c=1 sm=1 tr=0 ts=697b9e6b b=1 cx=c_pps a=zPCbziy225d3KhSqZt3L1A==:117 a=zPCbziy225d3KhSqZt3L1A==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=M51BFTxLslgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=yPCof4ZbAAAA:8 a=9d3epOvFGE0EtcMk89wA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 cc=ntf awl=host:12103 Commit e42010d8207f ("PCI: Set Read Completion Boundary to 128 iff Root Port supports it (_HPX)") worked around a bogus _HPX type 2 record, which caused program_hpx_type2() to set the RCB in an endpoint even though the Root Port did not have the RCB bit set. e42010d8207f fixed that by setting the RCB in the endpoint only when it was set in the Root Port. In retrospect, program_hpx_type2() is intended for AER-related settings, and the RCB should be configured elsewhere so it doesn't depend on the presence or contents of an _HPX record. Explicitly program the RCB from pci_configure_device() so it matches the Root Port's RCB. The Root Port may not be visible to virtualized guests; in that case, leave RCB alone. Fixes: Commit e42010d8207f ("PCI: Set Read Completion Boundary to 128 iff R= oot Port supports it (_HPX)") Signed-off-by: H=C3=A5kon Bugge --- v3 -> v4: * Use open coding to read the Root Port's RCB * Remove info log v2 -> v3: * Qualified the device types more strictly * s/pcie_root_rcb_set/pcie_read_root_rcb/ and changed signature * Do nothing if the RP's RCB cannot be determined * Reset the device's RCB if not set in the RP --- drivers/pci/probe.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 41183aed8f5d9..460f8af1c3429 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2410,6 +2410,38 @@ static void pci_configure_serr(struct pci_dev *dev) } } =20 +static void pci_configure_rcb(struct pci_dev *dev) +{ + struct pci_dev *rp; + u16 rp_lnkctl; + + /* + * Per PCIe r7.0, sec 7.5.3.7, RCB is only meaningful in Root + * Ports (where it is read-only), Endpoints, and Bridges. It + * may only be set for Endpoints and Bridges if it is set in + * the Root Port. For Endpoints, it is 'RsvdP' for Virtual + * Functions. + */ + if (!pci_is_pcie(dev) || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_UPSTREAM || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_DOWNSTREAM || + pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC || + dev->is_virtfn) + return; + + /* Root Port often not visible to virtualized guests */ + rp =3D pcie_find_root_port(dev); + if (!rp) + return; + + pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &rp_lnkctl); + pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_RCB, + (rp_lnkctl & PCI_EXP_LNKCTL_RCB) ? + PCI_EXP_LNKCTL_RCB : 0); +} + static void pci_configure_device(struct pci_dev *dev) { pci_configure_mps(dev); @@ -2419,6 +2451,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_aspm_l1ss(dev); pci_configure_eetlp_prefix(dev); pci_configure_serr(dev); + pci_configure_rcb(dev); =20 pci_acpi_program_hp_params(dev); } --=20 2.43.5 From nobody Sun Feb 8 09:32:59 2026 Received: from mx0b-00069f02.pphosted.com (mx0b-00069f02.pphosted.com [205.220.177.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A64A6347BA5; Thu, 29 Jan 2026 17:53:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.177.32 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769709184; cv=none; b=gREP9jWUZpXj/kPPbtPCSXNmvwAUd2Op4RE+Qv0RzL64UO7CKNlT3+QK13KL9XMJF2Dwm3TYO7emM5HDkmmzKTYp5/4ioJmsm/FiBVv0IxaAmXbI1LF8ZjlyQ4LyPP13A8yLX1h4Ya/Hwtfryq0XURuYzogkrDYD1XTXD3h/IA0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769709184; c=relaxed/simple; bh=elBqTdEPPPDTgZ9JFYnkaLSnM7vZKoaXZiXofSjZedI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jWfZhxX/Pk5eOitZlRk7hAeq+GfWyKCU3YPa9NzoGwurLPcQcdt+94nUzOmz/Q1AA1r36wo1qq6aUw61oT2A7G7ExMVdCF+s1xmvpmV5Y/5jLAm7ul4eLxNIyoxk/DINDuHhvL0EzKo0SZVmm+huCUEl9jzqgMLOKvgF8wu/nS0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oracle.com; spf=pass smtp.mailfrom=oracle.com; dkim=pass (2048-bit key) header.d=oracle.com header.i=@oracle.com header.b=VsWJ2VKR; arc=none smtp.client-ip=205.220.177.32 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oracle.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oracle.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=oracle.com header.i=@oracle.com header.b="VsWJ2VKR" Received: from pps.filterd (m0333520.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60TDgJNf1278673; Thu, 29 Jan 2026 17:52:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s= corp-2025-04-25; bh=fwb2FMXA5tJtyDq/Zqal//2M2OPh3VodiSxTtoTaLBU=; b= VsWJ2VKRf3OjE1laDkpNztObe9cr/Rf1nFHxMq/69fqkJmT9h89cVc6xH+ISzCUE tqKgZjunorm5a6iWAz1fJqzS60ynjbzKpsPZW2I1mPOKx6JbdK0f4RVvrUtq06GR UpFVjkSPdT1UDPS5b4dja6UoPWAQjMzlaAsOHTdiLY2A875kDcBvgNxLNRdlXTUw 8y7cqgpRGLxNKyjuWOWkmaaNA64ryENQm9+Y/vwXIPkAVEnz9KHmua+nQa+MfaC1 DL6GTQfDTkC1PAulgOJwCUH0mzmp0QaAB+I5IUjx6qsi7VRuRYWtjVKI3/DPWIlW wfskegk/uQbPtTIBwgaBTQ== Received: from iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com (iadpaimrmta01.appoci.oracle.com [130.35.100.223]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 4by2xquu2a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 29 Jan 2026 17:52:46 +0000 (GMT) Received: from pps.filterd (iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com [127.0.0.1]) by iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com (8.18.1.2/8.18.1.2) with ESMTP id 60TH18iq019819; Thu, 29 Jan 2026 17:52:46 GMT Received: from pps.reinject (localhost [127.0.0.1]) by iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTPS id 4bvmhhyfff-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 29 Jan 2026 17:52:46 +0000 Received: from iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com (iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 60THllYh012086; Thu, 29 Jan 2026 17:52:45 GMT Received: from lab61.no.oracle.com (lab61.no.oracle.com [10.172.144.82]) by iadpaimrmta01.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTP id 4bvmhhyfc3-3; Thu, 29 Jan 2026 17:52:45 +0000 From: =?UTF-8?q?H=C3=A5kon=20Bugge?= To: Bjorn Helgaas , Niklas Schnelle , "Rafael J. Wysocki" , Len Brown , Mahesh J Salgaonkar , "Oliver O'Halloran" , Kenji Kaneshige , Greg Kroah-Hartman Cc: Alex Williamson , Johannes Thumshirn , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, =?UTF-8?q?H=C3=A5kon=20Bugge?= , linuxppc-dev@lists.ozlabs.org Subject: [PATCH v4 2/2] PCI/ACPI: Restrict program_hpx_type2() to AER bits Date: Thu, 29 Jan 2026 18:52:33 +0100 Message-ID: <20260129175237.727059-3-haakon.bugge@oracle.com> X-Mailer: git-send-email 2.43.5 In-Reply-To: <20260129175237.727059-1-haakon.bugge@oracle.com> References: <20260129175237.727059-1-haakon.bugge@oracle.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-29_02,2026-01-29_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 adultscore=0 bulkscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 spamscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2601150000 definitions=main-2601290126 X-Proofpoint-GUID: jTAJP50xMzHjPyfLiE3zB8lMmrucg_11 X-Proofpoint-ORIG-GUID: jTAJP50xMzHjPyfLiE3zB8lMmrucg_11 X-Authority-Analysis: v=2.4 cv=UepciaSN c=1 sm=1 tr=0 ts=697b9e6e b=1 cx=c_pps a=zPCbziy225d3KhSqZt3L1A==:117 a=zPCbziy225d3KhSqZt3L1A==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=M51BFTxLslgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=yPCof4ZbAAAA:8 a=SsKr03gcbRYbsVN0MpsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 cc=ntf awl=host:12103 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI5MDEyNiBTYWx0ZWRfX1fAyVDYiClBu z17eEuc0YoENcle/VRABxs8D4vTxTXhqx9QGV4lBx7bdJ+k9IGdDW1sqQTxTG0xJBVJmotgBVZm vsc3IFJXZRha6liP7elgozwPwNiFGbunTG27JDrxDTFeC7OjaFrRkFNwUwOk1sAnkOUey0ozYlR 14FO5bqN2i+0tgpkZDFxVinNeL7EMl0ExdzcIlGGG5R3BYiNpfdRzngGN7GmEMeyLQyKF4DFTtP 4+AM0gQHVt8PEL+mhvMxiJsFhWtjtB4/F5G05rOdvogA/5cKuhj0E6936S+sS1tCTJHR8MzMAyU ACZiM7A/FohAgx/vHSnmVIaHjV6io9htTqU2fj+ThvgvFWWl3zSeEmNZcTgJiCAFA6sAOt0DXnB 542AhQvQVt3lvbck9aGa3VWNq1kQpfKoFduLtr7wEGxr659rndEj90gZ5A5ndywvoOInYNv8kyX 2Yio5A4ROwzWd1cfAi85Z0v9gZsAVZLfyZgmXxZ4= Previously program_hpx_type2() applied PCIe settings unconditionally, which could incorrectly change bits like Extended Tag Field Enable and Enable Relaxed Ordering. When _HPX was added to ACPI r3.0, the intent of the PCIe Setting Record (Type 2) in sec 6.2.7.3 was to configure AER registers when the OS does not own the AER Capability: The PCI Express setting record contains ... [the AER] Uncorrectable Error Mask, Uncorrectable Error Severity, Correctable Error Mask ... to be used when configuring registers in the Advanced Error Reporting Extended Capability Structure ... OSPM [1] will only evaluate _HPX with Setting Record =E2=80=93 Type 2 if OSPM is not controlling the PCI Express Advanced Error Reporting capability. ACPI r3.0b, sec 6.2.7.3, added more AER registers, including registers in the PCIe Capability with AER-related bits, and the restriction that the OS use this only when it owns PCIe native hotplug: ... when configuring PCI Express registers in the Advanced Error Reporting Extended Capability Structure *or PCI Express Capability Structure* ... An OS that has assumed ownership of native hot plug but does not ... have ownership of the AER register set must use ... the Type 2 record to program the AER registers ... However, since the Type 2 record also includes register bits that have functions other than AER, the OS must ignore values ... that are not applicable. Restrict program_hpx_type2() to only the intended purpose: - Apply settings only when OS owns PCIe native hotplug but not AER, - Only touch the AER-related bits (Error Reporting Enables) in Device Control - Don't touch Link Control at all, since nothing there seems AER-related, but log _HPX settings for debugging purposes Note that Read Completion Boundary is now configured elsewhere, since it is unrelated to _HPX. [1] Operating System-directed configuration and Power Management Fixes: 40abb96c51bb ("[PATCH] pciehp: Fix programming hotplug parameters") Signed-off-by: H=C3=A5kon Bugge --- v3 -> v4: * Improved commit message * Corrected info log when _HPX attempts to modify the Link Control register v2 -> v3: * No changes v1 -> v2: * Fixed comment style * Simplified the and/or logic when programming the Device Control register * Fixed the incorrect and brutal warning about Link Control register bits set and changed it to an info message about _HPX attempting to set/reset bits therein. * Removed the RCB programming from program_hpx_type2() * Moved the PCI_EXP_AER_FLAGS definition from drivers/pci/pcie/aer.c to drivers/pci/pci.h --- drivers/pci/pci-acpi.c | 58 +++++++++++++++++------------------------- drivers/pci/pci.h | 3 +++ drivers/pci/pcie/aer.c | 3 --- 3 files changed, 27 insertions(+), 37 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 9369377725fa0..3ffceaa7603c0 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -271,21 +271,6 @@ static acpi_status decode_type1_hpx_record(union acpi_= object *record, return AE_OK; } =20 -static bool pcie_root_rcb_set(struct pci_dev *dev) -{ - struct pci_dev *rp =3D pcie_find_root_port(dev); - u16 lnkctl; - - if (!rp) - return false; - - pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl); - if (lnkctl & PCI_EXP_LNKCTL_RCB) - return true; - - return false; -} - /* _HPX PCI Express Setting Record (Type 2) */ struct hpx_type2 { u32 revision; @@ -311,6 +296,7 @@ static void program_hpx_type2(struct pci_dev *dev, stru= ct hpx_type2 *hpx) { int pos; u32 reg32; + const struct pci_host_bridge *host; =20 if (!hpx) return; @@ -318,6 +304,15 @@ static void program_hpx_type2(struct pci_dev *dev, str= uct hpx_type2 *hpx) if (!pci_is_pcie(dev)) return; =20 + host =3D pci_find_host_bridge(dev->bus); + + /* + * We only do the HP programming if we own the PCIe native + * hotplug and not the AER ownership + */ + if (!host->native_pcie_hotplug || host->native_aer) + return; + if (hpx->revision > 1) { pci_warn(dev, "PCIe settings rev %d not supported\n", hpx->revision); @@ -325,33 +320,28 @@ static void program_hpx_type2(struct pci_dev *dev, st= ruct hpx_type2 *hpx) } =20 /* - * Don't allow _HPX to change MPS or MRRS settings. We manage - * those to make sure they're consistent with the rest of the + * We only allow _HPX to program the AER registers, namely + * PCI_EXP_DEVCTL_CERE, PCI_EXP_DEVCTL_NFERE, + * PCI_EXP_DEVCTL_FERE, and PCI_EXP_DEVCTL_URRE. + * + * The other settings in PCIe DEVCTL are managed by OS in + * order to make sure they're consistent with the rest of the * platform. */ - hpx->pci_exp_devctl_and |=3D PCI_EXP_DEVCTL_PAYLOAD | - PCI_EXP_DEVCTL_READRQ; - hpx->pci_exp_devctl_or &=3D ~(PCI_EXP_DEVCTL_PAYLOAD | - PCI_EXP_DEVCTL_READRQ); + hpx->pci_exp_devctl_and |=3D ~PCI_EXP_AER_FLAGS; + hpx->pci_exp_devctl_or &=3D PCI_EXP_AER_FLAGS; =20 /* Initialize Device Control Register */ pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, ~hpx->pci_exp_devctl_and, hpx->pci_exp_devctl_or); =20 - /* Initialize Link Control Register */ + /* Log if _HPX attempts to modify PCIe Link Control register */ if (pcie_cap_has_lnkctl(dev)) { - - /* - * If the Root Port supports Read Completion Boundary of - * 128, set RCB to 128. Otherwise, clear it. - */ - hpx->pci_exp_lnkctl_and |=3D PCI_EXP_LNKCTL_RCB; - hpx->pci_exp_lnkctl_or &=3D ~PCI_EXP_LNKCTL_RCB; - if (pcie_root_rcb_set(dev)) - hpx->pci_exp_lnkctl_or |=3D PCI_EXP_LNKCTL_RCB; - - pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, - ~hpx->pci_exp_lnkctl_and, hpx->pci_exp_lnkctl_or); + if (hpx->pci_exp_lnkctl_and !=3D 0xffff || + hpx->pci_exp_lnkctl_or !=3D 0) + pci_info(dev, "_HPX attempts Link Control setting (AND %#06x OR %#06x)\= n", + hpx->pci_exp_lnkctl_and, + hpx->pci_exp_lnkctl_or); } =20 /* Find Advanced Error Reporting Enhanced Capability */ diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 0e67014aa0013..f388d4414dd3a 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -88,6 +88,9 @@ struct pcie_tlp_log; #define PCI_BUS_BRIDGE_MEM_WINDOW 1 #define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2 =20 +#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ + PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump; =20 diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index e0bcaa896803c..9472d86cef552 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -239,9 +239,6 @@ void pcie_ecrc_get_policy(char *str) } #endif /* CONFIG_PCIE_ECRC */ =20 -#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ - PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) - int pcie_aer_is_native(struct pci_dev *dev) { struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); --=20 2.43.5