From nobody Sat Feb 7 14:15:41 2026 Received: from out-189.mta0.migadu.com (out-189.mta0.migadu.com [91.218.175.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56D2B318B94 for ; Thu, 29 Jan 2026 17:12:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769706743; cv=none; b=KfVGS0eyUYwuTLAriTDyw3gumv5rxpMIVZ4W7WAL0Aw5HInBwU4iIu/jScT/LYzKmh4QS/cUiI9AdmAfs6bsX3Bb+W/qzODLrQy4LSZfD0pajkv8WABhc9jP3waEZEHZiAvJeJyeYaHaeowsEHxblCt2xQ7raD7pjHcPYx1QtK8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769706743; c=relaxed/simple; bh=OXC1A2rsvEUcoHNtQ2UJItXyNZCYYO98F6lgzlaZNyg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UucEqKaAMzI/a4mZeCba4OSGZMYjhTL+0NwXfZnDAvxT9wtYJBAZbIL1wokhRJql98lpWVxEK+XlHlX/wDjm9Ijyfbliy/MbfnR/iXnTYI5lWRJ/3XS0QenRbstHzpXHr4wtFd4TCJkSvf5RL25poa0nv2tS+cihmhj1+vHtvL0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=iJdBs1Uh; arc=none smtp.client-ip=91.218.175.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="iJdBs1Uh" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1769706739; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EwiQGEV6gt5loAkyx50doAeyjzyj3tZN9e7LGO6xQp0=; b=iJdBs1UhjaO+argsRf0QDssIhZtdEWNURcYRXn0xhaL9XkL+VDwsHZtbGqSiL1p+EKtggj onxMDUpcomBMZX+B6ebYLmkafj2cV2Zmw0rjheGTeHZH/FSWnhUwJ41tNnCI5QgQjeuHNX F6xDARAbSi8lzyaH99pN03c681YaL60= From: Sean Anderson To: Andrew Lunn , Heiner Kallweit , Russell King , netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Jakub Kicinski , Paolo Abeni , "David S . Miller" , Eric Dumazet , Sean Anderson Subject: [PATCH net-next 1/2] net: phy: dp83867: Program TX FIFO for all interfaces Date: Thu, 29 Jan 2026 12:12:04 -0500 Message-Id: <20260129171205.3868605-2-sean.anderson@linux.dev> In-Reply-To: <20260129171205.3868605-1-sean.anderson@linux.dev> References: <20260129171205.3868605-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" All supported interfaces use the TX FIFO register at least some of the time, so there's no point in checking the interface. Retain the check for the RX FIFO level since it is only used by SGMII. Signed-off-by: Sean Anderson --- drivers/net/phy/dp83867.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 5f5de01c41e1..7e16e9299457 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -744,27 +744,24 @@ static int dp83867_config_init(struct phy_device *phy= dev) */ phy_disable_eee(phydev); =20 - if (phy_interface_is_rgmii(phydev) || - phydev->interface =3D=3D PHY_INTERFACE_MODE_SGMII) { - val =3D phy_read(phydev, MII_DP83867_PHYCTRL); - if (val < 0) - return val; + val =3D phy_read(phydev, MII_DP83867_PHYCTRL); + if (val < 0) + return val; =20 - val &=3D ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK; - val |=3D (dp83867->tx_fifo_depth << - DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); + val &=3D ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK; + val |=3D (dp83867->tx_fifo_depth << + DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); =20 - if (phydev->interface =3D=3D PHY_INTERFACE_MODE_SGMII) { - val &=3D ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; - val |=3D (dp83867->rx_fifo_depth << - DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT); - } - - ret =3D phy_write(phydev, MII_DP83867_PHYCTRL, val); - if (ret) - return ret; + if (phydev->interface =3D=3D PHY_INTERFACE_MODE_SGMII) { + val &=3D ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; + val |=3D (dp83867->rx_fifo_depth << + DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT); } =20 + ret =3D phy_write(phydev, MII_DP83867_PHYCTRL, val); + if (ret) + return ret; + if (phy_interface_is_rgmii(phydev)) { val =3D phy_read(phydev, MII_DP83867_PHYCTRL); if (val < 0) --=20 2.35.1.1320.gc452695387.dirty From nobody Sat Feb 7 14:15:41 2026 Received: from out-180.mta0.migadu.com (out-180.mta0.migadu.com [91.218.175.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8951346E6A for ; Thu, 29 Jan 2026 17:12:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769706745; cv=none; b=LxTXPX/V38avyZnAHEhFYaoahSqucrTHkM0FwDkgreLTDab0HAu0rq3EEhbP4XZRdFCV1Mv+36V94XeJ4emqYrskrKODzZUgkJYqlr75XBrUKwKp8VIp8xxXuMj99RZuSb/Yyo7d/H6JMDsGXc9PLH2vh5Vuv/4grLAq/09dJXw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769706745; c=relaxed/simple; bh=qybAs14Tk/B/VbviKoMTmm5OO1vLCm4WD0+AIGzJ1nE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WBPSIQ0I0fDVZNYAdpFnD5tTcLZogorCnJX5V7psCXKhwuxOV4ANpmS0n3uzl8vt5MdjFaJyZgfxbd2kFO3ip+xyNGppW8MzgYZ/+smmr+M7VWuDaPTsaqNxmkunQxqzmItTrsHhMYaVfqseEO90YPratGLcc6roB8MJoF4WOk4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Yc+FPp2q; arc=none smtp.client-ip=91.218.175.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Yc+FPp2q" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1769706741; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=k5pLBA2aCbjk3Rn/mBNnd9QmkEtRl8t+qCyK15ASMvI=; b=Yc+FPp2qPK2GXfX+eDSFcW1/oOGur0LUZzVDYXBkVdqZwwEAb6YWUaN23tjPGHTth/RHSu s46Ks/zNnai4tGnjSoJMnfoeLurYfmwi/hL9cps6Ed6/fdzHvTHCnCREdE4+djQM46qSbe GoLiMrrhiozbzwcL+loCjkvnylkkz/A= From: Sean Anderson To: Andrew Lunn , Heiner Kallweit , Russell King , netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Jakub Kicinski , Paolo Abeni , "David S . Miller" , Eric Dumazet , Sean Anderson Subject: [PATCH net-next 2/2] net: phy: dp83867: Always program R/SGMII enable bits Date: Thu, 29 Jan 2026 12:12:05 -0500 Message-Id: <20260129171205.3868605-3-sean.anderson@linux.dev> In-Reply-To: <20260129171205.3868605-1-sean.anderson@linux.dev> References: <20260129171205.3868605-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" If the board designers have neglected to populate the appropriate resistors on the strapping pins then the phy may default to the wrong interface mode. Enable/disable the RGMII/SGMII enable bits as necessary to select the correct interface. The dp83867 strapping pins have four levels and typically configure two features at once. LED_0 controls both port mirroring and whether SGMII is enabled. If it is pulled to VDDIO, both port mirroring and SGMII will be enabled. For variants of the dp83867 that do not support SGMII, this will prevent data from being transferred. As we now explicitly set the SGMII and RGMII enable bits, we do not need to detect whether SGMII has been inadvertently enabled. Signed-off-by: Sean Anderson --- drivers/net/phy/dp83867.c | 34 ++++++++++------------------------ 1 file changed, 10 insertions(+), 24 deletions(-) diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 7e16e9299457..3fb2293f568f 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -75,6 +75,7 @@ #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) =20 /* RGMIICTL bits */ +#define DP83867_RGMII_EN BIT(7) #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) =20 @@ -100,7 +101,7 @@ #define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) -#define DP83867_PHYCR_RESERVED_MASK BIT(11) +#define DP83867_PHYCR_SGMII_EN BIT(11) #define DP83867_PHYCR_FORCE_LINK_GOOD BIT(10) =20 /* RGMIIDCTL bits */ @@ -752,10 +753,12 @@ static int dp83867_config_init(struct phy_device *phy= dev) val |=3D (dp83867->tx_fifo_depth << DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT); =20 + val &=3D ~DP83867_PHYCR_SGMII_EN; if (phydev->interface =3D=3D PHY_INTERFACE_MODE_SGMII) { val &=3D ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK; val |=3D (dp83867->rx_fifo_depth << - DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT); + DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) | + DP83867_PHYCR_SGMII_EN; } =20 ret =3D phy_write(phydev, MII_DP83867_PHYCTRL, val); @@ -763,31 +766,10 @@ static int dp83867_config_init(struct phy_device *phy= dev) return ret; =20 if (phy_interface_is_rgmii(phydev)) { - val =3D phy_read(phydev, MII_DP83867_PHYCTRL); - if (val < 0) - return val; - - /* The code below checks if "port mirroring" N/A MODE4 has been - * enabled during power on bootstrap. - * - * Such N/A mode enabled by mistake can put PHY IC in some - * internal testing mode and disable RGMII transmission. - * - * In this particular case one needs to check STRAP_STS1 - * register's bit 11 (marked as RESERVED). - */ - - bs =3D phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); - if (bs & DP83867_STRAP_STS1_RESERVED) - val &=3D ~DP83867_PHYCR_RESERVED_MASK; - - ret =3D phy_write(phydev, MII_DP83867_PHYCTRL, val); - if (ret) - return ret; - /* Set up RGMII delays */ val =3D phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); =20 + val |=3D DP83867_RGMII_EN; val &=3D ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN= ); if (phydev->interface =3D=3D PHY_INTERFACE_MODE_RGMII_ID) val |=3D (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN= ); @@ -803,6 +785,10 @@ static int dp83867_config_init(struct phy_device *phyd= ev) phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, dp83867->rx_id_delay | (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); + } else { + val =3D phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); + val &=3D ~DP83867_RGMII_EN; + phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); } =20 /* If specified, set io impedance */ --=20 2.35.1.1320.gc452695387.dirty