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charset="utf-8" Add support for an optional enable GPIO that allows the multiplexer to be disabled before changing address lines and re-enabled after, preventing glitches during channel transitions. This is useful for devices like the Analog Devices ADG2404 (4:1 mux) that benefit from enable control to ensure clean channel switching. Acked-by: Conor Dooley Signed-off-by: Antoniu Miclaus Reviewed-by: Linus Walleij --- Changes in v6: - No code changes. --- .../devicetree/bindings/mux/gpio-mux.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/mux/gpio-mux.yaml b/Document= ation/devicetree/bindings/mux/gpio-mux.yaml index ef7e33ec85d4..798e0a73d77b 100644 --- a/Documentation/devicetree/bindings/mux/gpio-mux.yaml +++ b/Documentation/devicetree/bindings/mux/gpio-mux.yaml @@ -17,6 +17,9 @@ description: |+ multiplexer GPIO pins, where the first pin is the least significant bit. An active pin is a binary 1, an inactive pin is a binary 0. =20 + This binding supports GPIO-controlled multiplexers such as the Analog + Devices ADG2404 (4:1 mux with enable control). + properties: compatible: const: gpio-mux @@ -25,6 +28,18 @@ properties: description: List of gpios used to control the multiplexer, least significant bit= first. =20 + enable-gpios: + description: | + Optional GPIO to enable the multiplexer. When present, the mux is + disabled before changing address lines and re-enabled after. This + prevents glitches where an unintended channel could be briefly activ= ated + during address line transitions. When disabled, all outputs enter a + high-impedance (high-Z) state rather than holding their previous val= ue. + This is suitable for analog multiplexers where downstream capacitance + maintains the signal level during the brief disconnection. + Required for MUX_IDLE_DISCONNECT idle-state. + maxItems: 1 + mux-supply: description: Regulator to power on the multiplexer. @@ -59,6 +74,7 @@ examples: =20 mux-gpios =3D <&pioA 0 GPIO_ACTIVE_HIGH>, <&pioA 1 GPIO_ACTIVE_HIGH>; + enable-gpios =3D <&pioA 2 GPIO_ACTIVE_HIGH>; }; =20 adc-mux { --=20 2.43.0 From nobody Sat Feb 7 07:26:05 2026 Received: from mx0b-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0825330C626; Thu, 29 Jan 2026 15:57:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; 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Thu, 29 Jan 2026 10:57:05 -0500 From: Antoniu Miclaus To: Peter Rosin , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Antoniu Miclaus" , Srinivas Kandagatla , Linus Walleij , Johan Hovold , David Lechner , , Subject: [PATCH v6 2/2] mux: gpio-mux: add support for enable GPIO Date: Thu, 29 Jan 2026 17:56:21 +0200 Message-ID: <20260129155633.3985-3-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129155633.3985-1-antoniu.miclaus@analog.com> References: <20260129155633.3985-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Authority-Analysis: v=2.4 cv=PvmergM3 c=1 sm=1 tr=0 ts=697b8359 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gAnH3GRIAAAA:8 a=iafUaGi6XMNn_EhtBlsA:9 X-Proofpoint-GUID: lnuBdNhIym6EH8Fze5hSlXcWbkcjp5T7 X-Proofpoint-ORIG-GUID: lnuBdNhIym6EH8Fze5hSlXcWbkcjp5T7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI5MDExMSBTYWx0ZWRfXwgd927JBohRi SahmwswFMcDM4hIoU8dLRmIahqWSG1eiWBfS6SsBYwCdYsjlZIerzO0kiye/qGZNOKXEH106Std YmAA9E4nycqAm8TOfxSA26eQRl05V+TrB7/i30r0TJ43jQEJtoGuCZNBLx0JhPoV9p9m65A4lYU xLwh3Ux2spgzN5T5/LayiwAVB+KRBq4ITDuD3EW2De15Ak2HcXlsbGgkIvl3KT1s8Pz+fjL8Y6a OmkLuAY4XbGS9+4Pi+joAoaOlRX31ji70086HYWhucwcso0XbsdqeXqM42aiWUGbkJgrpusMU7o N2uzw7fb9qNqciDEnozkSxmp7L6Lo67l8HDpkKiihWUMYPR/BWsUBgxrfhOJKrp/q8m45aBzXiW XvLZDBjQLXYCvssOCVS+YjSw1Ax3/wovlxmRhqQ3LxPfc0cT57xwzqTj/eHLVj7+LX7v4RJZvnR qmIFfV0VDfvipGxhDVg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-29_02,2026-01-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 malwarescore=0 impostorscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601290111 Content-Type: text/plain; charset="utf-8" Add support for an optional enable GPIO to the gpio-mux driver. This allows the mux to be disabled before changing address lines and re-enabled after, preventing glitches that could briefly activate unintended channels during transitions. The enable GPIO is optional and the driver maintains backward compatibility with existing gpio-mux users. Signed-off-by: Antoniu Miclaus Reviewed-by: Linus Walleij --- Changes in v6: - Add error handling for gpiod functions - Make enable-gpios required for MUX_IDLE_DISCONNECT, optional otherwise - Remove redundant if (mux_gpio->enable) checks --- drivers/mux/gpio.c | 37 ++++++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/mux/gpio.c b/drivers/mux/gpio.c index 4cc3202c58f3..eeeff9587013 100644 --- a/drivers/mux/gpio.c +++ b/drivers/mux/gpio.c @@ -19,6 +19,7 @@ =20 struct mux_gpio { struct gpio_descs *gpios; + struct gpio_desc *enable; }; =20 static int mux_gpio_set(struct mux_control *mux, int state) @@ -26,12 +27,30 @@ static int mux_gpio_set(struct mux_control *mux, int st= ate) struct mux_gpio *mux_gpio =3D mux_chip_priv(mux->chip); DECLARE_BITMAP(values, BITS_PER_TYPE(state)); u32 value =3D state; + int ret; + + if (state =3D=3D MUX_IDLE_DISCONNECT) + return gpiod_set_value_cansleep(mux_gpio->enable, 0); + + /* + * Disable the mux before changing address lines to prevent + * glitches where an unintended channel could be briefly + * activated during the transition. When disabled, all mux + * outputs enter high-impedance (high-Z) state. For analog + * signals, downstream capacitance typically maintains the + * signal level during this brief disconnection. + */ + ret =3D gpiod_set_value_cansleep(mux_gpio->enable, 0); + if (ret) + return ret; =20 bitmap_from_arr32(values, &value, BITS_PER_TYPE(value)); =20 - gpiod_multi_set_value_cansleep(mux_gpio->gpios, values); + ret =3D gpiod_multi_set_value_cansleep(mux_gpio->gpios, values); + if (ret) + return ret; =20 - return 0; + return gpiod_set_value_cansleep(mux_gpio->enable, 1); } =20 static const struct mux_control_ops mux_gpio_ops =3D { @@ -73,12 +92,24 @@ static int mux_gpio_probe(struct platform_device *pdev) =20 ret =3D device_property_read_u32(dev, "idle-state", (u32 *)&idle_state); if (ret >=3D 0 && idle_state !=3D MUX_IDLE_AS_IS) { - if (idle_state < 0 || idle_state >=3D mux_chip->mux->states) { + if (idle_state =3D=3D MUX_IDLE_DISCONNECT) { + mux_gpio->enable =3D devm_gpiod_get(dev, "enable", + GPIOD_OUT_LOW); + if (IS_ERR(mux_gpio->enable)) + return dev_err_probe(dev, PTR_ERR(mux_gpio->enable), + "MUX_IDLE_DISCONNECT requires enable-gpios\n"); + } else if (idle_state < 0 || idle_state >=3D mux_chip->mux->states) { dev_err(dev, "invalid idle-state %u\n", idle_state); return -EINVAL; } =20 mux_chip->mux->idle_state =3D idle_state; + } else { + mux_gpio->enable =3D devm_gpiod_get_optional(dev, "enable", + GPIOD_OUT_LOW); + if (IS_ERR(mux_gpio->enable)) + return dev_err_probe(dev, PTR_ERR(mux_gpio->enable), + "failed to get enable gpio\n"); } =20 ret =3D devm_regulator_get_enable_optional(dev, "mux"); --=20 2.43.0