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Thu, 29 Jan 2026 02:31:06 -0800 From: Kartik Rajput To: , , , , , , , , , CC: Kartik Rajput Subject: [PATCH v10 1/3] i2c: tegra: Introduce tegra_i2c_variant to identify DVC and VI Date: Thu, 29 Jan 2026 16:00:41 +0530 Message-ID: <20260129103043.148490-2-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129103043.148490-1-kkartik@nvidia.com> References: <20260129103043.148490-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E8:EE_|BN7PPF0D942FA9A:EE_ X-MS-Office365-Filtering-Correlation-Id: d8d38434-28f3-46e5-bda9-08de5f219127 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?TsTp4gdd181EriVVKqUA5QMbkZj9TIGVODdAeI5X2sLG7DM2S2xOO0ZQvZQg?= =?us-ascii?Q?t4QxIMBD7GnHbg9i+BZtGcKf/77pVHb3qtb2aZwE10qhy40Oo4XStSDUMV7D?= =?us-ascii?Q?6vdjajKaMTOrkNbibuRueFKfU4iX85/LF2x4NFfV1h8Uy15S/nLc2VTrXNlg?= =?us-ascii?Q?kMqM6WK/iPFU4pzn7GzaUlLXspiDdhPCNB5LhD1si/1nnq5jdekbXLZU++28?= =?us-ascii?Q?lYuiXe9f6uQQNzntudbCCj2qAPttu3rQsI4DlgNSXJJxmEan3ZL6gHoTec0H?= =?us-ascii?Q?fLRq+YprHPcfURz7n9Rxv7QnM/NwMR05QJrQFSDOgBQrXWdrKOmE3Bhj8uz+?= =?us-ascii?Q?4E8c+jVK+AI8vMOPyjyU/2SobSH/qoE9CHbSAwu11JFUZmPn4MDpuny/+rCV?= =?us-ascii?Q?7TCFvXxirPRAA6Wat/dzGFMWeJS5CVT7M14mjrfwe2Ji6P0Ylo9cpjTAvx3X?= =?us-ascii?Q?TLyq4bebVq5XCvx1RfsAnP9qVVo0klIChRMPR3yo0oluhET+NZRsGcJBG1Oo?= =?us-ascii?Q?NNiWg1k0dkbrnWGcU1WgqUqU6V9fuHUa8j9MqbNH7AIg7Il7mbVOhcH+yEgs?= =?us-ascii?Q?4iQmzSTBZgbmx+ALN3L6F/NBYxe8nV1j/qcDDBpHBP5Zx/9uM3fPOm4TX4hE?= =?us-ascii?Q?DWN0xttH+AlAD1+wt3UoIDcbafzXA5n4uQt/5+1iSOd/So3+/hKCUtGwbQSz?= =?us-ascii?Q?rYvWqxpueu3Nl0O+nUZE6KXgT0rYJZcZL1t2UKjLx34WHcy38YE6mTUZuuHu?= =?us-ascii?Q?LTk04VPihLoToVOgqtT9lN9g4XyA5D6OVBue+/mT8U+SQpvhoOyVxqH+7mPu?= =?us-ascii?Q?hvO7sDSxIBUGi68bP3i1P+udKukyW+De/IWyrVvQoYNBb0JuCCgIKN8+fi+Z?= =?us-ascii?Q?qzJQKurssArISMgdyjvuFrAQN8LPmfw4tsI6n1Rwvi5hJ4efA4dCWjvpXHUh?= =?us-ascii?Q?84KPcy2xTg/p9xq9JyCh2ZLwkh/xrCcikFmtbbos1TG2xMVOonAp2xxeiYfu?= =?us-ascii?Q?e0bQ3JeHzNFloC02ko10YWdlI8pqeSTkIk9S9UJ/PaRLziC57/pkso5iGkLF?= =?us-ascii?Q?8Nl49lnqOuKb09HSL1NrNgIIYfkRAuStJNbmAb+vHyqqkbzetui71EOJfl06?= =?us-ascii?Q?66OjqbYV+7mBSOqjueLJHcevaqiYzk1+69IHcG2oCSmOqwuUXez9XgdrZjQs?= =?us-ascii?Q?C0p8LnFCQxQXG3D26A9jvMf9oOumjVicmtC0/J0lexaa3oR7pmHnL6Rof7wk?= =?us-ascii?Q?epYExPuion/lpi1vXe1zVwuwyD5VeGcExTqUt7pXj/ODJdNt7IllYkrh/kop?= =?us-ascii?Q?rKaBCkIu9MClg2t7xJlF9NoWOvxev6r5IRF4PrhI+gpeoYc1AmG7Ko8qLspf?= =?us-ascii?Q?0aPzniKJNhOZlzpZ06PMMcOAJPuT3ZAEriPjRrCbySaCbS2NlS4z3v1DvKqJ?= =?us-ascii?Q?sHJZMHIOXS4qjFPKDMEfz6CwjRksT9G8daBybmTUCI4mMAibasc6I7VaZzna?= =?us-ascii?Q?7rHj+fI7oIkqtTLQ7dgfwnCNYA5gwVUIaA9X37tn6ELSh0A3u1YtwWc8ATsJ?= =?us-ascii?Q?iv09fRY2EK3SZNuLKrSFertrkfMZHRr9E4oNVilwlKf646+55pWLCisM/j0Z?= =?us-ascii?Q?ZXfRZUFn6qDjD2vryPpJIcsf+jkfUelwgiXp0JujfwVMIgCFOlF578Y3D1b/?= =?us-ascii?Q?WWKW2lEXHxwYcEIz/27Cr5DmbbY=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2026 10:31:30.5641 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8d38434-28f3-46e5-bda9-08de5f219127 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF0D942FA9A Content-Type: text/plain; charset="utf-8" Replace the per-instance DVC/VI boolean flags with a tegra_i2c_variant enum and move the variant field into tegra_i2c_hw_feature so it is populated via SoC match data. Add dedicated SoC data entries for the "nvidia,tegra20-i2c-dvc" and "nvidia,tegra210-i2c-vi" compatibles and drop compatible-string checks from tegra_i2c_parse_dt. Suggested-by: Jon Hunter Signed-off-by: Kartik Rajput Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- Changes in v10: * Suqashed "i2c: tegra: Move variant to tegra_i2c_hw_feature" with this patch. --- drivers/i2c/busses/i2c-tegra.c | 112 ++++++++++++++++++++++++++++----- 1 file changed, 95 insertions(+), 17 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index bec619b9af4e..2ef5fba66b0f 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -171,6 +171,18 @@ enum msg_end_type { MSG_END_CONTINUE, }; =20 +/* + * tegra_i2c_variant: Identifies the variant of I2C controller. + * @TEGRA_I2C_VARIANT_DEFAULT: Identifies the default I2C controller. + * @TEGRA_I2C_VARIANT_DVC: Identifies the DVC I2C controller, has a differ= ent register layout. + * @TEGRA_I2C_VARIANT_VI: Identifies the VI I2C controller, has a differen= t register layout. + */ +enum tegra_i2c_variant { + TEGRA_I2C_VARIANT_DEFAULT, + TEGRA_I2C_VARIANT_DVC, + TEGRA_I2C_VARIANT_VI, +}; + /** * struct tegra_i2c_hw_feature : per hardware generation features * @has_continue_xfer_support: continue-transfer supported @@ -223,6 +235,7 @@ enum msg_end_type { * timing settings. * @enable_hs_mode_support: Enable support for high speed (HS) mode transf= ers. * @has_mutex: Has mutex register for mutual exclusion with other firmware= s or VMs. + * @variant: This represents the I2C controller variant. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -254,6 +267,7 @@ struct tegra_i2c_hw_feature { bool has_interface_timing_reg; bool enable_hs_mode_support; bool has_mutex; + enum tegra_i2c_variant variant; }; =20 /** @@ -268,8 +282,6 @@ struct tegra_i2c_hw_feature { * @base_phys: physical base address of the I2C controller * @cont_id: I2C controller ID, used for packet header * @irq: IRQ number of transfer complete interrupt - * @is_dvc: identifies the DVC I2C controller, has a different register la= yout - * @is_vi: identifies the VI I2C controller, has a different register layo= ut * @msg_complete: transfer completion notifier * @msg_buf_remaining: size of unsent data in the message buffer * @msg_len: length of message in current transfer @@ -321,12 +333,12 @@ struct tegra_i2c_dev { bool atomic_mode; bool dma_mode; bool msg_read; - bool is_dvc; - bool is_vi; }; =20 -#define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && (dev)->is_dvc) -#define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && (dev)->is_vi) +#define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && \ + (dev)->hw->variant =3D=3D TEGRA_I2C_VARIANT_DVC) +#define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && \ + (dev)->hw->variant =3D=3D TEGRA_I2C_VARIANT_VI) =20 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) @@ -1635,7 +1647,41 @@ static const struct tegra_i2c_hw_feature tegra20_i2c= _hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, +}; + +#if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) +static const struct tegra_i2c_hw_feature tegra20_dvc_i2c_hw =3D { + .has_continue_xfer_support =3D false, + .has_per_pkt_xfer_complete_irq =3D false, + .clk_divisor_hs_mode =3D 3, + .clk_divisor_std_mode =3D 0, + .clk_divisor_fast_mode =3D 0, + .clk_divisor_fast_plus_mode =3D 0, + .has_config_load_reg =3D false, + .has_multi_master_mode =3D false, + .has_slcg_override_reg =3D false, + .has_mst_fifo =3D false, + .has_mst_reset =3D false, + .quirks =3D &tegra_i2c_quirks, + .supports_bus_clear =3D false, + .has_apb_dma =3D true, + .tlow_std_mode =3D 0x4, + .thigh_std_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, + .setup_hold_time_std_mode =3D 0x0, + .setup_hold_time_fast_mode =3D 0x0, + .setup_hold_time_fastplus_mode =3D 0x0, + .setup_hold_time_hs_mode =3D 0x0, + .has_interface_timing_reg =3D false, + .enable_hs_mode_support =3D false, + .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DVC, }; +#endif =20 static const struct tegra_i2c_hw_feature tegra30_i2c_hw =3D { .has_continue_xfer_support =3D true, @@ -1665,6 +1711,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_= hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra114_i2c_hw =3D { @@ -1695,6 +1742,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c= _hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra124_i2c_hw =3D { @@ -1725,6 +1773,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra210_i2c_hw =3D { @@ -1755,7 +1804,41 @@ static const struct tegra_i2c_hw_feature tegra210_i2= c_hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, +}; + +#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) +static const struct tegra_i2c_hw_feature tegra210_vi_i2c_hw =3D { + .has_continue_xfer_support =3D true, + .has_per_pkt_xfer_complete_irq =3D true, + .clk_divisor_hs_mode =3D 1, + .clk_divisor_std_mode =3D 0x19, + .clk_divisor_fast_mode =3D 0x19, + .clk_divisor_fast_plus_mode =3D 0x10, + .has_config_load_reg =3D true, + .has_multi_master_mode =3D false, + .has_slcg_override_reg =3D true, + .has_mst_fifo =3D false, + .has_mst_reset =3D false, + .quirks =3D &tegra_i2c_quirks, + .supports_bus_clear =3D true, + .has_apb_dma =3D true, + .tlow_std_mode =3D 0x4, + .thigh_std_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, + .setup_hold_time_std_mode =3D 0, + .setup_hold_time_fast_mode =3D 0, + .setup_hold_time_fastplus_mode =3D 0, + .setup_hold_time_hs_mode =3D 0, + .has_interface_timing_reg =3D true, + .enable_hs_mode_support =3D false, + .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_VI, }; +#endif =20 static const struct tegra_i2c_hw_feature tegra186_i2c_hw =3D { .has_continue_xfer_support =3D true, @@ -1785,6 +1868,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra194_i2c_hw =3D { @@ -1817,6 +1901,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra256_i2c_hw =3D { @@ -1849,6 +1934,7 @@ static const struct tegra_i2c_hw_feature tegra256_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D true, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra264_i2c_hw =3D { @@ -1881,6 +1967,7 @@ static const struct tegra_i2c_hw_feature tegra264_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D true, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct of_device_id tegra_i2c_of_match[] =3D { @@ -1889,7 +1976,7 @@ static const struct of_device_id tegra_i2c_of_match[]= =3D { { .compatible =3D "nvidia,tegra194-i2c", .data =3D &tegra194_i2c_hw, }, { .compatible =3D "nvidia,tegra186-i2c", .data =3D &tegra186_i2c_hw, }, #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) - { .compatible =3D "nvidia,tegra210-i2c-vi", .data =3D &tegra210_i2c_hw, }, + { .compatible =3D "nvidia,tegra210-i2c-vi", .data =3D &tegra210_vi_i2c_hw= , }, #endif { .compatible =3D "nvidia,tegra210-i2c", .data =3D &tegra210_i2c_hw, }, { .compatible =3D "nvidia,tegra124-i2c", .data =3D &tegra124_i2c_hw, }, @@ -1897,7 +1984,7 @@ static const struct of_device_id tegra_i2c_of_match[]= =3D { { .compatible =3D "nvidia,tegra30-i2c", .data =3D &tegra30_i2c_hw, }, { .compatible =3D "nvidia,tegra20-i2c", .data =3D &tegra20_i2c_hw, }, #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) - { .compatible =3D "nvidia,tegra20-i2c-dvc", .data =3D &tegra20_i2c_hw, }, + { .compatible =3D "nvidia,tegra20-i2c-dvc", .data =3D &tegra20_dvc_i2c_hw= , }, #endif {}, }; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2026 10:31:28.8778 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13f3cc79-a61e-4d3f-af53-08de5f219026 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026369.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9554 Content-Type: text/plain; charset="utf-8" Tegra410 use different offsets for existing I2C registers, update the logic to use appropriate offsets per SoC. As the register offsets are now defined in the SoC-specific tegra_i2c_regs structures, the tegra_i2c_reg_addr() function is no longer needed to translate register offsets and has been removed. Signed-off-by: Kartik Rajput Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- Changes in v9: * Do not remove dvc_writel() and dvc_readl() calls. Changes in v8: * Replace usage of dvc_writel() with writel_relaxed(). * Remove dvc_writel(). Changes in v7: * Fix Tegra256 reg offsets, change it to tegra264_i2c_regs as it supports SW mutex. Changes in v6: * Do not remove dvc_writel(). * Keep DVC registers defined as a macro. * Correct Tegra20 DVC register offsets. * Remove sl_cnfg, sl_addr1 and sl_addr2 registers for DVC and VI as they are not used. Changes in v2: * Replace individual is_dvc and is_vi flags with an I2C variant. * Add tegra20_dvc_i2c_hw and tegra210_vi_i2c_hw in a separate patch. * Use calculated offsets for tegra20_dvc_i2c_regs and tegra210_vi_i2c_regs. * Initialize registers only if they are used on the given SoC. --- drivers/i2c/busses/i2c-tegra.c | 359 ++++++++++++++++++++++----------- 1 file changed, 237 insertions(+), 122 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 2ef5fba66b0f..d845b8782f4f 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -30,38 +30,29 @@ =20 #define BYTES_PER_FIFO_WORD 4 =20 -#define I2C_CNFG 0x000 #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12) #define I2C_CNFG_PACKET_MODE_EN BIT(10) #define I2C_CNFG_NEW_MASTER_FSM BIT(11) #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) -#define I2C_STATUS 0x01c -#define I2C_SL_CNFG 0x020 + #define I2C_SL_CNFG_NACK BIT(1) #define I2C_SL_CNFG_NEWSL BIT(2) -#define I2C_SL_ADDR1 0x02c -#define I2C_SL_ADDR2 0x030 -#define I2C_TLOW_SEXT 0x034 -#define I2C_TX_FIFO 0x050 -#define I2C_RX_FIFO 0x054 -#define I2C_PACKET_TRANSFER_STATUS 0x058 -#define I2C_FIFO_CONTROL 0x05c + #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5) #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2) -#define I2C_FIFO_STATUS 0x060 + #define I2C_FIFO_STATUS_TX GENMASK(7, 4) #define I2C_FIFO_STATUS_RX GENMASK(3, 0) -#define I2C_INT_MASK 0x064 -#define I2C_INT_STATUS 0x068 + #define I2C_INT_BUS_CLR_DONE BIT(11) #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) #define I2C_INT_NO_ACK BIT(3) #define I2C_INT_ARBITRATION_LOST BIT(2) #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) -#define I2C_CLK_DIVISOR 0x06c + #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16) #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0) =20 @@ -94,50 +85,38 @@ #define I2C_HEADER_CONTINUE_XFER BIT(15) #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 =20 -#define I2C_BUS_CLEAR_CNFG 0x084 #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16) #define I2C_BC_STOP_COND BIT(2) #define I2C_BC_TERMINATE BIT(1) #define I2C_BC_ENABLE BIT(0) -#define I2C_BUS_CLEAR_STATUS 0x088 + #define I2C_BC_STATUS BIT(0) =20 -#define I2C_CONFIG_LOAD 0x08c #define I2C_MSTR_CONFIG_LOAD BIT(0) =20 -#define I2C_CLKEN_OVERRIDE 0x090 #define I2C_MST_CORE_CLKEN_OVR BIT(0) =20 -#define I2C_INTERFACE_TIMING_0 0x094 -#define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8) -#define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0) -#define I2C_INTERFACE_TIMING_1 0x098 -#define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24) -#define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) -#define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8) -#define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) - -#define I2C_HS_INTERFACE_TIMING_0 0x09c -#define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8) -#define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0) -#define I2C_HS_INTERFACE_TIMING_1 0x0a0 -#define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) -#define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8) -#define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) - -#define I2C_MST_FIFO_CONTROL 0x0b4 +#define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8) +#define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0) +#define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24) +#define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) +#define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8) +#define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) + +#define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8) +#define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0) +#define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16) +#define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8) +#define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0) + #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) =20 -#define I2C_MST_FIFO_STATUS 0x0b8 #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) =20 -#define I2C_MASTER_RESET_CNTRL 0x0a8 - -#define I2C_SW_MUTEX 0x0ec #define I2C_SW_MUTEX_REQUEST GENMASK(3, 0) #define I2C_SW_MUTEX_GRANT GENMASK(7, 4) #define I2C_SW_MUTEX_ID_CCPLEX 9 @@ -159,6 +138,143 @@ */ #define I2C_PIO_MODE_PREFERRED_LEN 32 =20 +struct tegra_i2c_regs { + unsigned int cnfg; + unsigned int status; + unsigned int sl_cnfg; + unsigned int sl_addr1; + unsigned int sl_addr2; + unsigned int tlow_sext; + unsigned int tx_fifo; + unsigned int rx_fifo; + unsigned int packet_transfer_status; + unsigned int fifo_control; + unsigned int fifo_status; + unsigned int int_mask; + unsigned int int_status; + unsigned int clk_divisor; + unsigned int bus_clear_cnfg; + unsigned int bus_clear_status; + unsigned int config_load; + unsigned int clken_override; + unsigned int interface_timing_0; + unsigned int interface_timing_1; + unsigned int hs_interface_timing_0; + unsigned int hs_interface_timing_1; + unsigned int master_reset_cntrl; + unsigned int mst_fifo_control; + unsigned int mst_fifo_status; + unsigned int sw_mutex; +}; + +static const struct tegra_i2c_regs tegra20_i2c_regs =3D { + .cnfg =3D 0x000, + .status =3D 0x01c, + .sl_cnfg =3D 0x020, + .sl_addr1 =3D 0x02c, + .sl_addr2 =3D 0x030, + .tx_fifo =3D 0x050, + .rx_fifo =3D 0x054, + .packet_transfer_status =3D 0x058, + .fifo_control =3D 0x05c, + .fifo_status =3D 0x060, + .int_mask =3D 0x064, + .int_status =3D 0x068, + .clk_divisor =3D 0x06c, + .bus_clear_cnfg =3D 0x084, + .bus_clear_status =3D 0x088, + .config_load =3D 0x08c, + .clken_override =3D 0x090, + .interface_timing_0 =3D 0x094, + .interface_timing_1 =3D 0x098, + .hs_interface_timing_0 =3D 0x09c, + .hs_interface_timing_1 =3D 0x0a0, + .master_reset_cntrl =3D 0x0a8, + .mst_fifo_control =3D 0x0b4, + .mst_fifo_status =3D 0x0b8, +}; + +#if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) +static const struct tegra_i2c_regs tegra20_dvc_i2c_regs =3D { + .cnfg =3D 0x040, + .status =3D 0x05c, + .tx_fifo =3D 0x060, + .rx_fifo =3D 0x064, + .packet_transfer_status =3D 0x068, + .fifo_control =3D 0x06c, + .fifo_status =3D 0x070, + .int_mask =3D 0x074, + .int_status =3D 0x078, + .clk_divisor =3D 0x07c, + .bus_clear_cnfg =3D 0x094, + .bus_clear_status =3D 0x098, + .config_load =3D 0x09c, + .clken_override =3D 0x0a0, + .interface_timing_0 =3D 0x0a4, + .interface_timing_1 =3D 0x0a8, + .hs_interface_timing_0 =3D 0x0ac, + .hs_interface_timing_1 =3D 0x0b0, + .master_reset_cntrl =3D 0x0b8, + .mst_fifo_control =3D 0x0c4, + .mst_fifo_status =3D 0x0c8, +}; +#endif + +#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) +static const struct tegra_i2c_regs tegra210_vi_i2c_regs =3D { + .cnfg =3D 0x0c00, + .status =3D 0x0c70, + .tlow_sext =3D 0x0cd0, + .tx_fifo =3D 0x0d40, + .rx_fifo =3D 0x0d50, + .packet_transfer_status =3D 0x0d60, + .fifo_control =3D 0x0d70, + .fifo_status =3D 0x0d80, + .int_mask =3D 0x0d90, + .int_status =3D 0x0da0, + .clk_divisor =3D 0x0db0, + .bus_clear_cnfg =3D 0x0e10, + .bus_clear_status =3D 0x0e20, + .config_load =3D 0x0e30, + .clken_override =3D 0x0e40, + .interface_timing_0 =3D 0x0e50, + .interface_timing_1 =3D 0x0e60, + .hs_interface_timing_0 =3D 0x0e70, + .hs_interface_timing_1 =3D 0x0e80, + .master_reset_cntrl =3D 0x0ea0, + .mst_fifo_control =3D 0x0ed0, + .mst_fifo_status =3D 0x0ee0, +}; +#endif + +static const struct tegra_i2c_regs tegra264_i2c_regs =3D { + .cnfg =3D 0x000, + .status =3D 0x01c, + .sl_cnfg =3D 0x020, + .sl_addr1 =3D 0x02c, + .sl_addr2 =3D 0x030, + .tx_fifo =3D 0x050, + .rx_fifo =3D 0x054, + .packet_transfer_status =3D 0x058, + .fifo_control =3D 0x05c, + .fifo_status =3D 0x060, + .int_mask =3D 0x064, + .int_status =3D 0x068, + .clk_divisor =3D 0x06c, + .bus_clear_cnfg =3D 0x084, + .bus_clear_status =3D 0x088, + .config_load =3D 0x08c, + .clken_override =3D 0x090, + .interface_timing_0 =3D 0x094, + .interface_timing_1 =3D 0x098, + .hs_interface_timing_0 =3D 0x09c, + .hs_interface_timing_1 =3D 0x0a0, + .master_reset_cntrl =3D 0x0a8, + .mst_fifo_control =3D 0x0b4, + .mst_fifo_status =3D 0x0b8, + .sw_mutex =3D 0x0ec, +}; + /* * msg_end_type: The bus control which needs to be sent at end of transfer. * @MSG_END_STOP: Send stop pulse. @@ -236,6 +352,7 @@ enum tegra_i2c_variant { * @enable_hs_mode_support: Enable support for high speed (HS) mode transf= ers. * @has_mutex: Has mutex register for mutual exclusion with other firmware= s or VMs. * @variant: This represents the I2C controller variant. + * @regs: Register offsets for the specific SoC variant. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -268,6 +385,7 @@ struct tegra_i2c_hw_feature { bool enable_hs_mode_support; bool has_mutex; enum tegra_i2c_variant variant; + const struct tegra_i2c_regs *regs; }; =20 /** @@ -351,40 +469,26 @@ static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, u= nsigned int reg) return readl_relaxed(i2c_dev->base + reg); } =20 -/* - * If necessary, i2c_writel() and i2c_readl() will offset the register - * in order to talk to the I2C block inside the DVC block. - */ -static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int = reg) -{ - if (IS_DVC(i2c_dev)) - reg +=3D (reg >=3D I2C_TX_FIFO) ? 0x10 : 0x40; - else if (IS_VI(i2c_dev)) - reg =3D 0xc00 + (reg << 2); - - return reg; -} - static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned in= t reg) { - writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); + writel_relaxed(val, i2c_dev->base + reg); =20 /* read back register to make sure that register writes completed */ - if (reg !=3D I2C_TX_FIFO) - readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); + if (reg !=3D i2c_dev->hw->regs->tx_fifo) + readl_relaxed(i2c_dev->base + reg); else if (IS_VI(i2c_dev)) - readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS= )); + readl_relaxed(i2c_dev->base + i2c_dev->hw->regs->int_status); } =20 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg) { - return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); + return readl_relaxed(i2c_dev->base + reg); } =20 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, unsigned int reg, unsigned int len) { - writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); + writesl(i2c_dev->base + reg, data, len); } =20 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data, @@ -405,12 +509,12 @@ static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_= dev, void *data, static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, unsigned int reg, unsigned int len) { - readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); + readsl(i2c_dev->base + reg, data, len); } =20 static bool tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev) { - unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + unsigned int reg =3D i2c_dev->hw->regs->sw_mutex; u32 val, id; =20 val =3D readl(i2c_dev->base + reg); @@ -421,7 +525,7 @@ static bool tegra_i2c_mutex_acquired(struct tegra_i2c_d= ev *i2c_dev) =20 static bool tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev) { - unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + unsigned int reg =3D i2c_dev->hw->regs->sw_mutex; u32 val, id; =20 val =3D readl(i2c_dev->base + reg); @@ -459,7 +563,7 @@ static int tegra_i2c_mutex_lock(struct tegra_i2c_dev *i= 2c_dev) =20 static int tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev) { - unsigned int reg =3D tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX); + unsigned int reg =3D i2c_dev->hw->regs->sw_mutex; u32 val, id; =20 if (!i2c_dev->hw->has_mutex) @@ -482,16 +586,16 @@ static void tegra_i2c_mask_irq(struct tegra_i2c_dev *= i2c_dev, u32 mask) { u32 int_mask; =20 - int_mask =3D i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; - i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); + int_mask =3D i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask) & ~mask; + i2c_writel(i2c_dev, int_mask, i2c_dev->hw->regs->int_mask); } =20 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) { u32 int_mask; =20 - int_mask =3D i2c_readl(i2c_dev, I2C_INT_MASK) | mask; - i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); + int_mask =3D i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask) | mask; + i2c_writel(i2c_dev, int_mask, i2c_dev->hw->regs->int_mask); } =20 static void tegra_i2c_dma_complete(void *args) @@ -635,34 +739,34 @@ static void tegra_i2c_vi_init(struct tegra_i2c_dev *i= 2c_dev) =20 value =3D FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) | FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4); - i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0); + i2c_writel(i2c_dev, value, i2c_dev->hw->regs->interface_timing_0); =20 value =3D FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) | FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) | FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) | FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4); - i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1); + i2c_writel(i2c_dev, value, i2c_dev->hw->regs->interface_timing_1); =20 value =3D FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) | FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8); - i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0); + i2c_writel(i2c_dev, value, i2c_dev->hw->regs->hs_interface_timing_0); =20 value =3D FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) | FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) | FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11); - i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1); + i2c_writel(i2c_dev, value, i2c_dev->hw->regs->hs_interface_timing_1); =20 value =3D FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND; - i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG); + i2c_writel(i2c_dev, value, i2c_dev->hw->regs->bus_clear_cnfg); =20 - i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT); + i2c_writel(i2c_dev, 0x0, i2c_dev->hw->regs->tlow_sext); } =20 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, u32 reg, u32 mask, u32 delay_us, u32 timeout_us) { - void __iomem *addr =3D i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); + void __iomem *addr =3D i2c_dev->base + reg; u32 val; =20 if (!i2c_dev->atomic_mode) @@ -681,11 +785,11 @@ static int tegra_i2c_flush_fifos(struct tegra_i2c_dev= *i2c_dev) if (i2c_dev->hw->has_mst_fifo) { mask =3D I2C_MST_FIFO_CONTROL_TX_FLUSH | I2C_MST_FIFO_CONTROL_RX_FLUSH; - offset =3D I2C_MST_FIFO_CONTROL; + offset =3D i2c_dev->hw->regs->mst_fifo_control; } else { mask =3D I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH; - offset =3D I2C_FIFO_CONTROL; + offset =3D i2c_dev->hw->regs->fifo_control; } =20 val =3D i2c_readl(i2c_dev, offset); @@ -708,9 +812,9 @@ static int tegra_i2c_wait_for_config_load(struct tegra_= i2c_dev *i2c_dev) if (!i2c_dev->hw->has_config_load_reg) return 0; =20 - i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); + i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, i2c_dev->hw->regs->config_load); =20 - err =3D tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff, + err =3D tegra_i2c_poll_register(i2c_dev, i2c_dev->hw->regs->config_load, = 0xffffffff, 1000, I2C_CONFIG_LOAD_TIMEOUT); if (err) { dev_err(i2c_dev->dev, "failed to load config\n"); @@ -731,10 +835,10 @@ static int tegra_i2c_master_reset(struct tegra_i2c_de= v *i2c_dev) * SW needs to wait for 2us after assertion and de-assertion of this soft * reset. */ - i2c_writel(i2c_dev, 0x1, I2C_MASTER_RESET_CNTRL); + i2c_writel(i2c_dev, 0x1, i2c_dev->hw->regs->master_reset_cntrl); fsleep(2); =20 - i2c_writel(i2c_dev, 0x0, I2C_MASTER_RESET_CNTRL); + i2c_writel(i2c_dev, 0x0, i2c_dev->hw->regs->master_reset_cntrl); fsleep(2); =20 return 0; @@ -776,8 +880,8 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) if (i2c_dev->hw->has_multi_master_mode) val |=3D I2C_CNFG_MULTI_MASTER_MODE; =20 - i2c_writel(i2c_dev, val, I2C_CNFG); - i2c_writel(i2c_dev, 0, I2C_INT_MASK); + i2c_writel(i2c_dev, val, i2c_dev->hw->regs->cnfg); + i2c_writel(i2c_dev, 0, i2c_dev->hw->regs->int_mask); =20 if (IS_VI(i2c_dev)) tegra_i2c_vi_init(i2c_dev); @@ -822,12 +926,12 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_d= ev) clk_divisor =3D FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, i2c_dev->hw->clk_divisor_hs_mode) | FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); - i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); + i2c_writel(i2c_dev, clk_divisor, i2c_dev->hw->regs->clk_divisor); =20 if (i2c_dev->hw->has_interface_timing_reg) { val =3D FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); - i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); + i2c_writel(i2c_dev, val, i2c_dev->hw->regs->interface_timing_0); } =20 /* @@ -835,7 +939,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) * Otherwise, preserve the chip default values. */ if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) - i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); + i2c_writel(i2c_dev, tsu_thd, i2c_dev->hw->regs->interface_timing_1); =20 /* Write HS mode registers. These will get used only for HS mode*/ if (i2c_dev->hw->enable_hs_mode_support) { @@ -845,8 +949,8 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) =20 val =3D FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) | FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow); - i2c_writel(i2c_dev, val, I2C_HS_INTERFACE_TIMING_0); - i2c_writel(i2c_dev, tsu_thd, I2C_HS_INTERFACE_TIMING_1); + i2c_writel(i2c_dev, val, i2c_dev->hw->regs->hs_interface_timing_0); + i2c_writel(i2c_dev, tsu_thd, i2c_dev->hw->regs->hs_interface_timing_1); } =20 clk_multiplier =3D (tlow + thigh + 2) * (non_hs_mode + 1); @@ -859,12 +963,12 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_d= ev) } =20 if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) { - u32 sl_cfg =3D i2c_readl(i2c_dev, I2C_SL_CNFG); + u32 sl_cfg =3D i2c_readl(i2c_dev, i2c_dev->hw->regs->sl_cnfg); =20 sl_cfg |=3D I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; - i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); - i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); - i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); + i2c_writel(i2c_dev, sl_cfg, i2c_dev->hw->regs->sl_cnfg); + i2c_writel(i2c_dev, 0xfc, i2c_dev->hw->regs->sl_addr1); + i2c_writel(i2c_dev, 0x00, i2c_dev->hw->regs->sl_addr2); } =20 err =3D tegra_i2c_flush_fifos(i2c_dev); @@ -872,7 +976,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) return err; =20 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) - i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); + i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, i2c_dev->hw->regs->clken_ove= rride); =20 err =3D tegra_i2c_wait_for_config_load(i2c_dev); if (err) @@ -893,9 +997,9 @@ static int tegra_i2c_disable_packet_mode(struct tegra_i= 2c_dev *i2c_dev) */ udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz)); =20 - cnfg =3D i2c_readl(i2c_dev, I2C_CNFG); + cnfg =3D i2c_readl(i2c_dev, i2c_dev->hw->regs->cnfg); if (cnfg & I2C_CNFG_PACKET_MODE_EN) - i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); + i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, i2c_dev->hw->regs->= cnfg); =20 return tegra_i2c_wait_for_config_load(i2c_dev); } @@ -915,10 +1019,10 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_= dev *i2c_dev) return -EINVAL; =20 if (i2c_dev->hw->has_mst_fifo) { - val =3D i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); + val =3D i2c_readl(i2c_dev, i2c_dev->hw->regs->mst_fifo_status); rx_fifo_avail =3D FIELD_GET(I2C_MST_FIFO_STATUS_RX, val); } else { - val =3D i2c_readl(i2c_dev, I2C_FIFO_STATUS); + val =3D i2c_readl(i2c_dev, i2c_dev->hw->regs->fifo_status); rx_fifo_avail =3D FIELD_GET(I2C_FIFO_STATUS_RX, val); } =20 @@ -927,7 +1031,7 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_de= v *i2c_dev) if (words_to_transfer > rx_fifo_avail) words_to_transfer =3D rx_fifo_avail; =20 - i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); + i2c_readsl(i2c_dev, buf, i2c_dev->hw->regs->rx_fifo, words_to_transfer); =20 buf +=3D words_to_transfer * BYTES_PER_FIFO_WORD; buf_remaining -=3D words_to_transfer * BYTES_PER_FIFO_WORD; @@ -943,7 +1047,7 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_de= v *i2c_dev) * when (words_to_transfer was > rx_fifo_avail) earlier * in this function. */ - val =3D i2c_readl(i2c_dev, I2C_RX_FIFO); + val =3D i2c_readl(i2c_dev, i2c_dev->hw->regs->rx_fifo); val =3D cpu_to_le32(val); memcpy(buf, &val, buf_remaining); buf_remaining =3D 0; @@ -968,10 +1072,10 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_d= ev *i2c_dev) u32 val; =20 if (i2c_dev->hw->has_mst_fifo) { - val =3D i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); + val =3D i2c_readl(i2c_dev, i2c_dev->hw->regs->mst_fifo_status); tx_fifo_avail =3D FIELD_GET(I2C_MST_FIFO_STATUS_TX, val); } else { - val =3D i2c_readl(i2c_dev, I2C_FIFO_STATUS); + val =3D i2c_readl(i2c_dev, i2c_dev->hw->regs->fifo_status); tx_fifo_avail =3D FIELD_GET(I2C_FIFO_STATUS_TX, val); } =20 @@ -1002,9 +1106,9 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_de= v *i2c_dev) i2c_dev->msg_buf =3D buf + words_to_transfer * BYTES_PER_FIFO_WORD; =20 if (IS_VI(i2c_dev)) - i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); + i2c_writesl_vi(i2c_dev, buf, i2c_dev->hw->regs->tx_fifo, words_to_trans= fer); else - i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); + i2c_writesl(i2c_dev, buf, i2c_dev->hw->regs->tx_fifo, words_to_transfer= ); =20 buf +=3D words_to_transfer * BYTES_PER_FIFO_WORD; } @@ -1026,7 +1130,7 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_de= v *i2c_dev) i2c_dev->msg_buf_remaining =3D 0; i2c_dev->msg_buf =3D NULL; =20 - i2c_writel(i2c_dev, val, I2C_TX_FIFO); + i2c_writel(i2c_dev, val, i2c_dev->hw->regs->tx_fifo); } =20 return 0; @@ -1038,13 +1142,13 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev= _id) struct tegra_i2c_dev *i2c_dev =3D dev_id; u32 status; =20 - status =3D i2c_readl(i2c_dev, I2C_INT_STATUS); + status =3D i2c_readl(i2c_dev, i2c_dev->hw->regs->int_status); =20 if (status =3D=3D 0) { dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", - i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), - i2c_readl(i2c_dev, I2C_STATUS), - i2c_readl(i2c_dev, I2C_CNFG)); + i2c_readl(i2c_dev, i2c_dev->hw->regs->packet_transfer_status), + i2c_readl(i2c_dev, i2c_dev->hw->regs->status), + i2c_readl(i2c_dev, i2c_dev->hw->regs->cnfg)); i2c_dev->msg_err |=3D I2C_ERR_UNKNOWN_INTERRUPT; goto err; } @@ -1087,7 +1191,7 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_i= d) } } =20 - i2c_writel(i2c_dev, status, I2C_INT_STATUS); + i2c_writel(i2c_dev, status, i2c_dev->hw->regs->int_status); if (IS_DVC(i2c_dev)) dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); =20 @@ -1125,7 +1229,7 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_i= d) if (i2c_dev->hw->supports_bus_clear) tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); =20 - i2c_writel(i2c_dev, status, I2C_INT_STATUS); + i2c_writel(i2c_dev, status, i2c_dev->hw->regs->int_status); =20 if (IS_DVC(i2c_dev)) dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); @@ -1148,9 +1252,9 @@ static void tegra_i2c_config_fifo_trig(struct tegra_i= 2c_dev *i2c_dev, int err; =20 if (i2c_dev->hw->has_mst_fifo) - reg =3D I2C_MST_FIFO_CONTROL; + reg =3D i2c_dev->hw->regs->mst_fifo_control; else - reg =3D I2C_FIFO_CONTROL; + reg =3D i2c_dev->hw->regs->fifo_control; =20 if (i2c_dev->dma_mode) { if (len & 0xF) @@ -1161,7 +1265,7 @@ static void tegra_i2c_config_fifo_trig(struct tegra_i= 2c_dev *i2c_dev, dma_burst =3D 8; =20 if (i2c_dev->msg_read) { - reg_offset =3D tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); + reg_offset =3D i2c_dev->hw->regs->rx_fifo; =20 slv_config.src_addr =3D i2c_dev->base_phys + reg_offset; slv_config.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; @@ -1172,7 +1276,7 @@ static void tegra_i2c_config_fifo_trig(struct tegra_i= 2c_dev *i2c_dev, else val =3D I2C_FIFO_CONTROL_RX_TRIG(dma_burst); } else { - reg_offset =3D tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); + reg_offset =3D i2c_dev->hw->regs->tx_fifo; =20 slv_config.dst_addr =3D i2c_dev->base_phys + reg_offset; slv_config.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; @@ -1215,7 +1319,7 @@ static unsigned long tegra_i2c_poll_completion(struct= tegra_i2c_dev *i2c_dev, ktime_t ktimeout =3D ktime_add_ms(ktime, timeout_ms); =20 do { - u32 status =3D i2c_readl(i2c_dev, I2C_INT_STATUS); + u32 status =3D i2c_readl(i2c_dev, i2c_dev->hw->regs->int_status); =20 if (status) tegra_i2c_isr(i2c_dev->irq, i2c_dev); @@ -1274,14 +1378,14 @@ static int tegra_i2c_issue_bus_clear(struct i2c_ada= pter *adap) =20 val =3D FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND | I2C_BC_TERMINATE; - i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); + i2c_writel(i2c_dev, val, i2c_dev->hw->regs->bus_clear_cnfg); =20 err =3D tegra_i2c_wait_for_config_load(i2c_dev); if (err) return err; =20 val |=3D I2C_BC_ENABLE; - i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG); + i2c_writel(i2c_dev, val, i2c_dev->hw->regs->bus_clear_cnfg); tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); =20 time_left =3D tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, = 50); @@ -1292,7 +1396,7 @@ static int tegra_i2c_issue_bus_clear(struct i2c_adapt= er *adap) return -ETIMEDOUT; } =20 - val =3D i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); + val =3D i2c_readl(i2c_dev, i2c_dev->hw->regs->bus_clear_status); if (!(val & I2C_BC_STATUS)) { dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); return -EIO; @@ -1317,14 +1421,14 @@ static void tegra_i2c_push_packet_header(struct teg= ra_i2c_dev *i2c_dev, if (i2c_dev->dma_mode && !i2c_dev->msg_read) *dma_buf++ =3D packet_header; else - i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); + i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo); =20 packet_header =3D i2c_dev->msg_len - 1; =20 if (i2c_dev->dma_mode && !i2c_dev->msg_read) *dma_buf++ =3D packet_header; else - i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); + i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo); =20 packet_header =3D I2C_HEADER_IE_ENABLE; =20 @@ -1352,7 +1456,7 @@ static void tegra_i2c_push_packet_header(struct tegra= _i2c_dev *i2c_dev, if (i2c_dev->dma_mode && !i2c_dev->msg_read) *dma_buf++ =3D packet_header; else - i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); + i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo); } =20 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev, @@ -1473,7 +1577,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i= 2c_dev, =20 tegra_i2c_unmask_irq(i2c_dev, int_mask); dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", - i2c_readl(i2c_dev, I2C_INT_MASK)); + i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask)); =20 if (i2c_dev->dma_mode) { time_left =3D tegra_i2c_wait_completion(i2c_dev, @@ -1648,6 +1752,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_= hw =3D { .enable_hs_mode_support =3D false, .has_mutex =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, + .regs =3D &tegra20_i2c_regs, }; =20 #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) @@ -1680,6 +1785,7 @@ static const struct tegra_i2c_hw_feature tegra20_dvc_= i2c_hw =3D { .enable_hs_mode_support =3D false, .has_mutex =3D false, .variant =3D TEGRA_I2C_VARIANT_DVC, + .regs =3D &tegra20_dvc_i2c_regs, }; #endif =20 @@ -1712,6 +1818,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_= hw =3D { .enable_hs_mode_support =3D false, .has_mutex =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, + .regs =3D &tegra20_i2c_regs, }; =20 static const struct tegra_i2c_hw_feature tegra114_i2c_hw =3D { @@ -1743,6 +1850,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c= _hw =3D { .enable_hs_mode_support =3D false, .has_mutex =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, + .regs =3D &tegra20_i2c_regs, }; =20 static const struct tegra_i2c_hw_feature tegra124_i2c_hw =3D { @@ -1774,6 +1882,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c= _hw =3D { .enable_hs_mode_support =3D false, .has_mutex =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, + .regs =3D &tegra20_i2c_regs, }; =20 static const struct tegra_i2c_hw_feature tegra210_i2c_hw =3D { @@ -1805,6 +1914,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c= _hw =3D { .enable_hs_mode_support =3D false, .has_mutex =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, + .regs =3D &tegra20_i2c_regs, }; =20 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) @@ -1837,6 +1947,7 @@ static const struct tegra_i2c_hw_feature tegra210_vi_= i2c_hw =3D { .enable_hs_mode_support =3D false, .has_mutex =3D false, .variant =3D TEGRA_I2C_VARIANT_VI, + .regs =3D &tegra210_vi_i2c_regs, }; #endif =20 @@ -1869,6 +1980,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c= _hw =3D { .enable_hs_mode_support =3D false, .has_mutex =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, + .regs =3D &tegra20_i2c_regs, }; =20 static const struct tegra_i2c_hw_feature tegra194_i2c_hw =3D { @@ -1902,6 +2014,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c= _hw =3D { .enable_hs_mode_support =3D true, .has_mutex =3D false, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, + .regs =3D &tegra20_i2c_regs, }; =20 static const struct tegra_i2c_hw_feature tegra256_i2c_hw =3D { @@ -1935,6 +2048,7 @@ static const struct tegra_i2c_hw_feature tegra256_i2c= _hw =3D { .enable_hs_mode_support =3D true, .has_mutex =3D true, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, + .regs =3D &tegra264_i2c_regs, }; =20 static const struct tegra_i2c_hw_feature tegra264_i2c_hw =3D { @@ -1968,6 +2082,7 @@ static const struct tegra_i2c_hw_feature tegra264_i2c= _hw =3D { .enable_hs_mode_support =3D true, .has_mutex =3D true, .variant =3D TEGRA_I2C_VARIANT_DEFAULT, + .regs =3D &tegra264_i2c_regs, }; =20 static const struct of_device_id tegra_i2c_of_match[] =3D { --=20 2.43.0 From nobody Sat Feb 7 09:20:48 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011034.outbound.protection.outlook.com [52.101.52.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB2EE3803FD; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jan 2026 10:31:38.6248 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff2aff62-0185-4767-716c-08de5f2195e6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6106 Content-Type: text/plain; charset="utf-8" Add support for the Tegra410 SoC, which has 4 I2C controllers. The controllers are feature-equivalent to Tegra264; only the register offsets differ. Signed-off-by: Kartik Rajput Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- Changes in v3: * Updated timing parameters for Tegra410. --- drivers/i2c/busses/i2c-tegra.c | 63 ++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index d845b8782f4f..3c672f05373c 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -275,6 +275,34 @@ static const struct tegra_i2c_regs tegra264_i2c_regs = =3D { .sw_mutex =3D 0x0ec, }; =20 +static const struct tegra_i2c_regs tegra410_i2c_regs =3D { + .cnfg =3D 0x000, + .status =3D 0x01c, + .sl_cnfg =3D 0x020, + .sl_addr1 =3D 0x02c, + .sl_addr2 =3D 0x030, + .tx_fifo =3D 0x054, + .rx_fifo =3D 0x058, + .packet_transfer_status =3D 0x05c, + .fifo_control =3D 0x060, + .fifo_status =3D 0x064, + .int_mask =3D 0x068, + .int_status =3D 0x06c, + .clk_divisor =3D 0x070, + .bus_clear_cnfg =3D 0x088, + .bus_clear_status =3D 0x08c, + .config_load =3D 0x090, + .clken_override =3D 0x094, + .interface_timing_0 =3D 0x098, + .interface_timing_1 =3D 0x09c, + .hs_interface_timing_0 =3D 0x0a0, + .hs_interface_timing_1 =3D 0x0a4, + .master_reset_cntrl =3D 0x0ac, + .mst_fifo_control =3D 0x0b8, + .mst_fifo_status =3D 0x0bc, + .sw_mutex =3D 0x0f0, +}; + /* * msg_end_type: The bus control which needs to be sent at end of transfer. * @MSG_END_STOP: Send stop pulse. @@ -2085,6 +2113,40 @@ static const struct tegra_i2c_hw_feature tegra264_i2= c_hw =3D { .regs =3D &tegra264_i2c_regs, }; =20 +static const struct tegra_i2c_hw_feature tegra410_i2c_hw =3D { + .has_continue_xfer_support =3D true, + .has_per_pkt_xfer_complete_irq =3D true, + .clk_divisor_hs_mode =3D 1, + .clk_divisor_std_mode =3D 0x3f, + .clk_divisor_fast_mode =3D 0x2c, + .clk_divisor_fast_plus_mode =3D 0x11, + .has_config_load_reg =3D true, + .has_multi_master_mode =3D true, + .has_slcg_override_reg =3D true, + .has_mst_fifo =3D true, + .has_mst_reset =3D true, + .quirks =3D &tegra194_i2c_quirks, + .supports_bus_clear =3D true, + .has_apb_dma =3D false, + .tlow_std_mode =3D 0x8, + .thigh_std_mode =3D 0x7, + .tlow_fast_mode =3D 0x2, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x2, + .thigh_fastplus_mode =3D 0x2, + .tlow_hs_mode =3D 0x8, + .thigh_hs_mode =3D 0x6, + .setup_hold_time_std_mode =3D 0x08080808, + .setup_hold_time_fast_mode =3D 0x02020202, + .setup_hold_time_fastplus_mode =3D 0x02020202, + .setup_hold_time_hs_mode =3D 0x0b0b0b, + .has_interface_timing_reg =3D true, + .enable_hs_mode_support =3D true, + .has_mutex =3D true, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, + .regs =3D &tegra410_i2c_regs, +}; + static const struct of_device_id tegra_i2c_of_match[] =3D { { .compatible =3D "nvidia,tegra264-i2c", .data =3D &tegra264_i2c_hw, }, { .compatible =3D "nvidia,tegra256-i2c", .data =3D &tegra256_i2c_hw, }, @@ -2395,6 +2457,7 @@ static const struct acpi_device_id tegra_i2c_acpi_mat= ch[] =3D { {.id =3D "NVDA0101", .driver_data =3D (kernel_ulong_t)&tegra210_i2c_hw}, {.id =3D "NVDA0201", .driver_data =3D (kernel_ulong_t)&tegra186_i2c_hw}, {.id =3D "NVDA0301", .driver_data =3D (kernel_ulong_t)&tegra194_i2c_hw}, + {.id =3D "NVDA2017", .driver_data =3D (kernel_ulong_t)&tegra410_i2c_hw}, { } }; MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match); --=20 2.43.0