From nobody Mon Feb 9 01:35:01 2026 Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C93BD3346A0 for ; Thu, 29 Jan 2026 09:11:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.67 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677874; cv=none; b=qvNBpk2sD/H1AmrOE23ms9C07QJCnJC7p9NH5sXnxyoKYAQtH8KkGTt/sB5mKQ5y6Yb7qofXd6zRPYQuFRMTz8Nap05QVzv96Ve0qwcEpRM+egD6Cd0jvLJO07NRvg7NkLpdXPATdlu95zbpYo84Fg1K+KJ+jZOmxSOsnUXPyOo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677874; c=relaxed/simple; bh=whCqMCitloN4wFu7Cr4vtyiSLqxphxXk2OMNZa0+7lw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CSHtR4LDN2NR6oTHvHtSzeYvwfO39HI8sohhDNH/seXwdOas5VSHECL2/0zIw2XDxuXoPQ2Nk8uiatyl1r46JHByg66eLZY5oL4Z4O8PixgeLWExjXyK8ghqGI4r6GEpfbcoFtB+uIzgK1d87kwsbhQXzJqSr0FCqtKfe590km0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=GW1Ecmuk; arc=none smtp.client-ip=209.85.128.67 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GW1Ecmuk" Received: by mail-wm1-f67.google.com with SMTP id 5b1f17b1804b1-4805ef35864so5500275e9.0 for ; Thu, 29 Jan 2026 01:11:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769677871; x=1770282671; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wLhqjdXh9Y6qAyHzZ9r5IyywkiPoN7iN9AMjJ8Bl+Nw=; b=GW1EcmukRParFNqhT8RDoGZefOnN2Cbe36mDf/ZZTlfMPQI20vtpE+BtzNN4q/9NHE GzRnpJRvl3e94jhHEezfwpCGnupBY4JYexP68NODVlOMgYWUAijfmuysJ475KC37nDRZ ljAMVos3VYx5jyGi01WC09BkbFBSX1kmStVEm7g+p7y0Yi7NJ4gfVRKOEch6HQ6bKmaM Y28N2vTvh+ULbrlNVlCa12SD1BS0tijhkjI60bHFk91pCj3gxBPckrmPPQFnmLxnAIRz cgqdCYB5Ek2gXr3TS8ui47eQGxor5CMiARMJFeS/fVZ1Fu4GMS0w/35QxXoUbByNf0ND /xZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769677871; x=1770282671; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=wLhqjdXh9Y6qAyHzZ9r5IyywkiPoN7iN9AMjJ8Bl+Nw=; b=JfbGOknwlV3KdeCWVez39VHpDY2kPrNSMqC9kzYYLd52+meSh2srC6Gox0qKWDnEaT 026BfM7Hube3RNHXl4gg76kEK+UlkFX3pdBvpwJA+g1SnQVitIQbC1NFiGlSY8PkZpEW 8ar2HRx77M3C87oWN4/asoHMJ+THMwjHGIoojS2tp8qI+1TVzIK59JkdxnBJzNMiCP7R k5TxdOPKjiJCEjxOP/lw2UC6mSyC7McZX/vdRya1IAMc5vRMYrNJvO1gbjd+cLpd3v2n Tx+c2qsFgI6MCgEC2Ki+LZRmvaMi6hKhq3z0uiOf0lFxiW+mPuM4NPbBQQ631lPUzFdR vyxQ== X-Forwarded-Encrypted: i=1; AJvYcCXYQJaJjCeCMhAUibKDFHJ+clxTnos6y2GkxrZW7ZzqEikxxOL49UOcBGOJU221IxBVU5tUo7dIyqrTkm0=@vger.kernel.org X-Gm-Message-State: AOJu0Yy4SLQjP0qRuL86QDM3+00q/l9pF+u0D0rNa2CdogAmCnrLCn/h JkSGLE00G5j5jbdrqbwS2Mn1H1D0AX6d7OYwL62mM1ml4+b5n0V0ccpU X-Gm-Gg: AZuq6aKJ8UT+E3+c6ZDKp6aBus7VeEiIQwQoXlcCng5gaP3rqN3bsJG5NX0aeIDv1yw lNj/5xkbbqF22HMiFSQ1Vu5Lc4UNdGvz5ts1WtRKa4dwQZ/hbejXPl1P66qAtZ402GtaSSUWOgj Gzdgj/oWl3p5YMpTrFzXrikag+nOTxsfwWDAsJqfHghnCo6MqVLcNUQEadOHafFClDuF5/izAbG 0omtBaUTYO0YixmZfwIS5S7JVViNvg6Q+asWWcc7X8rYquz3KI8ur0X6qreHWYJe1b0+IeFLTL5 LumdkdF6Ccr6vaP3BIQkKzU0C5ZiIGakLAnTmPcTYygSdCtdm0UgHw2q0ROL5kd2Rvn6CzHuM8X Q8O72QUTqEflIUZEXUol19SxFs4D6g/uA2AZU77AuOHQhoSSApRedTlLzxOJbewDA2rUPrRp2VM kftBPd+woeb7/sbQs4 X-Received: by 2002:a05:600c:154c:b0:475:de12:d3b5 with SMTP id 5b1f17b1804b1-48069c6136fmr86663635e9.34.1769677871157; Thu, 29 Jan 2026 01:11:11 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:5792:2065:403:a80b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066be77b5sm175338875e9.2.2026.01.29.01.11.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 01:11:10 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: Biju Das , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das Subject: [PATCH 1/9] dt-bindings: pinctrl: renesas: Document reset-names Date: Thu, 29 Jan 2026 09:10:52 +0000 Message-ID: <20260129091108.95277-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> References: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das All SoCs has multiple resets. Document reset-names property. Signed-off-by: Biju Das --- .../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +++++++++++++++ arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 1 + arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 1 + 8 files changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya= ml index 00c05243b9a4..fbbba53cde9b 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -78,6 +78,16 @@ properties: - description: PFC main reset - description: Reset for the control register related to WDTUDFC= A and WDTUDFFCM pins =20 + reset-names: + oneOf: + - items: + - const: rstn + - const: port + - const: spare + - items: + - const: main + - const: error + additionalProperties: anyOf: - type: object @@ -152,10 +162,14 @@ allOf: properties: resets: maxItems: 2 + reset-names: + maxItems: 2 else: properties: resets: minItems: 3 + reset-names: + maxItems: 3 =20 required: - compatible @@ -187,6 +201,7 @@ examples: resets =3D <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; + reset-names =3D "rstn", "port", "spare"; power-domains =3D <&cpg>; =20 scif0_pins: serial0 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/d= ts/renesas/r9a07g043.dtsi index 593c66b27ad1..ded4f1f11d60 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -604,6 +604,7 @@ pinctrl: pinctrl@11030000 { resets =3D <&cpg R9A07G043_GPIO_RSTN>, <&cpg R9A07G043_GPIO_PORT_RESETN>, <&cpg R9A07G043_GPIO_SPARE_RESETN>; + reset-names =3D "rstn", "port", "spare"; }; =20 dmac: dma-controller@11820000 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/d= ts/renesas/r9a07g044.dtsi index 29273da81995..cb0c9550aa03 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1017,6 +1017,7 @@ pinctrl: pinctrl@11030000 { resets =3D <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; + reset-names =3D "rstn", "port", "spare"; }; =20 irqc: interrupt-controller@110a0000 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/d= ts/renesas/r9a07g054.dtsi index 0dee48c4f1e4..7a3e5b6a685f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1025,6 +1025,7 @@ pinctrl: pinctrl@11030000 { resets =3D <&cpg R9A07G054_GPIO_RSTN>, <&cpg R9A07G054_GPIO_PORT_RESETN>, <&cpg R9A07G054_GPIO_SPARE_RESETN>; + reset-names =3D "rstn", "port", "spare"; }; =20 irqc: interrupt-controller@110a0000 { diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 997e6cf0bb82..3a69bb246bab 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -533,6 +533,7 @@ pinctrl: pinctrl@11030000 { resets =3D <&cpg R9A08G045_GPIO_RSTN>, <&cpg R9A08G045_GPIO_PORT_RESETN>, <&cpg R9A08G045_GPIO_SPARE_RESETN>; + reset-names =3D "rstn", "port", "spare"; }; =20 irqc: interrupt-controller@11050000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g047.dtsi index cbb48ff5028f..66f40cb1464d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -265,6 +265,7 @@ pinctrl: pinctrl@10410000 { interrupt-parent =3D <&icu>; power-domains =3D <&cpg>; resets =3D <&cpg 0xa5>, <&cpg 0xa6>; + reset-names =3D "main", "error"; }; =20 cpg: clock-controller@10420000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g056.dtsi index 9fb15ca24984..e85daef4e42d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -288,6 +288,7 @@ pinctrl: pinctrl@10410000 { gpio-ranges =3D <&pinctrl 0 0 96>; power-domains =3D <&cpg>; resets =3D <&cpg 0xa5>, <&cpg 0xa6>; + reset-names =3D "main", "error"; }; =20 cpg: clock-controller@10420000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g057.dtsi index 80cba9fcfe7b..38793b948c02 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -270,6 +270,7 @@ pinctrl: pinctrl@10410000 { interrupt-parent =3D <&icu>; power-domains =3D <&cpg>; resets =3D <&cpg 0xa5>, <&cpg 0xa6>; + reset-names =3D "main", "error"; }; =20 cpg: clock-controller@10420000 { --=20 2.43.0 From nobody Mon Feb 9 01:35:01 2026 Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78AD6376BE8 for ; Thu, 29 Jan 2026 09:11:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.68 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677875; cv=none; b=cBjyORarrokJukHWz+/9pyug0T6DVsJ9cK44z7MhZ1zYVsGT217/OBlapvBuymL1ZRZojqq3N5DNt+Nz40yHpZH2BF2SaC5H8ewtU9U4lRaTLytDMDgpjm3E7mMes+BDsdr5CYqBuyH2einx4Wbc0UPqJ46mUXvLm7uY0vpNGCo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677875; c=relaxed/simple; bh=5HXaWSiI3vXmlt7Hf8eg5mNctMjnuBFiMLGRDTMd4ZM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W+l44fzgEuzlaCOM0Ic37mC5A5GLaQgLEZqk2KdzWyKODohe1ZxZe+0KQBFyo7mCrdjpChmiDDmyip4V9HeEJNm2ZDT66PtNgxp3VbP/JdPi64xIoenZTtBJ7uvkw3ByEL02+Tp8F1CtBEV2ezH531Xk6wnVQerMSPvmsTX7JeE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=mUdeDKfx; arc=none smtp.client-ip=209.85.128.68 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mUdeDKfx" Received: by mail-wm1-f68.google.com with SMTP id 5b1f17b1804b1-481188b7760so3453645e9.0 for ; Thu, 29 Jan 2026 01:11:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769677872; x=1770282672; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AHcoX9dbLBVOvdJKUTZ5uf7S6EXVjOaeeDaRiom2PWQ=; b=mUdeDKfxPnZS/WG3VfQH35vgvlGJ5R9ZUg4r64U+WoxGmHUbIk0xk2zejoNjGEm1Jg kaelo88r8nxV0Ellfk6CS9JjsCrHDNUUoyCbib+7UGo0EIFHGyY5T49Qyuh7SZM1kIGo 5GeieF3BnyO+RA5B4RkEZw/sgBQSnSNboGbrRlRWSKNGLplnVHOcmn6KhVxRj5G0818b KKMsFbxXvWKzns2EQFTQVz0P1nL/GZ4e5eNZk6MG4fDlFL1wi9rZ97x4EKFziQcDydvq 14iL20QLH2R/ekg/jim6J5NYOOliclknzp0FjfFe6cwqXYL0VGnnHJhbpuEVMq5zs19B jzBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769677872; x=1770282672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=AHcoX9dbLBVOvdJKUTZ5uf7S6EXVjOaeeDaRiom2PWQ=; b=uq4AqoQFA4nys4SwVON53sjJU2OD1zyX/HYFjme8157NxiTKJ5rfP2aDDUl1BXd19U IexOGq2FxfQFDv4kENrSZsks24T0pbC37emESX07hrKCnPy+93SSonF2hGOsNz/i9Eca ETBFG0Aa3rMhnfftZ2l/SwJV/C92OHGszzZxMBrezePfX/3AxH65V7F5bNnt1mJLuiKw 3C1PRlC+0b7w1r6tL/EtecLOkSr/uKsjeb0a3Bgz84Ems3pKqHQYixKfkBWMBwnxgYdK Gs/HqQAHvTz/C4MvwAUospX+pcurb6CjkhGVmrc2XnyUqfFh3cI7+7JJxGv3ONMn0bfq HMRA== X-Forwarded-Encrypted: i=1; AJvYcCUZO23WttkZn315etbiioga1IWxOG4jkgWQXrl7KBllGYb/u+EWglLa7GPnS0FuZ78HAk6jze+BWUo8cFw=@vger.kernel.org X-Gm-Message-State: AOJu0YwKUtXObHoxzrHGB/cKWA1VEGweOiD8QiMwe35D9u5F+Qk21TOh av/HIX/4qC+i9Wmn70j2MVEfAA6z+UlhHs/psDcQDw7Km6K5oATz68x2 X-Gm-Gg: AZuq6aLusE/NYwkEKmmje1yzr107Dvm15iwTGm5EJAZyseRqttD6Jiy7fdNqV3qbPVH iBG2TbioAp3Qq8ieHm54DaQmO+oCpFuUfEoOJB5cGA20ztrMefQEc6hODkZFlKFkIgf7jSbvowV INBlWX5fG+bJl61/XbSlqzLvjxwMChZEBSw/szK92pN5DlvkysFatfM+/pO6Qq4VuYBXzSpZxeE bloeBDOBc1Vpwi3YzbPJ5HHKk+iNKXgldhu0P7MFdCp0qP9hSD+mA3XfRcTKyF4vLKfyXciDAc9 bss0HOEKcKraJ3VGyUUq9bpAA6XDbAVoaW/mb9vjFguqCgZWSZ1GrqGCjHXQmMa8eHcZa7AIcDQ dzwhjOMtAl1Wjg3nic1RFsKpr070De3jSo+JbVB0E3ocvXkUOIs70wDvXtuy7OpRqq8CCvC9LcP B8JFIBuYvqJgH5fJmM X-Received: by 2002:a05:600c:8b61:b0:46e:32dd:1b1a with SMTP id 5b1f17b1804b1-48069bfad7fmr105512965e9.7.1769677871750; Thu, 29 Jan 2026 01:11:11 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:5792:2065:403:a80b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066be77b5sm175338875e9.2.2026.01.29.01.11.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 01:11:11 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: Biju Das , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das Subject: [PATCH 2/9] dt-bindings: pinctrl: renesas: Document RZ/G3L SoC Date: Thu, 29 Jan 2026 09:10:53 +0000 Message-ID: <20260129091108.95277-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> References: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add documentation for the pin controller found on the Renesas RZ/G3L (R9A08G046) SoC. The RZ/G3L PFC is similar to the RZ/G3S SoC but has more pins. Also add header file similar to RZ/G3E and RZ/V2H as it has alpha numeric ports. Signed-off-by: Biju Das --- .../pinctrl/renesas,rzg2l-pinctrl.yaml | 1 + .../pinctrl/renesas,r9a08g046-pinctrl.h | 39 +++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya= ml index fbbba53cde9b..dc7f92c35eae 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/= Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S + - renesas,r9a08g046-pinctrl # RZ/G3L - renesas,r9a09g047-pinctrl # RZ/G3E - renesas,r9a09g056-pinctrl # RZ/V2N - renesas,r9a09g057-pinctrl # RZ/V2H(P) diff --git a/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h b/incl= ude/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h new file mode 100644 index 000000000000..660c26477d42 --- /dev/null +++ b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G3L family pinctrl bindin= gs. + * + * Copyright (C) 2026 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ +#define __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ + +#include + +/* RZG3L_Px =3D Offset address of PFC_P_mn - 0x22 */ +#define RZG3L_P2 2 +#define RZG3L_P3 3 +#define RZG3L_P4 4 +#define RZG3L_P5 5 +#define RZG3L_P6 6 +#define RZG3L_P7 7 +#define RZG3L_P8 8 +#define RZG3L_PA 10 +#define RZG3L_PB 11 +#define RZG3L_PC 12 +#define RZG3L_PD 13 +#define RZG3L_PE 14 +#define RZG3L_PF 15 +#define RZG3L_PG 16 +#define RZG3L_PH 17 +#define RZG3L_PJ 19 +#define RZG3L_PK 20 +#define RZG3L_PL 21 +#define RZG3L_PM 22 +#define RZG3L_PS 28 + +#define RZG3L_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3L_P##b, p, f) +#define RZG3L_GPIO(port, pin) RZG2L_GPIO(RZG3L_P##port, pin) + +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ */ --=20 2.43.0 From nobody Mon Feb 9 01:35:01 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35D57376BE6 for ; Thu, 29 Jan 2026 09:11:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677875; cv=none; b=tfCFUZCwisLU4dLyRu79FSPrnaUq87WhUzjD/LTx/9Pp2TC3oJKpfYZVp1j785LQl7CuKp9b6aiWlEn21dkv3tuLdJ1O8tYDgFhAh7F8xXeiekm+xsdBnhWJ553AMN+e/A4auvoQ9qs/hfwgih7fkS2tGh2+P2TYA2o4b8nOTyo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677875; c=relaxed/simple; bh=xzApL+tOXmpVuGXhCiWBafOpCmGl0cWaKQ4hIdAkSwE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r8/kMp/oUgGkWtVXX0xyMbmxOskiDudAmN2EL2DoI5Zbua3GtGnSwXSRGVw9IJyfUZDsQkGBygI4EhIQiHImZWylATro3RtfHEfUf64hYq+ApJHf7eaKuhJDINYR/8nIIjIt+z+RnP749tXtv8iu+RtppizXsSM6EBmRbmUZzps= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=coz5DDJ9; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="coz5DDJ9" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4801eb2c0a5so6720615e9.3 for ; Thu, 29 Jan 2026 01:11:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769677872; x=1770282672; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rLDqQlTrMND5cjb5pp+RmbUOuIdXjH56f5dfNu8LRdI=; b=coz5DDJ9PUOn1JBgmMQCW5k9N71Y5elmZUAX0Lrxd8FHlplHfMV1sFTMgTgH4CC8YO A+fQnjhFIzeLvPFgGrpovSKz+DGCcPVK2EE3VcLTHnu15i1u0ELKabFuAq14gjHHHefT 5svHQu80n1GM374cIYC/Clwku8tnJeMnpyZUtYB3Wb8en4zmKlUnelEFD/fKm0IcBa1W sqZiwvoj8cdyU5uMFGJj79HeHyC+fYnbuH4zQAsKhtd3BvKYpZwNTH0Ld9TxSZ6r9oIF Je2QSd1+qHiHzRrNdrVKzyz/y6+ITImCdIfM+xH5UGersr3rdYBSqoKjdFjV3mfDTVHA 0afQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769677872; x=1770282672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=rLDqQlTrMND5cjb5pp+RmbUOuIdXjH56f5dfNu8LRdI=; b=Qnt2+dmO/TQvEclf9bfO331xSZFeuldVPMR40+bYtMSrNQ9xHU5hDNYloH4e+/ntcV SKlS3kGyMYJo/f75xOhflL/sAwAS0A0DEGnorrV1iNnhgQedkKQzL5DVZ5xgomHrFEWc AVSntLlA3Uc194AxjYU1bG+vLBt9PFcTV1+VwnMDmJbALndzChiXKZEW8FDp2Hqj275y meaq8y65ru9Zvh2ThX+ZywaIPtMNCRudjRBgBfQJib0mA+sENGuqvX57UcN78n9shyzE FV4JHwWrXaPi4LgonvLyI49ZjbBot7yO7aqDJTcexDAFeiQEKhaDXpr64GIfrFNseMIg OOhg== X-Forwarded-Encrypted: i=1; AJvYcCXjuY/SGfdD0UCJuspv4luEhd9onk6iGn6+xjvrfDoOKjxZ/DXRzvnGO1LwsT8A2lCOZLemxwoq0Vnrwq4=@vger.kernel.org X-Gm-Message-State: AOJu0Ywf01SNRNMNP0vE9vCUESPoiHROHj8DjLMrZ0GRzWwofDiimsxA DQ/OwRQtKRGBzcfsulqQIwPG9DcnI9snFFjQnHLbCK6+FX2/rKMGTuwzzxprTA== X-Gm-Gg: AZuq6aL/QjyVU6xROjOPxkIJa5necpb2mTKH+zg54tUASvYfxsxpWqawaDDFDW8rfA8 p4/myJhOhxg9AlELwcP+YXmkJvEIUPWRvbp8HOwEUzpz0+83dzBOZhS64aWs3APMIrggheGO2ro C4vGqc4p4+gE93VIOSj5MuRrErHkCIxZ/7wF7CIk7PtlNPVQMrowYR5LCyzYtVyGENVTJj4XM/t 5q+jIRtgEb0Jcmn0Wi50fLAC2o/hNbyGR1vtR4dk6+itCik/TM9IRfKayV8itwZ00qNsSQSRMgy Boq9A3IH7Oska8+bsW5IFF4T71aJqaFpj5DTz4ezybZwDYoE9566yP+7VnhoVzCJ/CgK2fTH3ZP folNJ9VGeCIGVxxu/P8l6jBF4+VEMagCorSECczpbOAg8SLFKwkErrgCKuQkxBrn8+6zgV9ZCwB 5zc55S6Hv8i2To2X8E X-Received: by 2002:a05:600c:5395:b0:477:c478:46d7 with SMTP id 5b1f17b1804b1-48069c55751mr102964815e9.22.1769677872353; Thu, 29 Jan 2026 01:11:12 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:5792:2065:403:a80b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066be77b5sm175338875e9.2.2026.01.29.01.11.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 01:11:12 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 3/9] clk: renesas: r9a08g046: Add GPIO clocks/resets Date: Thu, 29 Jan 2026 09:10:54 +0000 Message-ID: <20260129091108.95277-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> References: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add GPIO clock and reset entries. Signed-off-by: Biju Das --- drivers/clk/renesas/r9a08g046-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index e74bab2df29a..4d1b9c8c524f 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -174,6 +174,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { DEF_FIXED("ETHRM1", R9A08G046_CLK_ETHRM1, CLK_ETH1_RM, 1, 1), DEF_FIXED("ETHTX12", R9A08G046_CLK_ETHTX12, CLK_SEL_ETH1_TX, 1, 1), DEF_FIXED("ETHRX12", R9A08G046_CLK_ETHRX12, CLK_SEL_ETH1_RX, 1, 1), + DEF_FIXED("OSCCLK", R9A08G046_OSCCLK, CLK_EXTAL, 1, 1), }; =20 static const struct rzg2l_mod_clk r9a08g046_mod_clks[] =3D { @@ -221,6 +222,8 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = =3D { MSTOP(BUS_PERI_COM, BIT(3))), DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584= , 0, MSTOP(BUS_MCPU2, BIT(1))), + DEF_MOD("gpio_hclk", R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0, + MSTOP(BUS_PERI_CPU, BIT(6))), }; =20 static const struct rzg2l_reset r9a08g046_resets[] =3D { @@ -232,6 +235,9 @@ static const struct rzg2l_reset r9a08g046_resets[] =3D { DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0), DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1), DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0), + DEF_RST(R9A08G046_GPIO_RSTN, 0x898, 0), + DEF_RST(R9A08G046_GPIO_PORT_RESETN, 0x898, 1), + DEF_RST(R9A08G046_GPIO_SPARE_RESETN, 0x898, 2), }; =20 static const unsigned int r9a08g046_crit_mod_clks[] __initconst =3D { --=20 2.43.0 From nobody Mon Feb 9 01:35:01 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9873A37BE7F for ; Thu, 29 Jan 2026 09:11:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677876; cv=none; b=maMOl7iEl6Q7Sxv7j4ZEF19hnXFnhLpl1cgFMtZUh/IvD3jGMjIiuC1JJ9AVc5VvUk+FtJpbVTuGeK2OmiC14bNQG6Ypcj+kuX5j4oz5fQbqQD3FU6rqSwStRWWka6IrkhXiNdlmE2U0rFq4lgNuf+9h8zF1bpQK2k48NP5pwkI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677876; c=relaxed/simple; bh=tiJxoBJKqiDxJyRh8KuDPOyTjxFZmwC+C2EPVKUwaD4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qREkfP1tnbS578TE4D2zUz38Q2v5cfd4SoNXudOlxn+3IYkHCKIe2VpmQUeRS2X+cWYcXnaEOLF9sJioQJTh7WyUjRINJRtYLCV5MihrilJqcTqR81RnY8szlvsEIpAZz9BspAQeB4ePugu5T9rfivG6sTcTCc/7GB6DN1IKxss= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jfsEJiS6; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jfsEJiS6" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-480142406b3so4964665e9.1 for ; Thu, 29 Jan 2026 01:11:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769677873; x=1770282673; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nayUkHKP6L91MLG9SEcHVEuSxFmIGO+/zRwcQEweek0=; b=jfsEJiS6p7/Wt/X4OfCbvnNSsGuocLN013Q5sJNRrAKlM6YpZaQ3rz6pixM55mfXtX cxvvMKhwfr2M/VByOuHVyTYCq9LPwcPHlEGl6G6gJTKlgNf2a+K20Qi9ZdfC1jh5EgfB LYIOTkz8L6FOZ4zABooq9xLbEWRmuxSxAN/L3IWMhtLsrhrPAwaWpTs8nWQcINQXjzIW Th3Ox3SxRn2NB1O5O1i7dvSzjReW0lT0e0NXCBJyAY7uZv5CBEQPFfytOwyLFT6+GbdD 0Muyl0wFGDXOBF3J84+4+fR6KIh+LwFij6iFcIuNTysynef6AVE2ZHVy+7hryftNYOQN eXbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769677873; x=1770282673; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=nayUkHKP6L91MLG9SEcHVEuSxFmIGO+/zRwcQEweek0=; b=O1T7zCkJSYfsDD/1+F356zbx/VYq6g3KLkp3dIi6eNCAuxF2ReG2YYIjBOE348Mqmt Z9vCX7O6/fJYE76F5PiQxnLPkLK8UuoFrjwW8jkTsyUKH0c+kwAW/Mrw3Pj43nDiaFzE Bo757x1rb6iygfgvp6NTpGKIgINdl4N9JimbO4oLl/G8CIfKk+EsQEhnt/GkQAvx1bvr a9oVqhSDzTMCDc/gdC+yRkbhNyhSc8AntHZdyomGN5OLIc4/WC8wQzqwIgiUe5svhkFC JqkGI4uP2nm3Z80rpjYX98v6MaI1IEy2eTJ50Fg4XvliQJoVjOuWOORm2lNFmzysh7ER A9mw== X-Forwarded-Encrypted: i=1; AJvYcCWy/E+3YzYeMe8apU2i8uMsquRo63GazCIfdEPK1JYhsYNKl7M7BUopTr1EKezIppWGgexxrSohv1GP3FU=@vger.kernel.org X-Gm-Message-State: AOJu0YxEvFW562BNGZC7uKaQB1EluTocsTPwkOptVtPP57ri4Ne/mHyO I0Uka5dOBNIdajuYUnVNKCJ9l2+dWAymY2ZPAnFJ9tRGSpsNoeoMjUqi X-Gm-Gg: AZuq6aKPkBWB8QV+OLCwqNf8ob9RmXq1fLnZ8hCFriFRLvVVHWuQcldfIBxe3OIfXgb R60iBtqFcOpLPwtAvmebYqOW3Pz7n6Mfj+6jTh+PFQBsSIzXccKvQ5tABcL8vi+CMItQZ/3XH2B mp2qWk7Md6J4IkSPCgGX8aSDdnugJALPYPfFS2ZgASKROV69hP1HXN4en4Fqdc8tM5tWEvB2xGb 6PW3nrKIzMsoYkVmLjRVENNcCSiPNJ1KFRUFzakT52UsWjcMUU8e9EEiICGDX/PZ7HUXfJrL9Nh abtrf6c1koPelpElf0AwFOOTFNxawUH7IcwC20tABzaR9R5giThkAUCWotfVlqWudAbztQqT3HU jdpyycc5f+6b2Mm0k7fHqlHwg2WC5vtGzuvpTSRlSwi0yTffEHlDGJ65O3ze8ivBSu7B7KDEBDG He7NPYBc69+ulOyzVV X-Received: by 2002:a05:600c:6812:b0:477:afc5:fb02 with SMTP id 5b1f17b1804b1-48069c47cb8mr94006635e9.21.1769677872922; Thu, 29 Jan 2026 01:11:12 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:5792:2065:403:a80b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066be77b5sm175338875e9.2.2026.01.29.01.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 01:11:12 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 4/9] pinctrl: renesas: rzg2l: Add support for selecting power source for {WDT,AWO,ISO} Date: Thu, 29 Jan 2026 09:10:55 +0000 Message-ID: <20260129091108.95277-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> References: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3L SoC has support for setting power source that are not controlled by the following voltage control registers: - SD_CH{0,1,2}_POC, XSPI_POC, ETH{0,1}_POC, I3C_SET.POC Add support for selecting voltages using OTHER_POC register for setting I/O domain voltage for WDT, ISO and AWO. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 40 +++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 863e779dda02..cf7f9c2e37f8 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -63,10 +63,18 @@ #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */ #define PIN_CFG_ELC BIT(17) #define PIN_CFG_IOLH_RZV2H BIT(18) +#define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */ +#define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ +#define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ =20 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ =20 +#define PIN_CFG_OTHER_POC_MASK \ + (PIN_CFG_PVDD1833_OTH_AWO_POC | \ + PIN_CFG_PVDD1833_OTH_ISO_POC | \ + PIN_CFG_WDTOVF_N_POC) + #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ PIN_CFG_PUPD | \ @@ -146,6 +154,7 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) +#define OTHER_POC (0x3028) /* known on RZ/G3L only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ @@ -906,6 +915,12 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_re= gister_offsets *regs, u32 return ETH_POC(regs->eth_poc, 1); if (caps & PIN_CFG_IO_VMC_QSPI) return QSPI; + if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC) + return OTHER_POC; + if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC) + return OTHER_POC; + if (caps & PIN_CFG_WDTOVF_N_POC) + return OTHER_POC; =20 return -EINVAL; } @@ -925,6 +940,13 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl= *pctrl, u32 pin, u32 caps return pwr_reg; =20 val =3D readb(pctrl->base + pwr_reg); + if (pwr_reg =3D=3D OTHER_POC) { + u32 poc =3D FIELD_GET(PIN_CFG_OTHER_POC_MASK, caps); + u8 offs =3D ffs(poc) - 1; + + val =3D (val >> offs) & 0x1; + } + switch (val) { case PVDD_1800: return 1800; @@ -943,6 +965,7 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl = *pctrl, u32 pin, u32 caps const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; int pwr_reg; + u8 poc_val; u8 val; =20 if (caps & PIN_CFG_SOFT_PS) { @@ -952,15 +975,15 @@ static int rzg2l_set_power_source(struct rzg2l_pinctr= l *pctrl, u32 pin, u32 caps =20 switch (ps) { case 1800: - val =3D PVDD_1800; + poc_val =3D PVDD_1800; break; case 2500: if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) return -EINVAL; - val =3D PVDD_2500; + poc_val =3D PVDD_2500; break; case 3300: - val =3D PVDD_3300; + poc_val =3D PVDD_3300; break; default: return -EINVAL; @@ -970,6 +993,17 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl= *pctrl, u32 pin, u32 caps if (pwr_reg < 0) return pwr_reg; =20 + if (pwr_reg =3D=3D OTHER_POC) { + u32 poc =3D FIELD_GET(PIN_CFG_OTHER_POC_MASK, caps); + u8 offs =3D ffs(poc) - 1; + + val =3D readb(pctrl->base + pwr_reg); + val &=3D ~BIT(offs); + val |=3D (poc_val << offs); + } else { + val =3D poc_val; + } + writeb(val, pctrl->base + pwr_reg); pctrl->settings[pin].power_source =3D ps; =20 --=20 2.43.0 From nobody Mon Feb 9 01:35:01 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 941CD37F0FD for ; Thu, 29 Jan 2026 09:11:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677877; cv=none; b=P+egOZNmtBsjSs8gh8ez+xCnBlHkfuoeCRO9T5/CtB7UVTtHHkHbW5iYzK4BzoYowFWmasb57HgKXkC37qPS5dXCaW0CkhfMeItzY75+yhfpsPbE4JpnFSXEZQco3Qor/M9d98vQv3YC/Cl25fE89ZIG4zDM8orR9PIHzJcsQmY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677877; c=relaxed/simple; bh=9736Q1c5UPkbPCgTxA+3Cri6nfDIyGp2aLifbmZ9cpk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eqJgmrV7Gs8Yj5rrqMqvEMuCyOS6Iy4iiaK83pEdZit7V8Pdw5pHDEGrzofrCLKW9Sct+4Gcyub3bkGIbTF2JIs75r7ceTBq9hXKwujKm877Ry7AGs5RYk39/Wg2irMc1OaHPDidR+scD9r4g+XNTu/BtEK5xhBBkbMLPGP5aPM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=QqidqTCx; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QqidqTCx" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-48068ed1eccso6702925e9.2 for ; Thu, 29 Jan 2026 01:11:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769677874; x=1770282674; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pNHC7BZwLEWIAkvOqNMf9oTfVeweCY3nyHbRwQRrLe0=; b=QqidqTCxEAA4I+p1Y9Gjs+uTCmxID7oiiYScwmgYJY9vZBNLSE2xtEOlkqlzESVXUd 6GUp+6UlFAR4+ui6xfIy4qh83k8Hg8rpXcz5lU/LfFgmeP9zrfzzL37kbNI4/3WZ6ZOJ dwmsjqT7VutBSwrZU4TZRdOhC5KWtjVf/aiVOVjQDbv6sQTe0H5yTpG3BL2nHsG+vJNe 6ol74HCrH1VWySMitvDnduOuxenokU+bvliMIsMqLgZIaBMrCHilceonPCbf8BfEda6n JX+2rviTNA98XtVrX1swefeVjFLFl2MSu3z22JM9hEHwYAGGGKOb92dknSvrcaeo4prO sqKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769677874; x=1770282674; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=pNHC7BZwLEWIAkvOqNMf9oTfVeweCY3nyHbRwQRrLe0=; b=Ud+enk0txqlM/A+Kk86ffMMRCafGbaEkzb8xX/YXt0SOSQ+Viwb0qBsTv87MNCZeJL oxlFTpyaionR8aFF6+U3t1Za2mAXTQRdu0ngJK4SS/gN2AANvu1QR+Peb2480O34X3Dc //yonwgQ65xr9m3XyJnxIppwC9BQNA83z/fQGg+doCvFR7seeMxbtiu3ueJdykd64soC S/hc2UsoZxSLq5HVt8KD4AboIbucdCNz0h0Sl9aiPr3G4rICLd2FqUbwFErArDcKkM8+ /KjXaOIdmjuJN4fV1g8rzzFC5gyly3fYyNDB6AzaD6rNq25PBNfz7wo89ZmpzjyIuun/ IwDg== X-Forwarded-Encrypted: i=1; AJvYcCUs7IKb3W3B2szNcczGK/dBYF7MiQoXX/LoanQEa+10oUgwehdQF5jAUBKywl7xTcMgOSyQhSAIk13WjsE=@vger.kernel.org X-Gm-Message-State: AOJu0YzQRJwZpWmtjz9lwlU9lltb+AnTDwGF6aNCP1WWEP2xbhlyeoOp Etmik4BQr3ySliNazKVwOk4tfrFYNoWrPV2HXz7Pdz2LU9SCLYr2YRfOonrJqQ== X-Gm-Gg: AZuq6aK8rXR6B3QPsQZqA6++KZmjA2+cS7LXgyzL9K18Hdxi45MhJ3cZfbsT121J5DO hOIJqIqX4ocVJSGTrEvQzTOdK0e6+LjvK7kfAdoh6uMCXYzTbqCVgsQGDak/CFlZwicUH1532aV 1qhOc+6Hs78OLanlk0QWZhhJneyNUwZZaPGiWbpU3zdiCD7X32pNuoqIoiumU35t94tAdNJsF4F KdzOuxZ2+lLuTrYKodxkCUSKDX1PrAbRloQFIpCA/CuFIKcHFYjYdnRXcfnp4LJiDtgQESMP2S1 lOVj+LNMERgAQar7QXle2hRLPhWX601TvFm1nswW8C+Ce22PAGBBv3UzjaDCjVEzjD6QRrGGddW P8CAjAS3wtVzSwV7oMTetFEzHk5zlLIPq8Px87qU5UyclsnvF04T/8IDFjbkJtHhtm8/EEULFVn x1cfUy8+fmE56rXqrH X-Received: by 2002:a05:600c:5395:b0:477:c478:46d7 with SMTP id 5b1f17b1804b1-48069c55751mr102965605e9.22.1769677873398; Thu, 29 Jan 2026 01:11:13 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:5792:2065:403:a80b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066be77b5sm175338875e9.2.2026.01.29.01.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 01:11:13 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 5/9] pinctrl: renesas: rzg2l: Add OEN support for RZ/G3L Date: Thu, 29 Jan 2026 09:10:56 +0000 Message-ID: <20260129091108.95277-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> References: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for configuring the ETH_MODE register on the RZ/G3L SoC to enable output-enable control for specific pins. On this SoC, certain pins such as P{B,E}1_ISO need to support switching between input and output modes depending on the PHY interface mode (e.g., RMII vs RGMII). This functionality maps to the 'output-enable' property in the device tree and requires explicit control via the ETH_MODE register. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index cf7f9c2e37f8..5e3e56e32cea 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1198,6 +1198,23 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin, u8 oe return 0; } =20 +static int rzg3l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) +{ + u64 *pin_data =3D pctrl->desc.pins[_pin].drv_data; + u8 port, pin; + + if (*pin_data & RZG2L_SINGLE_PIN) + return -EINVAL; + + pin =3D RZG2L_PIN_ID_TO_PIN(_pin); + if (pin !=3D pctrl->data->hwcfg->oen_max_pin) + return -EINVAL; + + port =3D RZG2L_PIN_ID_TO_PORT(_pin); + + return (port =3D=3D pctrl->data->hwcfg->oen_max_port) ? 1 : 0; +} + static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) { u64 *pin_data =3D pctrl->desc.pins[_pin].drv_data; --=20 2.43.0 From nobody Mon Feb 9 01:35:01 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48F8B37F116 for ; Thu, 29 Jan 2026 09:11:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677879; cv=none; b=Un5/KJCW1EbUlo7KQHHbpj6FYDMRBYaNq+iYZUN/manP4kVXBiBqqG0RuJQLFx5x0UsLjYep8V6yaPctpCayhneaD8clpTKn0C2N14KKU9/qajVZw2I5jme/WmFV9Z9F/wPzkuO8j+muXEFj272Si9XH2woRiLZeoKcSoO9QI8Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677879; c=relaxed/simple; bh=clZzrs0xiHiuryZmmiswKWziwPY99rU9AuPvqtXxfmc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RxnrZy2GKWSM2NOG7VoXOJjJ+cSorzgNBVSM/gQvFQazTUOA1HmstfXuKjMmJPBRqhMaGpFnm3qU8B2vvCNx42xaffdvXsLZBrcMBXXUqSB4jo5OyafIO0yez/T1sPMCu8oW7AQsyPtTWRYodVYoNgGqf/Z1hZm+srhEaQqjftc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Eq+L8Q6a; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Eq+L8Q6a" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-47fedb7c68dso6903615e9.2 for ; Thu, 29 Jan 2026 01:11:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769677874; x=1770282674; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M9Q0bB59x9gNqAfAEZotgxiHV1QyCskKWM3iqLx4w7w=; b=Eq+L8Q6anAONgU0BQbkcvfvVaKzHfjCjUSSrcOb/sl3kc6TJO3463f3G2BA2QwxuH4 hSiCoUEGlz4reCtq06dre/kcu6xTSbhVkIVHNY8XVnlnjQngREdRmXtUAJ3VSk2usPkG 2eTpQqQmmn6RZy0KGaj6fpgc5ZCr/9DUjOE5cBSvznevxjbYoeTd/weaRO13wlULyVwg BQxQ8cH6+pTU3IEdftY1Iez/kZHaCkXNqMQRXDZBsQFHsMYNW4WmTMkEOSafMd8lRhD5 etQkWO4syacfEhE64+ulu84tvIxz2V0VJd7Ha29SYP24sx4rytjLtQyr9oXcaJ1gImnv +ktg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769677874; x=1770282674; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=M9Q0bB59x9gNqAfAEZotgxiHV1QyCskKWM3iqLx4w7w=; b=gPghpqrC8lGKzZrpDk03blU3vYjP161b/F9r3v3acdwiX0OJvg0jJFtVuqDgIvTMQs uCtJz/FIOLrI9MgiTIZgBBGHseVuehWiGtN1nmOKNI8GCAZskxhf+hwlfrRCcLwHGuE9 L70xfFa1mQphYWv6Zop6/ByLmtcWYK2Ej/p53kYTzm3183l5sssQQPgtsYIDrhdl7osX Q+tzNiwcCXKTLBnsmAK95TUfrzymtgJJIXcl6oNLarI2lB23qz26KwrE1ahnvXsJjGn7 bdf3W9eYwSi1W5ddkGNGoFl3Gyx9BnIqphlnsyogosL7VjkKWC4JZPDBLsQguFoyGwla DElQ== X-Forwarded-Encrypted: i=1; AJvYcCWyVSeoduc/cqIwUPKxDXjCRd2mEz3IIS6P6M+3MFQKNaSPtFzhZM4iSGx52xWoPSYr0bm+vxgU/hxQmX0=@vger.kernel.org X-Gm-Message-State: AOJu0Yz9zEZvekIKW8XbluG/1LIX8NJRF4W7zok6GtGp59NC5rk6REOH LK77EKZbd65xkNjIE41RtnfimLXYuc++PVVcOojpsMsjL1FXpH9otOhF X-Gm-Gg: AZuq6aLErFQ/KzCQGDU77PCZtPDyrPBuFy9YzYdR2DYQSWQiQYUFy04lAItsoKbpjIz KIWeNDR2WhVnJa7OjVn8Zho5/mzLHPtkKZRIwSqnDzvx0TiGNnYvpNWy2r9mY42UVTgPUADSTFd NEEpRK2v/5SEme2mx5pQaPQTSKKARmpJet0uLz5LhPAH+L8M3JBrXRhRF0+kzqv+OWNZxR1Nkgb h7zlg6w3r9XcDA/Wb8nHGcdLm6yh8/vu9Cr8/7KAyMBpzC+n2oUNiDZVclwPcNWZZuU/1wGOUrE 26WLYmdGQz6AniMskg+Ta2nvMJLK3jyRhsagoyyLI/Q4H4CZoHSef+th0tuhTrmmoVm9kEGyZEV TdaHvuDbzOzhxr1XqYuxwrqgRRWrWsCf/g+jOSPByRz2Y04TJLexVXnRzWWDWzOEKg3Ol6PPIMs Ik6R6bkpS1eyDqTCAy X-Received: by 2002:a05:600c:1e1c:b0:479:2f95:5179 with SMTP id 5b1f17b1804b1-48069c161d3mr102454155e9.15.1769677874065; Thu, 29 Jan 2026 01:11:14 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:5792:2065:403:a80b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066be77b5sm175338875e9.2.2026.01.29.01.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 01:11:13 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij , Magnus Damm Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 6/9] pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC Date: Thu, 29 Jan 2026 09:10:57 +0000 Message-ID: <20260129091108.95277-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> References: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add pinctrl driver support for RZ/G3L SoC. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 228 ++++++++++++++++++++++++ 1 file changed, 228 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 5e3e56e32cea..e45282afcf86 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -26,6 +26,7 @@ #include #include =20 +#include #include #include #include @@ -93,6 +94,17 @@ =20 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF) =20 +#define RZG3L_MPXED_ETH_PIN_FUNCS(ether) \ + (PIN_CFG_IO_VMC_##ether | \ + PIN_CFG_IOLH_C | \ + PIN_CFG_NF) + +#define RZG3L_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) = | \ + PIN_CFG_SOFT_PS) + +#define RZG3L_MPXED_PIN_FUNCS_POC(grp, poc) (RZG3L_MPXED_PIN_FUNCS(grp) | \ + PIN_CFG_PVDD1833_OTH_##poc##_POC) + #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54) #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46) #define PIN_CFG_MASK GENMASK_ULL(31, 0) @@ -229,12 +241,14 @@ static const struct pin_config_item renesas_rzv2h_con= f_items[] =3D { * @sd_ch: SD_CH register offset * @eth_poc: ETH_POC register offset * @oen: OEN register offset + * @other_poc: OTHER_POC register offset */ struct rzg2l_register_offsets { u16 pwpr; u16 sd_ch; u16 eth_poc; u16 oen; + u16 other_poc; }; =20 /** @@ -333,6 +347,7 @@ struct rzg2l_pinctrl_pin_settings { * @smt: SMT registers cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache + * @other_poc: OTHER_POC register cache * @oen: Output Enable register cache * @qspi: QSPI registers cache */ @@ -348,6 +363,7 @@ struct rzg2l_pinctrl_reg_cache { u8 sd_ch[2]; u8 eth_poc[2]; u8 oen; + u8 other_poc; u8 qspi; }; =20 @@ -397,6 +413,60 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct r= zg2l_pinctrl *pctrl, return 0; } =20 +static const u64 r9a08g046_variable_pin_cfg[] =3D { + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) = | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) = | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) = | PIN_CFG_OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) = | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) = | PIN_CFG_OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG3L_MPXED_PIN_FUNCS(B)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 6, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO= )), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 7, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO= )), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG3L_MPXED_PIN_FUNCS(B)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 0, RZG3L_MPXED_PIN_FUNCS(A) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 1, RZG3L_MPXED_PIN_FUNCS(A)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 2, RZG3L_MPXED_PIN_FUNCS(A)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 3, RZG3L_MPXED_PIN_FUNCS(A)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 4, RZG3L_MPXED_PIN_FUNCS(A)), +}; + static const u64 r9a09g047_variable_pin_cfg[] =3D { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= IEN), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS), @@ -2141,6 +2211,70 @@ static const u64 r9a09g047_gpio_configs[] =3D { RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */ }; =20 +static const char * const rzg3l_gpio_names[] =3D { + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", + "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", + "", "", "", "", "", "", "", "", + "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", + "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", + "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", + "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", + "", "", "", "", "", "", "", "", + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", + "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", + "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", + "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", + "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7", + "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7", + "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", + "", "", "", "", "", "", "", "", + "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", + "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7", + "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7", + "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7", +}; + +static const u64 r9a08g046_gpio_configs[] =3D { + 0x0, + 0x0, + RZG2L_GPIO_PORT_PACK(2, 0x22, PIN_CFG_NF | PIN_CFG_IEN), /* P2 */ + RZG2L_GPIO_PORT_PACK(7, 0x23, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P3 */ + 0x0, + RZG2L_GPIO_PORT_PACK(7, 0x25, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P5 */ + RZG2L_GPIO_PORT_PACK(7, 0x26, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P6 */ + RZG2L_GPIO_PORT_PACK(8, 0x27, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P7 */ + RZG2L_GPIO_PORT_PACK(6, 0x28, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P8 */ + 0x0, + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */ + RZG2L_GPIO_PORT_PACK(3, 0x2c, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), /* PC */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */ + RZG2L_GPIO_PORT_PACK(3, 0x2f, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), /* PF */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ + RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ + 0x0, + RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ + RZG2L_GPIO_PORT_PACK(4, 0x34, RZG3L_MPXED_PIN_FUNCS_POC(B, AWO)), /* PK */ + RZG2L_GPIO_PORT_PACK(5, 0x35, RZG3L_MPXED_PIN_FUNCS(C)), /* PL */ + RZG2L_GPIO_PORT_PACK(8, 0x36, RZG3L_MPXED_PIN_FUNCS(C)), /* PM */ + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + RZG2L_GPIO_PORT_PACK(2, 0x3c, RZG3L_MPXED_PIN_FUNCS(A)), /* PS */ +}; + static const char * const rzv2h_gpio_names[] =3D { "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", @@ -2479,6 +2613,37 @@ static struct rzg2l_dedicated_configs rzg3e_dedicate= d_pins[] =3D { (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, }; =20 +static const struct rzg2l_dedicated_configs rzg3l_dedicated_pins[] =3D { + { "WDTOVF_N", RZG2L_SINGLE_PIN_PACK(0x5, 0, + (PIN_CFG_IOLH_A | PIN_CFG_WDTOVF_N_POC)) }, + { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, + (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, + { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, + (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B) }, + { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B) }, + { "SD0_DS", RZG2L_SINGLE_PIN_PACK(0x9, 5, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x0a, 0, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x0a, 1, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x0a, 2, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x0a, 3, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x0a, 4, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x0a, 5, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x0a, 6, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x0a, 7, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, +}; + static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl = *pctrl) { const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[virq]; @@ -3007,6 +3172,9 @@ static int rzg2l_pinctrl_probe(struct platform_device= *pdev) BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg2l_gpio_names)); =20 + BUILD_BUG_ON(ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg3l_gpio_names)); + BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg3e_gpio_names)); =20 @@ -3254,6 +3422,8 @@ static int rzg2l_pinctrl_suspend_noirq(struct device = *dev) =20 cache->qspi =3D readb(pctrl->base + QSPI); cache->oen =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); + if (regs->other_poc) + cache->other_poc =3D readb(pctrl->base + regs->other_poc); =20 if (!atomic_read(&pctrl->wakeup_path)) clk_disable_unprepare(pctrl->clk); @@ -3279,6 +3449,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) } =20 writeb(cache->qspi, pctrl->base + QSPI); + if (regs->other_poc) + writeb(cache->other_poc, pctrl->base + regs->other_poc); =20 raw_spin_lock_irqsave(&pctrl->lock, flags); rzg2l_oen_write_with_pwpr(pctrl, cache->oen); @@ -3380,6 +3552,41 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { .oen_max_port =3D 7, /* P7_1 is the maximum OEN port. */ }; =20 +static const struct rzg2l_hwcfg rzg3l_hwcfg =3D { + .regs =3D { + .pwpr =3D 0x3000, + .sd_ch =3D 0x3004, + .eth_poc =3D 0x3010, + .oen =3D 0x3018, + .other_poc =3D 0x3028, + }, + .iolh_groupa_ua =3D { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] =3D 2200, 4400, 9000, 10000, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] =3D 1900, 4000, 8000, 9000, + }, + .iolh_groupb_ua =3D { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] =3D 7000, 8000, 9000, 10000, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] =3D 4000, 6000, 8000, 9000, + }, + .iolh_groupc_ua =3D { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] =3D 5200, 6000, 6550, 6800, + /* 2v5 source */ + [RZG2L_IOLH_IDX_2V5] =3D 4700, 5300, 5800, 6100, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] =3D 4500, 5200, 5700, 6050, + }, + .tint_start_index =3D 17, + .drive_strength_ua =3D true, + .func_base =3D 0, + .oen_max_pin =3D 1, /* Pin 1 of PE1_ISO is the maximum OEN pin. */ + .oen_max_port =3D 14, /* PE1_ISO is the maximum OEN port. */ +}; + static const struct rzg2l_hwcfg rzv2h_hwcfg =3D { .regs =3D { .pwpr =3D 0x3c04, @@ -3439,6 +3646,23 @@ static struct rzg2l_pinctrl_data r9a08g045_data =3D { .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, }; =20 +static struct rzg2l_pinctrl_data r9a08g046_data =3D { + .port_pins =3D rzg3l_gpio_names, + .port_pin_configs =3D r9a08g046_gpio_configs, + .n_ports =3D ARRAY_SIZE(r9a08g046_gpio_configs), + .variable_pin_cfg =3D r9a08g046_variable_pin_cfg, + .n_variable_pin_cfg =3D ARRAY_SIZE(r9a08g046_variable_pin_cfg), + .dedicated_pins =3D rzg3l_dedicated_pins, + .n_port_pins =3D ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins =3D ARRAY_SIZE(rzg3l_dedicated_pins), + .hwcfg =3D &rzg3l_hwcfg, + .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, + .pmc_writeb =3D &rzg2l_pmc_writeb, + .pin_to_oen_bit =3D &rzg3l_pin_to_oen_bit, + .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, + .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, +}; + static struct rzg2l_pinctrl_data r9a09g047_data =3D { .port_pins =3D rzg3e_gpio_names, .port_pin_configs =3D r9a09g047_gpio_configs, @@ -3519,6 +3743,10 @@ static const struct of_device_id rzg2l_pinctrl_of_ta= ble[] =3D { .compatible =3D "renesas,r9a08g045-pinctrl", .data =3D &r9a08g045_data, }, + { + .compatible =3D "renesas,r9a08g046-pinctrl", + .data =3D &r9a08g046_data, + }, { .compatible =3D "renesas,r9a09g047-pinctrl", .data =3D &r9a09g047_data, --=20 2.43.0 From nobody Mon Feb 9 01:35:01 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C32D376BED for ; Thu, 29 Jan 2026 09:11:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677879; cv=none; b=im6vkkF+a9U8xm0I3mTlg97LdKF/sN3sdL7jp6a9wgcBCrv6Gg7ehVYKDWCzofXbD+PIEdl8sSQTVKGNouTAM9zBpQN1c8LFvM9cXD36iLGHoUI+Ul/jyxa4d7tyhEZmr/jbRJLNMh+qjRbzWOggS+hAEZi2/gPJrxaOVOCDijQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677879; c=relaxed/simple; bh=v6FdTaM3/9S+cgZOR/jP9oZ2cYA4WGpZsxblMxIWwD4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aZRR/4TRXTiHHK/W9DE6MUblTcRrlFprXoF0KdGDCoJ3ggSQbG6lW1X35YYY+6Qz5d3iXvDWGVgi09iqKPODnA96QhxRXhNNZob+aJeCFf41lg1GbMhIEXrbvGXQKoiAm+LsMliKo8Jyp0lTphrpM96Qi+NyBXrSRobUibc9mAc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ekFCyuJ1; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ekFCyuJ1" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-47ee937ecf2so5796025e9.0 for ; Thu, 29 Jan 2026 01:11:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769677875; x=1770282675; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yxb+xzLrz5vUgOO6D/hBhQgk8cWp111oMhH2v5GHUEo=; b=ekFCyuJ1gP/PZsf61ep3ZZVggHI6M10J8OD5qdyjoXM4wppazlMHknJUMbX6hGozdF ixAgMLtaHUKv9L6+18qSBWk74GYKtIa0iA9m1qzxs7yy9ZNT1SlqztvKNwUWxJdlZVb9 0BZUetnbFcwg7g3qBr02Gfk7UcDGOvQeoIP6dAkCRRjO6k/SfUrNxiHk+CAWO2q69Kvr Ju0AkIJpsDqXlQgbjNoXIqPrggd5Nj8Kd+8OW2PZFIAgIr9w8zLA9ThdbWhNQtaXidvv h/7Z9qVyPGxV+Q9XGMXzs9MYfC23zChUyqWZMWMOfnoBSiMwruEFheMgC0TApNkfTeUY P3bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769677875; x=1770282675; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=yxb+xzLrz5vUgOO6D/hBhQgk8cWp111oMhH2v5GHUEo=; b=OiFqflrmpF1kYd+mV2AuwOaBnXSoXmqv8PW3k6LWDE9NayMrswCF/W40PeTdHAOX/Z CrqQkxthWgMeKXb/BuUTrEeHm0smKO7kD46Iifzj155rNjegmxbBxRfzNBs+NLXYyyV3 sTNtLkqFb5tYKPJOxwfXnnhXnwx/tEzXDDgn0ovLg6a9PnRQbYoGHVx9Vb3l/RqSRBHg r3vNlGF6+uhFcLeBrpTBSLrxc4DZkko5qQJhRLwQcvsJql4OVhh6j91yO+iGLEHIv28o 0A+xdwrAk9TfLwuLVIps2YEJbSchcUS9Dp17z3gBNuR0hDrUQ1JB0dlqtqNh8uhm2DJE 9HaQ== X-Forwarded-Encrypted: i=1; AJvYcCV0DbhX1nSxWXdrWC2SuPxE7OnmnWPrV6tVu+J9yQDlPVsNri63AJJJSuDdnUgHufKQSCUcFr0uvpRH+LI=@vger.kernel.org X-Gm-Message-State: AOJu0YyoEHndiFFFeRjP0agnOANFjpSjb0jfz6ylbQyjP7AYGegwwdno DKrodYImHBeyZ82sMn5LcCs05y7dG5RXkgSUUPBSe3Sj6W8W3SIZk44S X-Gm-Gg: AZuq6aJiXLPweaPLLsZKhPmEd79c2a3ZBj5gpAqoNQ3meyfDIGUi8xy30CgE5i4iZET 3iquX8KruxkGRiRZsYJs3MEc3O6U8DSIFeZlXjdVQQNryKxoBF4SghzGwx/2yssFTQQi9osS+Nq kAAcL0kXfB0FXEWiDfmHTpCqFjExy4KYmH71x0hg+5VZwC/ZE5QP6WbJEOi8+xmlYXfCFnFZD3A famrqmZXz1UVrl26oWQnz0VyzFw3VtvJ+UjXQkIIQCNkm0nn78Vm7nFK9LtiDy05MPSu2rqEssj u5q4sjPFVLkOIdZfGZnIdgOQakzhvIFoo45zKT+bQLAjM/2BLcxv1X0nNnu9dDGQYO0shTu53kx yuXtfFF4VESmlFejpewZ5FN8uufw/IPNIAL8MXWDfttl1c4jAR14UTiUGcPTTPAVwZhTo/wz2La 5sQuKoW+YTT0sOA2fy X-Received: by 2002:a05:600c:1d1d:b0:477:9e0c:f59 with SMTP id 5b1f17b1804b1-48082891d58mr31641625e9.2.1769677874568; Thu, 29 Jan 2026 01:11:14 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:5792:2065:403:a80b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066be77b5sm175338875e9.2.2026.01.29.01.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 01:11:14 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 7/9] arm64: dts: renesas: r9a08g046: Add pincontrol node Date: Thu, 29 Jan 2026 09:10:58 +0000 Message-ID: <20260129091108.95277-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> References: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add pincontrol node to RZ/G3L ("R9A08G046") SoC DTSI. Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi index 231b118ecc62..c6b042ac9c36 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -181,9 +181,19 @@ sysc: system-controller@11020000 { }; =20 pinctrl: pinctrl@11030000 { + compatible =3D "renesas,r9a08g046-pinctrl"; reg =3D <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 0 232>; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&cpg CPG_MOD R9A08G046_GPIO_HCLK>; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G046_GPIO_RSTN>, + <&cpg R9A08G046_GPIO_PORT_RESETN>, + <&cpg R9A08G046_GPIO_SPARE_RESETN>; + reset-names =3D "rstn", "port", "spare"; }; =20 dmac: dma-controller@11820000 { --=20 2.43.0 From nobody Mon Feb 9 01:35:01 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E22937B3ED for ; Thu, 29 Jan 2026 09:11:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677879; cv=none; b=G32HobjNHX3YhZW3kvCg/SuNofNiTQabdTEkAwuJc8ffIzB0ugG4hQfLwV8i79a4OdxohK0viAOZ4lUm/Q342ZULm1DhareYrxP19nabZKaZNUJ/OpHd2FUahN3vsFaqsKdvqUfiJzAVUPUWZ7rKFGZe9dX/ELHJqRk6A0ZXNtE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677879; c=relaxed/simple; bh=l53JAl1A5TRe2s7pqTepmBMNLndaNxM1i2f8fJ+CJTQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mr7MlTblLWKWVTtGJPiOSm00HAUa9g0j6YMK9KhIcjAQHYQ3432NtXp7BLAT1Nrey740mbfWYvzXVs7rrm8mTZbwOjUWATqBTcraO2Pq0h9u6QDCA84m3vNCP3HSz934DRPz2mxXKVJ7GLen1ZzGp+taqP5BiQtax+qxhOwXQm8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NtpTDgsS; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NtpTDgsS" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-47edd9024b1so5644615e9.3 for ; Thu, 29 Jan 2026 01:11:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769677875; x=1770282675; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kt7uEiXTlV6e7nA3ca7sq5Y8eWxdpRVOenYUuxl1aik=; b=NtpTDgsSJA3amImCWdi16FNcBLuT4nXqexsIOau2mz+lUE0lkUWIJg9Qg3UO65gQez kBI9n4JYAYb/EcpvmKBOS+I57U39vREl5P3sFGCJNVk2npi5dNyaF5RWW6L86CUxe0eR uc44wYMLjIhdQ7WZUr2jZaI3td9cg2VlxnXl59l1+s/RtCrkSimWCRiMUpiFqAhjJbbf IX0mqQWEMvYIeudyerdZmQkGMpUpKft0WeVSHSEGzYV9+mfDX7iSEV9U0GisybnvBv2u v7Y4SzTsxqP1ytvbA9S/UYWnRlZYxLRkG59POsWee/AWsNjX4AoeOSUtH9fZluPVNLgy tocw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769677875; x=1770282675; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Kt7uEiXTlV6e7nA3ca7sq5Y8eWxdpRVOenYUuxl1aik=; b=Ac8lNa4a81Gagc9qpXrP1+dME5XlL4gbh4Tp0sNcc+csGbBgoBdgbsQNh6g9ZkyFc5 xuOP8A26T36odvVJrQsRDraM94XTH7mSnuEoylXDm3jQdRP81ABr9rfO7LO9LOcn1u+R XPi/VtJD2zSBgegmiQec5JVxIsQWVnggg7SZ9qm9RS+GF/WRE9aTKjGkzeb57ZtjVFi2 zayRCfBWYSyUX2DP2AILe+SMY0iVyYdCkc+tG3pQ1BOqI7G4LRoYcB1/kCd6C3tdKV4y o81QqDAMw0yT7lkIbOCTcPUjHIUTqZhUx9hcKypPPv2M5rWQui8cRpgeDNXxU56/2yHL IOXg== X-Forwarded-Encrypted: i=1; AJvYcCWnZ/eSvqijcXvI209s5In0oCwyheOsExgHJSX41+U9j3Z4TZl+qI3VRtZJsfEjyRXK6z7nQhk30ZHUD7k=@vger.kernel.org X-Gm-Message-State: AOJu0Yw0kRhZhcwWW7IEiDAGBQgCHvVUtwhLUd4IBOcPHO7FKBjzIit8 ukCKuIjUYqddopMFFKYO+dMINEdaETI9Dz2uC1betPTR/41BBko2plhs07XDzg== X-Gm-Gg: AZuq6aJFZMp7WxTLYLPhY23w8M1Ht04w4CxkoeGwS5I4Bza4JdjqU7QUQXJmxjXayGb yekiKpPojKC0xBFFvJYfxn/UHxm5yAzfKjkFWpHtniTIUkokm67OjVQPmzxpefN/RlLLHHRx8rS 4utEozUNduE1Og3fXvbZIFFyw5s6l9lSP1XA5bpxYF2AnLGs3T6Rajp1czUvu9oKlpQ4fAve3Os K4NmWE06nCk60AuiJ5YWdsO0OmIztooM3aSyoys1Qyskhd3rtDyicd3+zETCzgtiKaEjtoazcJE CR9p7VAHqi4e2Z0qfkEqk54BElc5Se2Ox9pooDNSuzrYozmGVvrwClCmdrtWlsuQjsmtDvcttog z8joV9wEqUHHx89qs8gubzlwSgzSCFJlwVTU0GGt3M/Hmvte3w3Ym2S5sJY1nMGHIwBoXd743X8 W1uk4+9ZgfAHlD8drD X-Received: by 2002:a05:600c:4fd4:b0:47e:e807:a05a with SMTP id 5b1f17b1804b1-48069c98d9fmr93495945e9.33.1769677875090; Thu, 29 Jan 2026 01:11:15 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:5792:2065:403:a80b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066be77b5sm175338875e9.2.2026.01.29.01.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 01:11:14 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 8/9] arm64: dts: renesas: r9a08g046l48-smarc: Add SCIF0 pincontrol Date: Thu, 29 Jan 2026 09:10:59 +0000 Message-ID: <20260129091108.95277-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> References: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add device node for SCIF0 pincontrol. Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a08g046l48-smarc.dts index 86db86335d5e..2f918830b8f1 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -35,3 +35,15 @@ &keys { /delete-node/ key-2; /delete-node/ key-3; }; + +&pinctrl { + scif0_pins: scif0 { + pins =3D "SCIF_TXD", "SCIF_RXD"; + power-source =3D <1800>; + }; +}; + +&scif0 { + pinctrl-0 =3D <&scif0_pins>; + pinctrl-names =3D "default"; +}; --=20 2.43.0 From nobody Mon Feb 9 01:35:01 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53B3D37C0E3 for ; Thu, 29 Jan 2026 09:11:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677880; cv=none; b=qJ4wfbl+5zRy5ptOSNhQV2n8YUz0Ve9C2lgF7ErtukKxnvses66b48GDVG9OKqUR3Km4Mn0wmIgZqrzuAvDuETsC27Sp2bcN3N8+/lnAVfh2B2fdLCW56fRrc2itmnIGfETNcrJB1wc18agJI7tfJmoQm9RgAFSjELp5gHy9ZNE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769677880; c=relaxed/simple; bh=pqS0iTnZy+TD7iR+ETY3i6A5U7dU6kE1UlBEw/91Vl8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WALuEXDiQPENUoZOdLolJPs6jnZQrctVC/nwlhbSObFyYutp1CPwanAvQrPjl4rE6EzW+xNHBEeYkR8bQbQ9E78lq67E7j6n7l/Xy/HxVZgpTUtZWn9gwoiDcDPQbzLFpA8S+u33ssm2MG7fIlE9qiRBuA55SsGFWy4TF2an+ZA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=i7Q2H2FO; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="i7Q2H2FO" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4806f3fc50bso6883325e9.0 for ; Thu, 29 Jan 2026 01:11:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769677876; x=1770282676; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y9LVqcaf1ijJnoQzqgdsz1n58Lr+Jp/HnhYJrE/7aVo=; b=i7Q2H2FOJuJqQ6evr5ZAUmrWOPaWhS8LsPiJbe9SsPfIU9hnm+isrsvBeaeMs8FdQ4 ZtODem4Jcs/+SeuLhvt8mgaXvrwcP+TkN+pm0oYcTmW6OOrpgNC9o/rwr2H92CNhbtnY 47wt5VvZEnbR8EKbRh5yope1SiGqp7smrX9cqV/njgnaMGspWXzmmYsx+q+DWAEMsPfj 5j8uTqp8dm0CWEGojfTdAhLcPhaJW8ugUZw0QeQfV2ZTEyN+lZRRURuuBL89yj4oQ7MG S2FKbbXGGeUEtIqoI+GKZYtqeBl/G9Lup9uls7FdC6m88VR/IAZGs8LDS/qDC7Mbaz4D pSuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769677876; x=1770282676; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Y9LVqcaf1ijJnoQzqgdsz1n58Lr+Jp/HnhYJrE/7aVo=; b=UDoVM/3ICnj4Y1olnX7So0ng8yppVO/3nFzzUoaVy3WsDMmhanMGkvqd61+ggBxZJc BnLDllctwSLMoSeyo2L0z5xhXmJUohKH+lmRTcS2217d7x4wsmYgVdj9WwPp3Kfmz4+z EI7ZRLPCgx/ctDkGDkozfRPnaj3rmRS8rJWJLSXrl8qsfe8vxdJB5WNM2ZdUTzxC7uZq N6qCNwqPKxw2VqNLtmhdLttp9xUtS+SxBKL432wwvbu/kBGPccYwZCABkYLBAeKeYmze K1juapIEeyNFSbMAVUyQTiDAN6Pkjj6ALULhmP4QLTv5uToQ3tRVZ1DPlxtCz7k3rbU4 rowQ== X-Forwarded-Encrypted: i=1; AJvYcCX2O0lY2gUockdROic6g3NyTCMFLAKWa3WZFmx1SXIZcASKAYpO+4bTgSINDi8RF5wzwdAqpSti+zwbjwU=@vger.kernel.org X-Gm-Message-State: AOJu0YxEXMQMBmQypqgkBcPBq/gAt4CA4FFiJ6raqNZGs2FG9G8UmHeR knlQa4HSmlMDCQDbNDkC7KSl6HQu5wB2lMHGzZ2N4lQ7c07S+uFdU9pW X-Gm-Gg: AZuq6aJjNvYaXhs3IQNvacB6MLwQfjgnyEeKn0Nx36ARr8vUrZ03E9TX0u3gNRGpRfg SrkaTKuSSTWXIljNQGQ1+djMn/c2yNVDkSBQkk6tKSfTUWf3SASri6b9Cy6hGTdQtvGWZnS697w ot+1YaUa4W1yNkeXVfVYpj4IPwre7oZpm1M5qj0P0ufgpnqQSM7oN8wAKnSZRUhAsbTXZpa9DuQ HisGwpf0dPmXfrFNA3YSbzrI0Rx4ygZVgtDtGS9V84W3NUFSzzIvyf1z9/s1EP/GVmblsrPi4o0 6pqbMeHtnkNe/3MSSApVCYJu72xxNi3b/Timz7fVGr5HsszSkjaZ+h7dsHmLV+2vV/bt6I9O6ny B8RAGImo+oZCUbny+upaPgiClB6nOvrz/a7HXd2ZGaHuQ3glXpWFJVEYi4ESqCJjHe5G+1nAcqv btzXipQMQ4j0IPzG75 X-Received: by 2002:a05:600c:4f4f:b0:47e:e48b:506d with SMTP id 5b1f17b1804b1-4806c7cc86dmr103201195e9.16.1769677875603; Thu, 29 Jan 2026 01:11:15 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:5792:2065:403:a80b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066be77b5sm175338875e9.2.2026.01.29.01.11.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 01:11:15 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 9/9] arm64: dts: renesas: rzg3l-smarc-som: Enable eth1 (GBETH1) interface Date: Thu, 29 Jan 2026 09:11:00 +0000 Message-ID: <20260129091108.95277-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> References: <20260129091108.95277-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Enable the Gigabit Ethernet Interface (GBETH1) populated on the RZ/G3L SMARC EVK. Also add pincontrol definitions for GBETH{0,1}. Signed-off-by: Biju Das --- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 1 + .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 92 +++++++++++++++++++ 2 files changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a08g046l48-smarc.dts index 2f918830b8f1..58733016b66b 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -14,6 +14,7 @@ =20 #include #include +#include #include "r9a08g046l48.dtsi" #include "rzg3l-smarc-som.dtsi" #include "renesas-smarc2.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3l-smarc-som.dtsi index f52af01a7eff..0b9bb073c282 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -10,6 +10,7 @@ / { =20 aliases { ethernet0 =3D ð0; + ethernet1 =3D ð1; }; =20 memory@48000000 { @@ -23,6 +24,8 @@ ð0 { phy-handle =3D <&phy0>; phy-mode =3D "rgmii-id"; =20 + pinctrl-0 =3D <ð0_pins>; + pinctrl-names =3D "default"; status =3D "okay"; }; =20 @@ -30,6 +33,19 @@ ð0_rxc_rx_clk { clock-frequency =3D <125000000>; }; =20 +ð1 { + phy-handle =3D <&phy1>; + phy-mode =3D "rgmii-id"; + + pinctrl-0 =3D <ð1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +ð1_rxc_rx_clk { + clock-frequency =3D <125000000>; +}; + &extal_clk { clock-frequency =3D <24000000>; }; @@ -53,3 +69,79 @@ phy0: ethernet-phy@7 { txd3-skew-psec =3D <0>; }; }; + +&mdio1 { + phy1: ethernet-phy@7 { + compatible =3D "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + rxc-skew-psec =3D <1400>; + txc-skew-psec =3D <1400>; + rxdv-skew-psec =3D <0>; + txdv-skew-psec =3D <0>; + rxd0-skew-psec =3D <0>; + rxd1-skew-psec =3D <0>; + rxd2-skew-psec =3D <0>; + rxd3-skew-psec =3D <0>; + txd0-skew-psec =3D <0>; + txd1-skew-psec =3D <0>; + txd2-skew-psec =3D <0>; + txd3-skew-psec =3D <0>; + }; +}; + +&pinctrl { + eth0_pins: eth0 { + txc { + pinmux =3D ; /* ETH0_TXC_REF_CLK */ + power-source =3D <1800>; + output-enable; + drive-strength-microamp =3D <5200>; + }; + + ctrl { + pinmux =3D , /* MDC */ + , /* MDIO */ + , /* PHY_INTR */ + , /* RXD3 */ + , /* RXD2 */ + , /* RXD1 */ + , /* RXD0 */ + , /* RXC */ + , /* RX_CTL */ + , /* TXD3 */ + , /* TXD2 */ + , /* TXD1 */ + , /* TXD0 */ + ; /* TX_CTL */ + power-source =3D <1800>; + }; + }; + + eth1_pins: eth1 { + txc { + pinmux =3D ; /* ETH1_TXC_REF_CLK */ + power-source =3D <1800>; + output-enable; + drive-strength-microamp =3D <5200>; + }; + + ctrl { + pinmux =3D , /* MDC */ + , /* MDIO */ + , /* PHY_INTR */ + , /* RXD3 */ + , /* RXD2 */ + , /* RXD1 */ + , /* RXD0 */ + , /* RXC */ + , /* RX_CTL */ + , /* TXD3 */ + , /* TXD2 */ + , /* TXD1 */ + , /* TXD0 */ + ; /* TX_CTL */ + power-source =3D <1800>; + }; + }; +}; --=20 2.43.0