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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org Subject: [RFC net-next 2/4] net: dsa: yt921x: Refactor long register helpers Date: Thu, 29 Jan 2026 16:51:34 +0800 Message-ID: <20260129085139.2767649-3-mmyangfl@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260129085139.2767649-1-mmyangfl@gmail.com> References: <20260129085139.2767649-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dealing long registers with u64 is good, until you realize there are longer registers that are 96 bits. Use u32 arrays instead. Signed-off-by: David Yang --- drivers/net/dsa/yt921x.c | 152 +++++++++++++++++++++++++-------------- drivers/net/dsa/yt921x.h | 37 +++++----- 2 files changed, 116 insertions(+), 73 deletions(-) diff --git a/drivers/net/dsa/yt921x.c b/drivers/net/dsa/yt921x.c index 1b66b07f45b2..6d03888b6743 100644 --- a/drivers/net/dsa/yt921x.c +++ b/drivers/net/dsa/yt921x.c @@ -258,63 +258,102 @@ yt921x_reg_toggle_bits(struct yt921x_priv *priv, u32= reg, u32 mask, bool set) return yt921x_reg_update_bits(priv, reg, mask, !set ? 0 : mask); } =20 -/* Some registers, like VLANn_CTRL, should always be written in 64-bit, ev= en if - * you are to write only the lower / upper 32 bits. +/* Some registers, like VLANn_CTRL, should always be written in chunks, ev= en if + * you only want to write parts of 32 bits. * - * There is no such restriction for reading, but we still provide 64-bit r= ead - * wrappers so that we always handle u64 values. + * There is no such restriction for reading, but we still provide multi-ch= unk + * read wrappers so that we can handle them consistently. */ =20 -static int yt921x_reg64_read(struct yt921x_priv *priv, u32 reg, u64 *valp) +static int +yt921x_longreg_read(struct yt921x_priv *priv, u32 reg, u32 *vals, + unsigned int span) { - u32 lo; - u32 hi; int res; =20 - res =3D yt921x_reg_read(priv, reg, &lo); - if (res) - return res; - res =3D yt921x_reg_read(priv, reg + 4, &hi); - if (res) - return res; + for (unsigned int i =3D 0; i < span; i++) { + res =3D yt921x_reg_read(priv, reg + 4 * i, &vals[i]); + if (res) + return res; + } =20 - *valp =3D ((u64)hi << 32) | lo; return 0; } =20 -static int yt921x_reg64_write(struct yt921x_priv *priv, u32 reg, u64 val) +static int +yt921x_longreg_write(struct yt921x_priv *priv, u32 reg, const u32 *vals, + unsigned int span) { int res; =20 - res =3D yt921x_reg_write(priv, reg, (u32)val); - if (res) - return res; - return yt921x_reg_write(priv, reg + 4, (u32)(val >> 32)); + for (unsigned int i =3D 0; i < span; i++) { + res =3D yt921x_reg_write(priv, reg + 4 * i, vals[i]); + if (res) + return res; + } + + return 0; } =20 static int -yt921x_reg64_update_bits(struct yt921x_priv *priv, u32 reg, u64 mask, u64 = val) +yt921x_longreg_update_bits(struct yt921x_priv *priv, u32 reg, const u32 *m= asks, + const u32 *vals, unsigned int span) { + bool changed =3D false; + u32 vs[4]; int res; - u64 v; - u64 u; =20 - res =3D yt921x_reg64_read(priv, reg, &v); + BUILD_BUG_ON(span > ARRAY_SIZE(vs)); + + res =3D yt921x_longreg_read(priv, reg, vs, span); if (res) return res; =20 - u =3D v; - u &=3D ~mask; - u |=3D val; - if (u =3D=3D v) + for (unsigned int i =3D 0; i < span; i++) { + u32 u =3D vs[i]; + + u &=3D ~masks[i]; + u |=3D vals[i]; + if (u !=3D vs[i]) + changed =3D true; + + vs[i] =3D u; + } + + if (!changed) return 0; =20 - return yt921x_reg64_write(priv, reg, u); + return yt921x_longreg_write(priv, reg, vs, span); } =20 -static int yt921x_reg64_clear_bits(struct yt921x_priv *priv, u32 reg, u64 = mask) +static int +yt921x_longreg_clear_bits(struct yt921x_priv *priv, u32 reg, const u32 *ma= sks, + unsigned int span) { - return yt921x_reg64_update_bits(priv, reg, mask, 0); + bool changed =3D false; + u32 vs[4]; + int res; + + BUILD_BUG_ON(span > ARRAY_SIZE(vs)); + + res =3D yt921x_longreg_read(priv, reg, vs, span); + if (res) + return res; + + for (unsigned int i =3D 0; i < span; i++) { + u32 u =3D vs[i]; + + u &=3D ~masks[i]; + if (u !=3D vs[i]) + changed =3D true; + + vs[i] =3D u; + } + + if (!changed) + return 0; + + return yt921x_longreg_write(priv, reg, vs, span); } =20 static int yt921x_reg_mdio_read(void *context, u32 reg, u32 *valp) @@ -1843,33 +1882,32 @@ yt921x_vlan_filtering(struct yt921x_priv *priv, int= port, bool vlan_filtering) return 0; } =20 -static int -yt921x_vlan_del(struct yt921x_priv *priv, int port, u16 vid) +static int yt921x_vlan_del(struct yt921x_priv *priv, int port, u16 vid) { - u64 mask64; + u32 masks[YT921X_VLAN_CTRL_S]; =20 - mask64 =3D YT921X_VLAN_CTRL_PORTS(port) | - YT921X_VLAN_CTRL_UNTAG_PORTn(port); + masks[0] =3D YT921X_VLAN_CTRLa_PORTn(port); + masks[1] =3D YT921X_VLAN_CTRLb_UNTAG_PORTn(port); =20 - return yt921x_reg64_clear_bits(priv, YT921X_VLANn_CTRL(vid), mask64); + return yt921x_longreg_clear_bits(priv, YT921X_VLANn_CTRL(vid), masks, + YT921X_VLAN_CTRL_S); } =20 static int yt921x_vlan_add(struct yt921x_priv *priv, int port, u16 vid, bool untagged) { - u64 mask64; - u64 ctrl64; + u32 masks[YT921X_VLAN_CTRL_S]; + u32 ctrls[YT921X_VLAN_CTRL_S]; =20 - mask64 =3D YT921X_VLAN_CTRL_PORTn(port) | - YT921X_VLAN_CTRL_PORTS(priv->cpu_ports_mask); - ctrl64 =3D mask64; + masks[0] =3D YT921X_VLAN_CTRLa_PORTn(port) | + YT921X_VLAN_CTRLa_PORTS(priv->cpu_ports_mask); + ctrls[0] =3D masks[0]; =20 - mask64 |=3D YT921X_VLAN_CTRL_UNTAG_PORTn(port); - if (untagged) - ctrl64 |=3D YT921X_VLAN_CTRL_UNTAG_PORTn(port); + masks[1] =3D YT921X_VLAN_CTRLb_UNTAG_PORTn(port); + ctrls[1] =3D untagged ? masks[1] : 0; =20 - return yt921x_reg64_update_bits(priv, YT921X_VLANn_CTRL(vid), - mask64, ctrl64); + return yt921x_longreg_update_bits(priv, YT921X_VLANn_CTRL(vid), + masks, ctrls, YT921X_VLAN_CTRL_S); } =20 static int @@ -2329,8 +2367,8 @@ yt921x_dsa_vlan_msti_set(struct dsa_switch *ds, struc= t dsa_bridge bridge, const struct switchdev_vlan_msti *msti) { struct yt921x_priv *priv =3D to_yt921x_priv(ds); - u64 mask64; - u64 ctrl64; + u32 masks[YT921X_VLAN_CTRL_S]; + u32 ctrls[YT921X_VLAN_CTRL_S]; int res; =20 if (!msti->vid) @@ -2338,12 +2376,14 @@ yt921x_dsa_vlan_msti_set(struct dsa_switch *ds, str= uct dsa_bridge bridge, if (!msti->msti || msti->msti >=3D YT921X_MSTI_NUM) return -EINVAL; =20 - mask64 =3D YT921X_VLAN_CTRL_STP_ID_M; - ctrl64 =3D YT921X_VLAN_CTRL_STP_ID(msti->msti); + masks[0] =3D 0; + ctrls[0] =3D 0; + masks[1] =3D YT921X_VLAN_CTRLb_STP_ID_M; + ctrls[1] =3D YT921X_VLAN_CTRLb_STP_ID(msti->msti); =20 mutex_lock(&priv->reg_lock); - res =3D yt921x_reg64_update_bits(priv, YT921X_VLANn_CTRL(msti->vid), - mask64, ctrl64); + res =3D yt921x_longreg_update_bits(priv, YT921X_VLANn_CTRL(msti->vid), + masks, ctrls, YT921X_VLAN_CTRL_S); mutex_unlock(&priv->reg_lock); =20 return res; @@ -3090,8 +3130,8 @@ static int yt921x_chip_reset(struct yt921x_priv *priv) static int yt921x_chip_setup_dsa(struct yt921x_priv *priv) { struct dsa_switch *ds =3D &priv->ds; + u32 ctrls[YT921X_VLAN_CTRL_S]; unsigned long cpu_ports_mask; - u64 ctrl64; u32 ctrl; int port; int res; @@ -3152,8 +3192,10 @@ static int yt921x_chip_setup_dsa(struct yt921x_priv = *priv) /* Tagged VID 0 should be treated as untagged, which confuses the * hardware a lot */ - ctrl64 =3D YT921X_VLAN_CTRL_LEARN_DIS | YT921X_VLAN_CTRL_PORTS_M; - res =3D yt921x_reg64_write(priv, YT921X_VLANn_CTRL(0), ctrl64); + ctrls[0] =3D YT921X_VLAN_CTRLa_LEARN_DIS | YT921X_VLAN_CTRLa_PORTS_M; + ctrls[1] =3D 0; + res =3D yt921x_longreg_write(priv, YT921X_VLANn_CTRL(0), ctrls, + YT921X_VLAN_CTRL_S); if (res) return res; =20 diff --git a/drivers/net/dsa/yt921x.h b/drivers/net/dsa/yt921x.h index 3f129b8d403f..361470582687 100644 --- a/drivers/net/dsa/yt921x.h +++ b/drivers/net/dsa/yt921x.h @@ -429,24 +429,25 @@ enum yt921x_app_selector { #define YT921X_FDB_HW_FLUSH_ON_LINKDOWN BIT(0) =20 #define YT921X_VLANn_CTRL(vlan) (0x188000 + 8 * (vlan)) -#define YT921X_VLAN_CTRL_UNTAG_PORTS_M GENMASK_ULL(50, 40) -#define YT921X_VLAN_CTRL_UNTAG_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRL_UNT= AG_PORTS_M, (x)) -#define YT921X_VLAN_CTRL_UNTAG_PORTn(port) BIT_ULL((port) + 40) -#define YT921X_VLAN_CTRL_STP_ID_M GENMASK_ULL(39, 36) -#define YT921X_VLAN_CTRL_STP_ID(x) FIELD_PREP(YT921X_VLAN_CTRL_STP_ID_= M, (x)) -#define YT921X_VLAN_CTRL_SVLAN_EN BIT_ULL(35) -#define YT921X_VLAN_CTRL_FID_M GENMASK_ULL(34, 23) -#define YT921X_VLAN_CTRL_FID(x) FIELD_PREP(YT921X_VLAN_CTRL_FID_M, (x)) -#define YT921X_VLAN_CTRL_LEARN_DIS BIT_ULL(22) -#define YT921X_VLAN_CTRL_PRIO_EN BIT_ULL(21) -#define YT921X_VLAN_CTRL_PRIO_M GENMASK_ULL(20, 18) -#define YT921X_VLAN_CTRL_PRIO(x) FIELD_PREP(YT921X_VLAN_CTRL_PRIO_M, (= x)) -#define YT921X_VLAN_CTRL_PORTS_M GENMASK_ULL(17, 7) -#define YT921X_VLAN_CTRL_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRL_PORTS_M,= (x)) -#define YT921X_VLAN_CTRL_PORTn(port) BIT_ULL((port) + 7) -#define YT921X_VLAN_CTRL_BYPASS_1X_AC BIT_ULL(6) -#define YT921X_VLAN_CTRL_METER_EN BIT_ULL(5) -#define YT921X_VLAN_CTRL_METER_ID_M GENMASK_ULL(4, 0) +#define YT921X_VLAN_CTRL_S 2 +#define YT921X_VLAN_CTRLb_UNTAG_PORTS_M GENMASK(18, 8) +#define YT921X_VLAN_CTRLb_UNTAG_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRLb_U= NTAG_PORTS_M, (x)) +#define YT921X_VLAN_CTRLb_UNTAG_PORTn(port) BIT((port) + 8) +#define YT921X_VLAN_CTRLb_STP_ID_M GENMASK(7, 4) +#define YT921X_VLAN_CTRLb_STP_ID(x) FIELD_PREP(YT921X_VLAN_CTRLb_STP_I= D_M, (x)) +#define YT921X_VLAN_CTRLb_SVLAN_EN BIT(3) +#define YT921X_VLAN_CTRLab_FID_M GENMASK_ULL(34, 23) +#define YT921X_VLAN_CTRLab_FID(x) FIELD_PREP(YT921X_VLAN_CTRLab_FID_M,= (x)) +#define YT921X_VLAN_CTRLa_LEARN_DIS BIT(22) +#define YT921X_VLAN_CTRLa_PRIO_EN BIT(21) +#define YT921X_VLAN_CTRLa_PRIO_M GENMASK(20, 18) +#define YT921X_VLAN_CTRLa_PRIO(x) FIELD_PREP(YT921X_VLAN_CTRLa_PRIO_M,= (x)) +#define YT921X_VLAN_CTRLa_PORTS_M GENMASK(17, 7) +#define YT921X_VLAN_CTRLa_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRLa_PORTS_= M, (x)) +#define YT921X_VLAN_CTRLa_PORTn(port) BIT((port) + 7) +#define YT921X_VLAN_CTRLa_BYPASS_1X_AC BIT(6) +#define YT921X_VLAN_CTRLa_METER_EN BIT(5) +#define YT921X_VLAN_CTRLa_METER_ID_M GENMASK(4, 0) =20 #define YT921X_TPID_IGRn(x) (0x210000 + 4 * (x)) /* [0, 3] */ #define YT921X_TPID_IGR_TPID_M GENMASK(15, 0) --=20 2.51.0