From nobody Mon Feb 9 03:47:54 2026 Received: from luna.linkmauve.fr (luna.linkmauve.fr [82.65.109.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F32EC25742F; Wed, 28 Jan 2026 18:29:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=82.65.109.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769624989; cv=none; b=Lpnmu7HnpSvTl+SzX8jO0ij2gEPciHjCsyuooCgm4+L+V3OVNxazWpcxW7Nka7M/CStBGu68VQq2XQJDJQIuRNVxY3qwOuGVTuuI8hxng1wx9ZgBSMsmIrRJtKMiGaVj4hhkniY7dW0V6As3S4a3+GI24Aa0zGOobxakBbp0nQM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769624989; c=relaxed/simple; bh=hIXy4ODNUDfyh2LDWRnsbyzoIBW5G1hBEd8Pqcu6hgQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jRjx6y3E5MB8gkoZLUZdLKj7SeKUrofHFtBl3c6xGV67ZieYuY4z+ZoBq9sWAvELJJK5tgKiAnQFmuaAxixmvm5VzsUigfhjxS+e6SONDDEQMvP22RK/6Naa40/U/78OirpJcdjbpaQubx+EyGsOwSCCrLiX6SQgPg3nVLSuIa0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=linkmauve.fr; spf=pass smtp.mailfrom=linkmauve.fr; arc=none smtp.client-ip=82.65.109.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=linkmauve.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linkmauve.fr Received: by luna.linkmauve.fr (Postfix, from userid 1000) id 97216F43B1A; Wed, 28 Jan 2026 19:29:39 +0100 (CET) From: Link Mauve To: rust-for-linux@vger.kernel.org Cc: Link Mauve , Srinivas Kandagatla , Miguel Ojeda , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Daniel Almeida , Greg Kroah-Hartman , Lyude Paul , Asahi Lina , Viresh Kumar , Lorenzo Stoakes , Tamir Duberstein , linux-kernel@vger.kernel.org Subject: [RFC PATCH 1/3] nvmem: Document enum nvmem_type and its variants Date: Wed, 28 Jan 2026 19:29:20 +0100 Message-ID: <20260128182925.13225-2-linkmauve@linkmauve.fr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128182925.13225-1-linkmauve@linkmauve.fr> References: <20260128182925.13225-1-linkmauve@linkmauve.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable These were previously undocumented, and while it is fine in C we emit a warning whenever an enum or its variants aren=E2=80=99t documented in Rust. Signed-off-by: Link Mauve --- include/linux/nvmem-provider.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h index f3b13da78aac..92e3d9a76137 100644 --- a/include/linux/nvmem-provider.h +++ b/include/linux/nvmem-provider.h @@ -25,6 +25,14 @@ typedef int (*nvmem_cell_post_process_t)(void *priv, con= st char *id, int index, unsigned int offset, void *buf, size_t bytes); =20 +/** + * The possible types for a nvmem provider. + * @NVMEM_TYPE_UNKNOWN: The type of memory is unknown. + * @NVMEM_TYPE_EEPROM: Electrically erasable programmable ROM. + * @NVMEM_TYPE_OTP: One-time programmable memory. + * @NVMEM_TYPE_BATTERY_BACKED: This memory is backed by a battery. + * @NVMEM_TYPE_FRAM: Ferroelectric RAM. + */ enum nvmem_type { NVMEM_TYPE_UNKNOWN =3D 0, NVMEM_TYPE_EEPROM, --=20 2.52.0 From nobody Mon Feb 9 03:47:54 2026 Received: from luna.linkmauve.fr (luna.linkmauve.fr [82.65.109.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 478EE37105B; Wed, 28 Jan 2026 18:29:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=82.65.109.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769624991; cv=none; b=XWF1SHoiQqpmkbd/8KjhMcqQfNoGJpzMkKQjWwMbmyPPDVy5b55D1xmva3K7qOab/QE1jSUSUYdW57BT92CAufpLFtQJ/R9/kQXiO3hWNInhSwl0voFQVA3P7PO4QH5UiQdKuTjKTHXyEywNDOfqyKTB2D0BPPw1QYVFXkCeFsU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769624991; c=relaxed/simple; bh=xypnlq/Lb7X6S2MnSwrGdh4sGeo6T/wA9KzyrMLgxbY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=t+eoJzARub4BrY/i92RGBo+Ku3YT+AmnT0e/zm8pNijZIzZbKVGoj+qpPSEwitxwD8RaGbTDWSZMwui8y0Z5JISXP1OpGoWJLnAYXF4oIWYhyvDpE0+rYE2jsqArV++vjuVTpW/ET6Qo0RJ8F4XvoCCsaRH8FXJviTSP9rXr+aQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=linkmauve.fr; spf=pass smtp.mailfrom=linkmauve.fr; arc=none smtp.client-ip=82.65.109.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=linkmauve.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linkmauve.fr Received: by luna.linkmauve.fr (Postfix, from userid 1000) id 47208F43B1B; Wed, 28 Jan 2026 19:29:41 +0100 (CET) From: Link Mauve To: rust-for-linux@vger.kernel.org Cc: Link Mauve , Srinivas Kandagatla , Miguel Ojeda , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Daniel Almeida , Greg Kroah-Hartman , Lyude Paul , Asahi Lina , Viresh Kumar , Lorenzo Stoakes , Tamir Duberstein , linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/3] rust: nvmem: Add an abstraction for nvmem providers Date: Wed, 28 Jan 2026 19:29:21 +0100 Message-ID: <20260128182925.13225-3-linkmauve@linkmauve.fr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128182925.13225-1-linkmauve@linkmauve.fr> References: <20260128182925.13225-1-linkmauve@linkmauve.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This is my very first Rust abstraction in the kernel, I took inspiration from various other abstractions that had already been written. I only implemented enough to rewrite a very simple driver I wrote in the past, in order to test the API and make sure it=E2=80=99s at least as ergon= omic as the C version, without any unsafe at all. I=E2=80=99m not completely happy about the API, especially the NvmemConfig = type has a bunch of setters but nothing forces you to use them correctly, notably that .set_priv() has been called before .set(). Should I maybe merge them into a single one which takes both arguments? Or is it ok if priv isn=E2=80=99t set? I=E2=80=99m not sure in which case that could be u= seful, maybe in C when using globals. Signed-off-by: Link Mauve --- rust/bindings/bindings_helper.h | 1 + rust/kernel/lib.rs | 2 + rust/kernel/nvmem.rs | 155 ++++++++++++++++++++++++++++++++ 3 files changed, 158 insertions(+) create mode 100644 rust/kernel/nvmem.rs diff --git a/rust/bindings/bindings_helper.h b/rust/bindings/bindings_helpe= r.h index a067038b4b42..522a76b2e294 100644 --- a/rust/bindings/bindings_helper.h +++ b/rust/bindings/bindings_helper.h @@ -65,6 +65,7 @@ #include #include #include +#include #include #include #include diff --git a/rust/kernel/lib.rs b/rust/kernel/lib.rs index f812cf120042..dd0ac968d05f 100644 --- a/rust/kernel/lib.rs +++ b/rust/kernel/lib.rs @@ -115,6 +115,8 @@ pub mod module_param; #[cfg(CONFIG_NET)] pub mod net; +#[cfg(CONFIG_NVMEM)] +pub mod nvmem; pub mod num; pub mod of; #[cfg(CONFIG_PM_OPP)] diff --git a/rust/kernel/nvmem.rs b/rust/kernel/nvmem.rs new file mode 100644 index 000000000000..555ed260629c --- /dev/null +++ b/rust/kernel/nvmem.rs @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! nvmem framework provider. +//! +//! Copyright (C) 2026 Link Mauve + +use crate::build_error; +use crate::device::Device; +use crate::error::{from_result, VTABLE_DEFAULT_ERROR}; +use crate::prelude::*; +use core::marker::PhantomData; +use macros::vtable; + +/// The possible types for a nvmem provider. +#[derive(Default)] +#[repr(u32)] +pub enum Type { + /// The type of memory is unknown. + #[default] + Unknown =3D bindings::nvmem_type_NVMEM_TYPE_UNKNOWN, + + /// Electrically erasable programmable ROM. + Eeprom =3D bindings::nvmem_type_NVMEM_TYPE_EEPROM, + + /// One-time programmable memory. + Otp =3D bindings::nvmem_type_NVMEM_TYPE_OTP, + + /// This memory is backed by a battery. + BatteryBacked =3D bindings::nvmem_type_NVMEM_TYPE_BATTERY_BACKED, + + /// Ferroelectric RAM. + Fram =3D bindings::nvmem_type_NVMEM_TYPE_FRAM, +} + +/// nvmem configuration. +/// +/// Rust abstraction for the C `struct nvmem_config`. +#[derive(Default)] +pub struct NvmemConfig +where + T: Default, +{ + inner: bindings::nvmem_config, + _p: PhantomData, +} + +impl NvmemConfig { + /// NvmemConfig's read callback. + /// + /// SAFETY: Called from C. Inputs must be valid pointers. + extern "C" fn reg_read( + context: *mut c_void, + offset: u32, + val: *mut c_void, + bytes: usize, + ) -> i32 { + from_result(|| { + // SAFETY: context is a valid T::Priv as defined in Self::set_= priv(). + let context =3D unsafe { &*(context as *mut T::Priv) }; + let val =3D val as *mut u8; + // SAFETY: val should be non-null, and allocated for bytes byt= es. + let data =3D unsafe { core::slice::from_raw_parts_mut(val, byt= es) }; + T::read(context, offset, data).map(|()| 0) + }) + } + + /// NvmemConfig's write callback. + /// + /// SAFETY: Called from C. Inputs must be valid pointers. + extern "C" fn reg_write( + context: *mut c_void, + offset: u32, + // TODO: Change val from void* to const void* in the C API! + val: *mut c_void, + bytes: usize, + ) -> i32 { + from_result(|| { + // SAFETY: context is a valid T::Priv as defined in Self::set_= priv(). + let context =3D unsafe { &*(context as *mut T::Priv) }; + let val =3D val as *mut u8 as *const u8; + // SAFETY: val should be non-null, and allocated for bytes byt= es. + let data =3D unsafe { core::slice::from_raw_parts(val, bytes) = }; + T::write(context, offset, data).map(|()| 0) + }) + } + + /// User context passed to read/write callbacks. + pub fn set_priv(&mut self, priv_: &T::Priv) { + // FIXME: This list of as indicates some unsoundness in the types= =E2=80=A6 + self.inner.priv_ =3D priv_ as *const T::Priv as *const c_void as *= mut c_void; + } + + /// Sets the configuration on the given device. + pub fn set(mut self, dev: &Device) { + self.inner.reg_read =3D Some(Self::reg_read); + self.inner.reg_write =3D Some(Self::reg_write); + // SAFETY: All arguments should be non-null and what the function = expects. + unsafe { bindings::devm_nvmem_register(dev.as_raw(), &self.inner) = }; + } + + /// Optional name. + pub fn set_name(&mut self, name: &CStr) { + // TODO: Why do we have to do this cast from i8 to u8? + self.inner.name =3D name.as_ptr() as *const _; + } + + /// Type of the nvmem storage + pub fn set_type(&mut self, type_: Type) { + self.inner.type_ =3D type_ as u32; + } + + /// Device is read-only. + pub fn set_read_only(&mut self, read_only: bool) { + self.inner.read_only =3D read_only; + } + + /// Device is accessibly to root only. + pub fn set_root_only(&mut self, root_only: bool) { + self.inner.root_only =3D root_only; + } + + /// Device size. + pub fn set_size(&mut self, size: i32) { + self.inner.size =3D size; + } + + /// Minimum read/write access granularity. + pub fn set_word_size(&mut self, word_size: i32) { + self.inner.word_size =3D word_size; + } + + /// Minimum read/write access stride. + pub fn set_stride(&mut self, stride: i32) { + self.inner.stride =3D stride; + } +} + +/// Helper trait to define the callbacks of a nvmem provider. +#[vtable] +pub trait NvmemProvider { + /// The type passed into the context for read and write functions. + type Priv; + + /// Callback to read data. + #[inline] + fn read(_context: &Self::Priv, _offset: u32, _data: &mut [u8]) -> Resu= lt { + build_error!(VTABLE_DEFAULT_ERROR) + } + + /// Callback to write data. + #[inline] + fn write(_context: &Self::Priv, _offset: u32, _data: &[u8]) -> Result { + build_error!(VTABLE_DEFAULT_ERROR) + } +} --=20 2.52.0 From nobody Mon Feb 9 03:47:54 2026 Received: from luna.linkmauve.fr (luna.linkmauve.fr [82.65.109.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4799537105C; Wed, 28 Jan 2026 18:29:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=82.65.109.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769624991; cv=none; b=f+TVAaRplU+FV3V86/NF1sOgnEWN/DtsS8J05kRW86XSOWFaq2lg51Pj7p3oZoUHhNtJf+TkQ5DvF7b740j9B+4nU1JM3oCgScw7l7JXWTkdKFkqMKwc+kXSUI+E9CaOQ3lFcY+LtRB6GNtzgW78GUso7lsB0iBA6ekeWqlgZoo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769624991; c=relaxed/simple; bh=enCdY+GUGxoQci/ulFuQFQ6dafNy8HAatx8DOExTxcM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=unQ0pqUmL1qgkQPJET0a1RgYeTDYs39+s85fd1JqAo+7VZaK3tH+4/OK/x2p+skFxSM9JqR5f9s/rmkTMZBcIok5tvDkGJScUTdBzBNsX8/GRGAO8wui0TVzNvWCbOtHk8Hk+Bvh+QGm7/KebkL0TVpbn016GuTRaYgdTsNgZnI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=linkmauve.fr; spf=pass smtp.mailfrom=linkmauve.fr; arc=none smtp.client-ip=82.65.109.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=linkmauve.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linkmauve.fr Received: by luna.linkmauve.fr (Postfix, from userid 1000) id 4FB08F43B1C; Wed, 28 Jan 2026 19:29:47 +0100 (CET) From: Link Mauve To: rust-for-linux@vger.kernel.org Cc: Link Mauve , Srinivas Kandagatla , Miguel Ojeda , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Daniel Almeida , Greg Kroah-Hartman , Lyude Paul , Asahi Lina , Viresh Kumar , Lorenzo Stoakes , Tamir Duberstein , linux-kernel@vger.kernel.org Subject: [RFC PATCH 3/3] =?UTF-8?q?nvmem:=20Replace=20the=20Wii=20and=20Wi?= =?UTF-8?q?i=E2=80=AFU=20OTP=20driver=20with=20a=20Rust=20one?= Date: Wed, 28 Jan 2026 19:29:22 +0100 Message-ID: <20260128182925.13225-4-linkmauve@linkmauve.fr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260128182925.13225-1-linkmauve@linkmauve.fr> References: <20260128182925.13225-1-linkmauve@linkmauve.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable I wrote this driver long ago, and wanted to try seeing how hard it would be to convert it to Rust. I don=E2=80=99t have access to my Wii=E2=80=AFU at the moment, so I=E2=80= =99ve only tested that this module builds without error or warning, but not tested it on the hardware, hence the RFC status of this series. It is a very simple driver, we write the address we want to read in one memory address, and read the data from a second memory address. A third memory address can be used to disable all reads in a range until the system has been rebooted, but I didn=E2=80=99t find any reason to expose th= at feature. I made sure to use no unsafe in this driver, to make sure the API exposed in the previous commit is usable. There is no function to read a 32-bit value in big-endian yet, but this driver will exclusively run on big-endian PowerPC 32 anyway, so it shouldn=E2=80=99t be an issue to use io.read32() and io.write32(). Ideally we wouldn=E2=80=99t have to impl the write() function in NintendoOtpProvider, but currently the vtable requires both. Signed-off-by: Link Mauve --- drivers/nvmem/Makefile | 2 +- drivers/nvmem/nintendo-otp.c | 122 ------------------------------ drivers/nvmem/nintendo_otp.rs | 137 ++++++++++++++++++++++++++++++++++ 3 files changed, 138 insertions(+), 123 deletions(-) delete mode 100644 drivers/nvmem/nintendo-otp.c create mode 100644 drivers/nvmem/nintendo_otp.rs diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 7252b8ec88d4..3d40a0a23f76 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -51,7 +51,7 @@ nvmem_mtk-efuse-y :=3D mtk-efuse.o obj-$(CONFIG_NVMEM_MXS_OCOTP) +=3D nvmem-mxs-ocotp.o nvmem-mxs-ocotp-y :=3D mxs-ocotp.o obj-$(CONFIG_NVMEM_NINTENDO_OTP) +=3D nvmem-nintendo-otp.o -nvmem-nintendo-otp-y :=3D nintendo-otp.o +nvmem-nintendo-otp-y :=3D nintendo_otp.o obj-$(CONFIG_NVMEM_QCOM_QFPROM) +=3D nvmem_qfprom.o nvmem_qfprom-y :=3D qfprom.o obj-$(CONFIG_NVMEM_QCOM_SEC_QFPROM) +=3D nvmem_sec_qfprom.o diff --git a/drivers/nvmem/nintendo-otp.c b/drivers/nvmem/nintendo-otp.c deleted file mode 100644 index 355e7f1fc6d5..000000000000 --- a/drivers/nvmem/nintendo-otp.c +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Nintendo Wii and Wii=C2=A0U OTP driver - * - * This is a driver exposing the OTP of a Nintendo Wii or Wii=C2=A0U conso= le. - * - * This memory contains common and per-console keys, signatures and - * related data required to access peripherals. - * - * Based on reversed documentation from https://wiiubrew.org/wiki/Hardware= /OTP - * - * Copyright (C) 2021 Emmanuel Gil Peyrot - */ - -#include -#include -#include -#include -#include -#include -#include - -#define HW_OTPCMD 0 -#define HW_OTPDATA 4 -#define OTP_READ 0x80000000 -#define BANK_SIZE 128 -#define WORD_SIZE 4 - -struct nintendo_otp_priv { - void __iomem *regs; -}; - -struct nintendo_otp_devtype_data { - const char *name; - unsigned int num_banks; -}; - -static const struct nintendo_otp_devtype_data hollywood_otp_data =3D { - .name =3D "wii-otp", - .num_banks =3D 1, -}; - -static const struct nintendo_otp_devtype_data latte_otp_data =3D { - .name =3D "wiiu-otp", - .num_banks =3D 8, -}; - -static int nintendo_otp_reg_read(void *context, - unsigned int reg, void *_val, size_t bytes) -{ - struct nintendo_otp_priv *priv =3D context; - u32 *val =3D _val; - int words =3D bytes / WORD_SIZE; - u32 bank, addr; - - while (words--) { - bank =3D (reg / BANK_SIZE) << 8; - addr =3D (reg / WORD_SIZE) % (BANK_SIZE / WORD_SIZE); - iowrite32be(OTP_READ | bank | addr, priv->regs + HW_OTPCMD); - *val++ =3D ioread32be(priv->regs + HW_OTPDATA); - reg +=3D WORD_SIZE; - } - - return 0; -} - -static const struct of_device_id nintendo_otp_of_table[] =3D { - { .compatible =3D "nintendo,hollywood-otp", .data =3D &hollywood_otp_data= }, - { .compatible =3D "nintendo,latte-otp", .data =3D &latte_otp_data }, - {/* sentinel */}, -}; -MODULE_DEVICE_TABLE(of, nintendo_otp_of_table); - -static int nintendo_otp_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - const struct of_device_id *of_id =3D - of_match_device(nintendo_otp_of_table, dev); - struct nvmem_device *nvmem; - struct nintendo_otp_priv *priv; - - struct nvmem_config config =3D { - .stride =3D WORD_SIZE, - .word_size =3D WORD_SIZE, - .reg_read =3D nintendo_otp_reg_read, - .read_only =3D true, - .root_only =3D true, - }; - - priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->regs =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(priv->regs)) - return PTR_ERR(priv->regs); - - if (of_id->data) { - const struct nintendo_otp_devtype_data *data =3D of_id->data; - config.name =3D data->name; - config.size =3D data->num_banks * BANK_SIZE; - } - - config.dev =3D dev; - config.priv =3D priv; - - nvmem =3D devm_nvmem_register(dev, &config); - - return PTR_ERR_OR_ZERO(nvmem); -} - -static struct platform_driver nintendo_otp_driver =3D { - .probe =3D nintendo_otp_probe, - .driver =3D { - .name =3D "nintendo-otp", - .of_match_table =3D nintendo_otp_of_table, - }, -}; -module_platform_driver(nintendo_otp_driver); -MODULE_AUTHOR("Emmanuel Gil Peyrot "); -MODULE_DESCRIPTION("Nintendo Wii and Wii U OTP driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/nvmem/nintendo_otp.rs b/drivers/nvmem/nintendo_otp.rs new file mode 100644 index 000000000000..d1906c7348b3 --- /dev/null +++ b/drivers/nvmem/nintendo_otp.rs @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0-only + +//! Nintendo Wii and Wii=C2=A0U OTP driver +//! +//! This is a driver exposing the OTP of a Nintendo Wii or Wii=C2=A0U cons= ole. +//! +//! This memory contains common and per-console keys, signatures and +//! related data required to access peripherals. +//! +//! Based on reversed documentation from https://wiiubrew.org/wiki/Hardwar= e/OTP +//! +//! Copyright (C) 2021 Link Mauve + +use kernel::{ + c_str, + device::Core, + io::Io, + nvmem::{self, NvmemConfig, NvmemProvider}, + of::{DeviceId, IdTable}, + platform, + prelude::*, + sync::aref::ARef, +}; + +const HW_OTPCMD: usize =3D 0; +const HW_OTPDATA: usize =3D 4; +const OTP_READ: u32 =3D 0x80000000; +const BANK_SIZE: u32 =3D 128; +const WORD_SIZE: u32 =3D 4; + +struct Info { + name: &'static CStr, + num_banks: u32, +} + +const WII_INFO: Info =3D Info { + name: c_str!("wii-otp"), + num_banks: 1, +}; + +const WIIU_INFO: Info =3D Info { + name: c_str!("wiiu-otp"), + num_banks: 8, +}; + +struct NintendoOtpDriver { + pdev: ARef, +} + +kernel::of_device_table!( + OF_TABLE, + MODULE_OF_TABLE, + ::IdInfo, + [ + (DeviceId::new(c_str!("nintendo,hollywood-otp")), WII_INFO), + (DeviceId::new(c_str!("nintendo,latte-otp")), WIIU_INFO), + ] +); + +#[derive(Default)] +struct NintendoOtpProvider; + +#[vtable] +impl NvmemProvider for NintendoOtpProvider { + type Priv =3D Io<8>; + + fn read(io: &Self::Priv, mut reg: u32, mut data: &mut [u8]) -> Result { + loop { + let Some(bytes) =3D data.split_off_mut(..4) else { + break; + }; + let bank =3D (reg / BANK_SIZE) << 8; + let addr =3D (reg / WORD_SIZE) % (BANK_SIZE / WORD_SIZE); + io.write32(OTP_READ | bank | addr, HW_OTPCMD); + let elem =3D io.read32(HW_OTPDATA); + bytes.copy_from_slice(&elem.to_be_bytes()); + reg +=3D WORD_SIZE; + } + + Ok(()) + } + + fn write(_context: &Self::Priv, _offset: u32, _data: &[u8]) -> Result { + Err(ENODEV) + } +} + +impl platform::Driver for NintendoOtpDriver { + type IdInfo =3D Info; + const OF_ID_TABLE: Option> =3D Some(&OF_TABLE); + + fn probe( + pdev: &platform::Device, + info: Option<&Self::IdInfo>, + ) -> impl PinInit { + let dev =3D pdev.as_ref(); + + let Some(Info { name, num_banks }) =3D info else { + return Err(EINVAL); + }; + + dev_info!(dev, "Probed as '{name}', num_banks =3D {num_banks}.\n"); + + let request =3D pdev.io_request_by_index(0).ok_or(ENODEV)?; + let iomem =3D request.iomap_exclusive_sized::<8>(); + let iomem =3D KBox::pin_init(iomem, GFP_KERNEL)?; + + let io =3D iomem.access(dev)?; + + let mut config =3D NvmemConfig::::default(); + config.set_name(name); + config.set_type(nvmem::Type::Otp); + config.set_size((num_banks * BANK_SIZE) as i32); + config.set_word_size(WORD_SIZE as i32); + config.set_stride(WORD_SIZE as i32); + config.set_read_only(true); + config.set_root_only(true); + config.set_priv(io); + config.set(dev); + + Ok(Self { pdev: pdev.into() }) + } +} + +impl Drop for NintendoOtpDriver { + fn drop(&mut self) { + dev_dbg!(self.pdev.as_ref(), "Remove Rust Platform driver sample.\= n"); + } +} + +kernel::module_platform_driver! { + type: NintendoOtpDriver, + name: "nintendo-otp", + authors: ["Link Mauve "], + description: "Nintendo Wii and Wii U OTP driver", + license: "GPL v2", +} --=20 2.52.0