From nobody Tue Feb 10 11:23:58 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38D9F2E2299 for ; Wed, 28 Jan 2026 15:38:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769614713; cv=none; b=Q68ECURAWohr2bZD7NkE/u8bOFLdYWduSpElxyDpLP5gbhw+BNFhpQOAplh8DfBtqYzK415I7RSU0u75+xAWr5nad8qXwVAlJG0UIMUb3YMJXwe/kCyGEx2PXbiqrjURxHwA9j/99Z5y+A2HaPKdhte1vkx7ssEI+/iufOzKV/o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769614713; c=relaxed/simple; bh=cICnMvrZpddQjj4AsMXgMuQwqiM4gYA74oqyfJsDmfM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ExUwRNTjyWhc245dZPi3/VVM8ddhVS9Wlu7QJefxn6zk1nEltEY4hTrGCSSoHqKbUtvYDxVrrt4O3ToeNBdfeqG3c+bD28PfTM7Kgw81c52bKrQTwBS8a0Ij1ZWFkea9QlXlBlPQSOicOpHYgX42/dYLvXMGDRsvAxUy/EflW9c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1vl7cg-0003ov-Ni; Wed, 28 Jan 2026 16:38:26 +0100 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac] helo=dude04) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1vl7cg-002wSX-33; Wed, 28 Jan 2026 16:38:26 +0100 Received: from ore by dude04 with local (Exim 4.98.2) (envelope-from ) id 1vl7cg-0000000FRAk-0h6c; Wed, 28 Jan 2026 16:38:26 +0100 From: Oleksij Rempel To: Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Andy Shevchenko , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , David Jander Subject: [PATCH v3 7/8] iio: dac: ds4424: convert to regmap Date: Wed, 28 Jan 2026 16:38:23 +0100 Message-ID: <20260128153824.3679187-8-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260128153824.3679187-1-o.rempel@pengutronix.de> References: <20260128153824.3679187-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Refactor the driver to use the regmap API. Replace the driver-specific mutex and manual shadow buffers with the standard regmap infrastructure for locking and caching. This ensures the cache is populated from hardware at probe, preventing state desynchronization (e.g. across suspend/resume). Define access tables to validate the different register maps of DS44x2 and DS44x4. Signed-off-by: Oleksij Rempel Reviewed-by: Sander Vanheule --- changes v3: - Switch to REGCACHE_MAPLE to efficiently handle the sparse register map (offset 0xF8) and avoid allocating memory for the unused 0x00-0xF7 range. - Use explicit regmap_bulk_read() in probe to seed the cache with the bootloader configuration. This avoids the invalid read from address 0x00 that occurred with generic cache defaults. - Remove ds4424_verify_chip(); devm_regmap_init_i2c() and the subsequent bulk read implicitly validate the device presence. - Use regmap_bulk_write() in ds4424_suspend() to efficiently zero all channels. - Adopt fsleep() for delays and include . - Use dev_err_ratelimited() with the physical device context in the read path (incorporating feedback aimed at v2 patch 8). changes v2: - new patch --- drivers/iio/dac/Kconfig | 1 + drivers/iio/dac/ds4424.c | 171 ++++++++++++++++++++++----------------- 2 files changed, 97 insertions(+), 75 deletions(-) diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index 7cd3caec1262..dbbbc45e8718 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -408,6 +408,7 @@ config DPOT_DAC config DS4424 tristate "Maxim Integrated DS4422/DS4424 DAC driver" depends on I2C + select REGMAP_I2C help If you say yes here you get support for Maxim chips DS4422, DS4424. =20 diff --git a/drivers/iio/dac/ds4424.c b/drivers/iio/dac/ds4424.c index f340d491fcc1..9bef1c60b2eb 100644 --- a/drivers/iio/dac/ds4424.c +++ b/drivers/iio/dac/ds4424.c @@ -5,12 +5,14 @@ * Copyright (C) 2017 Maxim Integrated */ =20 +#include #include #include #include #include #include #include +#include #include =20 #include @@ -42,11 +44,8 @@ enum ds4424_device_ids { }; =20 struct ds4424_data { - struct i2c_client *client; - struct mutex lock; - uint8_t save[DS4424_MAX_DAC_CHANNELS]; + struct regmap *regmap; struct regulator *vcc_reg; - uint8_t raw[DS4424_MAX_DAC_CHANNELS]; }; =20 static const struct iio_chan_spec ds4424_channels[] =3D { @@ -56,52 +55,88 @@ static const struct iio_chan_spec ds4424_channels[] =3D= { DS4424_CHANNEL(3), }; =20 -static int ds4424_get_value(struct iio_dev *indio_dev, - int *val, int channel) -{ - struct ds4424_data *data =3D iio_priv(indio_dev); - int ret; +static const struct regmap_range ds44x2_ranges[] =3D { + regmap_reg_range(DS4424_DAC_ADDR(0), DS4424_DAC_ADDR(1)), +}; =20 - mutex_lock(&data->lock); - ret =3D i2c_smbus_read_byte_data(data->client, DS4424_DAC_ADDR(channel)); - if (ret < 0) - goto fail; +static const struct regmap_range ds44x4_ranges[] =3D { + regmap_reg_range(DS4424_DAC_ADDR(0), DS4424_DAC_ADDR(3)), +}; =20 - *val =3D ret; +static const struct regmap_access_table ds44x2_table =3D { + .yes_ranges =3D ds44x2_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ds44x2_ranges), +}; =20 -fail: - mutex_unlock(&data->lock); - return ret; -} +static const struct regmap_access_table ds44x4_table =3D { + .yes_ranges =3D ds44x4_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ds44x4_ranges), +}; =20 -static int ds4424_set_value(struct iio_dev *indio_dev, - int val, struct iio_chan_spec const *chan) +static const struct regmap_config ds44x2_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .cache_type =3D REGCACHE_MAPLE, + .max_register =3D DS4424_DAC_ADDR(1), + .rd_table =3D &ds44x2_table, + .wr_table =3D &ds44x2_table, + /* Seed cache from HW during regmap_init */ +}; + +static const struct regmap_config ds44x4_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .cache_type =3D REGCACHE_MAPLE, + .max_register =3D DS4424_DAC_ADDR(3), + .rd_table =3D &ds44x4_table, + .wr_table =3D &ds44x4_table, + /* Seed cache from HW during regmap_init */ +}; + +static int ds4424_init_regmap(struct i2c_client *client, + struct iio_dev *indio_dev) { struct ds4424_data *data =3D iio_priv(indio_dev); + const struct regmap_config *regmap_config; + u8 vals[DS4424_MAX_DAC_CHANNELS]; int ret; =20 - mutex_lock(&data->lock); - ret =3D i2c_smbus_write_byte_data(data->client, - DS4424_DAC_ADDR(chan->channel), val); - if (ret < 0) - goto fail; - - data->raw[chan->channel] =3D val; - -fail: - mutex_unlock(&data->lock); - return ret; + if (indio_dev->num_channels =3D=3D DS4424_MAX_DAC_CHANNELS) + regmap_config =3D &ds44x4_regmap_config; + else + regmap_config =3D &ds44x2_regmap_config; + + data->regmap =3D devm_regmap_init_i2c(client, regmap_config); + if (IS_ERR(data->regmap)) + return dev_err_probe(&client->dev, PTR_ERR(data->regmap), + "Failed to init regmap.\n"); + + /* + * Prime the cache with the bootloader's configuration. + * regmap_bulk_read will automatically populate the cache with + * the values read from the hardware. + */ + ret =3D regmap_bulk_read(data->regmap, DS4424_DAC_ADDR(0), vals, + indio_dev->num_channels); + if (ret) + return dev_err_probe(&client->dev, ret, + "Failed to read hardware defaults\n"); + + return 0; } =20 static int ds4424_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { - int ret, regval; + struct ds4424_data *data =3D iio_priv(indio_dev); + unsigned int regval; + int ret; =20 switch (mask) { case IIO_CHAN_INFO_RAW: - ret =3D ds4424_get_value(indio_dev, ®val, chan->channel); + ret =3D regmap_read(data->regmap, DS4424_DAC_ADDR(chan->channel), + ®val); if (ret < 0) { dev_err_ratelimited(indio_dev->dev.parent, "Failed to read channel %d: %pe\n", @@ -124,6 +159,7 @@ static int ds4424_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { + struct ds4424_data *data =3D iio_priv(indio_dev); unsigned int abs_val; =20 if (val2 !=3D 0) @@ -143,58 +179,44 @@ static int ds4424_write_raw(struct iio_dev *indio_dev, if (val > 0) abs_val |=3D DS4424_DAC_SOURCE; =20 - return ds4424_set_value(indio_dev, abs_val, chan); + return regmap_write(data->regmap, DS4424_DAC_ADDR(chan->channel), + abs_val); =20 default: return -EINVAL; } } =20 -static int ds4424_verify_chip(struct iio_dev *indio_dev) -{ - int ret, val; - - ret =3D ds4424_get_value(indio_dev, &val, 0); - if (ret < 0) - dev_err(&indio_dev->dev, - "%s failed. ret: %d\n", __func__, ret); - - return ret; -} - static int ds4424_suspend(struct device *dev) { - struct i2c_client *client =3D to_i2c_client(dev); - struct iio_dev *indio_dev =3D i2c_get_clientdata(client); + struct iio_dev *indio_dev =3D dev_get_drvdata(dev); struct ds4424_data *data =3D iio_priv(indio_dev); - int ret =3D 0; - int i; - - for (i =3D 0; i < indio_dev->num_channels; i++) { - data->save[i] =3D data->raw[i]; - ret =3D ds4424_set_value(indio_dev, 0, - &indio_dev->channels[i]); - if (ret < 0) - return ret; + u8 zero_buf[DS4424_MAX_DAC_CHANNELS] =3D { 0 }; + int ret; + + /* Disable all outputs, bypass cache so the '0' isn't saved */ + regcache_cache_bypass(data->regmap, true); + ret =3D regmap_bulk_write(data->regmap, DS4424_DAC_ADDR(0), + zero_buf, indio_dev->num_channels); + regcache_cache_bypass(data->regmap, false); + if (ret) { + dev_err(dev, "Failed to zero outputs: %pe\n", ERR_PTR(ret)); + return ret; } - return ret; + + regcache_cache_only(data->regmap, true); + regcache_mark_dirty(data->regmap); + + return 0; } =20 static int ds4424_resume(struct device *dev) { - struct i2c_client *client =3D to_i2c_client(dev); - struct iio_dev *indio_dev =3D i2c_get_clientdata(client); + struct iio_dev *indio_dev =3D dev_get_drvdata(dev); struct ds4424_data *data =3D iio_priv(indio_dev); - int ret =3D 0; - int i; =20 - for (i =3D 0; i < indio_dev->num_channels; i++) { - ret =3D ds4424_set_value(indio_dev, data->save[i], - &indio_dev->channels[i]); - if (ret < 0) - return ret; - } - return ret; + regcache_cache_only(data->regmap, false); + return regcache_sync(data->regmap); } =20 static DEFINE_SIMPLE_DEV_PM_OPS(ds4424_pm_ops, ds4424_suspend, ds4424_resu= me); @@ -217,7 +239,6 @@ static int ds4424_probe(struct i2c_client *client) =20 data =3D iio_priv(indio_dev); i2c_set_clientdata(client, indio_dev); - data->client =3D client; indio_dev->name =3D id->name; =20 data->vcc_reg =3D devm_regulator_get(&client->dev, "vcc"); @@ -225,7 +246,6 @@ static int ds4424_probe(struct i2c_client *client) return dev_err_probe(&client->dev, PTR_ERR(data->vcc_reg), "Failed to get vcc-supply regulator.\n"); =20 - mutex_init(&data->lock); ret =3D regulator_enable(data->vcc_reg); if (ret < 0) { dev_err(&client->dev, @@ -233,10 +253,7 @@ static int ds4424_probe(struct i2c_client *client) return ret; } =20 - usleep_range(1000, 1200); - ret =3D ds4424_verify_chip(indio_dev); - if (ret < 0) - goto fail; + fsleep(1000); =20 switch (id->driver_data) { case ID_DS4402: @@ -258,6 +275,10 @@ static int ds4424_probe(struct i2c_client *client) goto fail; } =20 + ret =3D ds4424_init_regmap(client, indio_dev); + if (ret) + goto fail; + indio_dev->channels =3D ds4424_channels; indio_dev->modes =3D INDIO_DIRECT_MODE; indio_dev->info =3D &ds4424_info; --=20 2.47.3