From nobody Sat Feb 7 05:53:39 2026 Received: from mail-ej1-f67.google.com (mail-ej1-f67.google.com [209.85.218.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F8B5350A37 for ; Wed, 28 Jan 2026 12:58:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.67 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769605139; cv=none; b=oWBzb/LslSiC476H5ni6LVJn3E3jHzbNDJQvGMjFGXQWgrnBZPWNq9pEpHXLYUFJq8lfWoycXhrb8RZDYTBiU2XH14hEdbN4khMfrw1t14DieTknzzEQ8SVR072CAY2j2rnf2i0cFpT5O4k8lOMX61CHB0sS8G36xUeb+lsjy+k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769605139; c=relaxed/simple; bh=Ash0Tpop8Drl9CIAodpSoVI1Y7+zlfnaCRmi8fNAgWg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=n5EPFDzN+0o5TC2buKCv7Ziy7Oec+Cuogm87H9IJZxFbpcD2h5/R7CoDhm/8w5RuJcwDN76TxHfM9H0PnXBOun0jNCM++qItpMhKe3/JqCHX2nCNPhQ4jTP61yqeDS+VYFDIbAgXrWCXtlOpcSkqCDhXivoAKcWzt+j4B0gPdqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=M/hxNO9u; arc=none smtp.client-ip=209.85.218.67 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="M/hxNO9u" Received: by mail-ej1-f67.google.com with SMTP id a640c23a62f3a-b87677a8abeso1031986066b.1 for ; Wed, 28 Jan 2026 04:58:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1769605136; x=1770209936; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fzDhRuPZgWgWzngc97Sq+tn62O+gmDRD2phzboYIu0g=; b=M/hxNO9uLcwVLFm44DQUKOS1cllH8vOdw4q9KA2AL/1EWeG0D/boDy/Zq9Fp21Po8r Gz2pplArVmhDfVgE2c9BcsQHSfm467YhFv4jD/cRgK6WNST/7L4hH/GWnnwZ4azcAmaX RqSTHrsW9jrrwLbAZ2ZNsxb1K4SOJcyyJTRdVpG+FAYiY+gV9al5k9n8WlA+IU1Hq15c btdWHnWm5kl1raJVdfMynB8MYr8luVRaUeuN2ZD0rVKUqggp4t1TqwazBGIgysk7wUa8 exbY11nWtR4ML9qxOzzpkq2oJgw5CvEsn+u36Rx8PbdM5q7k8kYU+ItL59f9Mq1ePSZb DPGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769605136; x=1770209936; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=fzDhRuPZgWgWzngc97Sq+tn62O+gmDRD2phzboYIu0g=; b=SVqvwuNryZGnpnIQ9y6FtNrpilh4OL9NvpSx9hVibOgs7qqh9F8Zwq++QOqE87UfEW CI8tBXo89fbgeYm0jROu9vHWqYrbMir261fDRbZ46z2iU3DtOLTn1C4a74l3d6+TCxrE aeys4xYfyffikcpIT58dVRjhpInw2JTcGIhZGYxjuDEb3B+BXFrTs8AzeViAxtF4uzKm TvAZZBiyRGu3GJv0jiu31Hsd2koXKVXOMsjMTFRzUSfxPPji2R3MwSr2agOdmTvI4xC9 Lj972B9FbG74l9k1W4atYS1hcddWTjHf6HMr1bXkEnbKGc0IvkYtPJY+9xmjp6WI2Mdd BXEQ== X-Forwarded-Encrypted: i=1; AJvYcCUzeX7FCbvcDGZfoC2nmP9UtSxzVGitSAqCl5hgm6G0tPjSidLtZoKWjJV74Wb8YnR8hC13rxvDG9yv3DE=@vger.kernel.org X-Gm-Message-State: AOJu0YxfcZwfFU0/+YY4ggZ2lBusiTBg2vnyT4ZOJKfZ/jhe33jRLIlr NPAiWcI0lpSo+mTdW+MPan9QBR65smf+hpzJ2r5l8h/urfOXT7cl3gPZ X-Gm-Gg: AZuq6aL+s12WqN+b7kam6c1rfH7ejyBQRbq68KCPEovyAw5/Xq6DlGu/jf3DwYxSYKY h02K9YlOgvZiNQuo9Fwy/kdGclh1UlgWFsNezWrsG/ZfVaRTIXByhYjVZez0Tvx4dJGK0rOIFet CmojqOhKV/9PGvfhGEGlyF5wqfFOl8uJERCJTNiu/K4C5QtFvspcw29Nxr4KFGVhXRQplogzMT+ VmGM6gMSridCmFuqMa1WBddSMWAV1rpod4s/zRyJkQc46nc3R9rwM4BXxspsoEoh76nKbCOOYJb u3eS7j+rhMOtnpugF35bV0rAcFs9Je+W2pkpLgw0KgqgLzz9jS6kvgzmb+PF3UpeDcuD98ABs96 sRBzN/PrCsFMAJuE/jhQTz2S5N/luz/xN+CAYlY/4GHHywLbVcc+c0N3UuS62DtoKMi/1Yl+QCX JBmVoTzFDsX0RASdqIffj/JGBTLzt4j384GEE= X-Received: by 2002:a17:907:d8e:b0:b76:f090:777b with SMTP id a640c23a62f3a-b8dab2e7d35mr340318266b.22.1769605135725; Wed, 28 Jan 2026 04:58:55 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:e29d:6e0e:72c1:d15d]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf2f3e26sm123344966b.67.2026.01.28.04.58.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 04:58:55 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Lad Prabhakar , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das Subject: [PATCH net-next 1/8] dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/G3L SoC Date: Wed, 28 Jan 2026 12:58:38 +0000 Message-ID: <20260128125850.425264-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260128125850.425264-1-biju.das.jz@bp.renesas.com> References: <20260128125850.425264-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add device tree binding support for the Gigabit Ethernet (GBETH) IP on Renesas RZ/G3L SoC. This SoC uses different Synopsys DesignWare MAC version 5.30 compared to RZ/G3E. RZ/G3L requires an extra clock compared to RZ/G3E and has pps interrupts. Add a new compatible string "renesas,r9a08g046-gbeth" for RZ/G3L SoC and update the schema to handle hardware differences between SoC variants. Extend the base snps,dwmac.yaml schema to accommodate the PPS interrupts. Signed-off-by: Biju Das Acked-by: Conor Dooley --- .../bindings/net/renesas,rzv2h-gbeth.yaml | 77 ++++++++++++++++--- .../devicetree/bindings/net/snps,dwmac.yaml | 3 + 2 files changed, 69 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml= b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml index bd53ab300f50..21ac3c20bb61 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml @@ -26,6 +26,9 @@ select: properties: compatible: oneOf: + - items: + - const: renesas,r9a08g046-gbeth # RZ/G3L + - const: snps,dwmac-5.30a - items: - enum: - renesas,r9a09g047-gbeth # RZ/G3E @@ -47,13 +50,17 @@ properties: clocks: oneOf: - items: - - description: CSR clock - - description: AXI system clock + - description: CSR/Register access clock + - description: AXI system/Main clock - description: PTP clock - description: TX clock - description: RX clock - description: TX clock phase-shifted by 180 degrees - description: RX clock phase-shifted by 180 degrees + - description: RMII clock + + minItems: 7 + - items: - description: CSR clock - description: AXI system clock @@ -69,6 +76,10 @@ properties: - const: rx - const: tx-180 - const: rx-180 + - const: rmii + + minItems: 7 + - items: - const: stmmaceth - const: pclk @@ -88,6 +99,22 @@ properties: - const: tx-queue-1 - const: tx-queue-2 - const: tx-queue-3 + - items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + - const: ppt-pps-0 + - const: ppt-pps-1 + - const: ppt-pps-2 + - const: ppt-pps-3 - items: - const: macirq - const: eth_wake_irq @@ -135,6 +162,27 @@ required: allOf: - $ref: snps,dwmac.yaml# =20 + - if: + properties: + compatible: + contains: + const: renesas,r9a08g046-gbeth + then: + properties: + clocks: + minItems: 8 + + clock-names: + minItems: 8 + + interrupts: + minItems: 15 + maxItems: 15 + + interrupt-names: + minItems: 15 + maxItems: 15 + - if: properties: compatible: @@ -163,12 +211,26 @@ allOf: required: - reset-names else: + properties: + resets: + maxItems: 1 + + pcs-handle: false + + reset-names: false + + - if: + properties: + compatible: + contains: + const: renesas,rzv2h-gbeth + then: properties: clocks: - minItems: 7 + maxItems: 7 =20 clock-names: - minItems: 7 + maxItems: 7 =20 interrupts: minItems: 11 @@ -178,13 +240,6 @@ allOf: minItems: 11 maxItems: 11 =20 - resets: - maxItems: 1 - - pcs-handle: false - - reset-names: false - unevaluatedProperties: false =20 examples: diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Docume= ntation/devicetree/bindings/net/snps,dwmac.yaml index dd3c72e8363e..38bc34dc4f09 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -75,6 +75,7 @@ properties: - qcom,sc8280xp-ethqos - qcom,sm8150-ethqos - renesas,r9a06g032-gmac + - renesas,r9a08g046-gbeth - renesas,r9a09g077-gbeth - renesas,rzn1-gmac - renesas,rzv2h-gbeth @@ -142,6 +143,8 @@ properties: pattern: '^rx-queue-[0-7]$' - description: Per channel transmit completion interrupt pattern: '^tx-queue-[0-7]$' + - description: PPS interrupt + pattern: '^ptp-pps-[0-3]$' =20 clocks: minItems: 1 --=20 2.43.0 From nobody Sat Feb 7 05:53:39 2026 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60ADE350D44 for ; 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Wed, 28 Jan 2026 04:58:56 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:e29d:6e0e:72c1:d15d]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf2f3e26sm123344966b.67.2026.01.28.04.58.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 04:58:56 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Lad Prabhakar , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Biju Das Subject: [PATCH net-next 2/8] net: stmmac: dwmac-renesas-gbeth: Add support for RZ/G3L SoC Date: Wed, 28 Jan 2026 12:58:39 +0000 Message-ID: <20260128125850.425264-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260128125850.425264-1-biju.das.jz@bp.renesas.com> References: <20260128125850.425264-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Compared to other Renesas GBETH stmmac glue drivers, RZ/G3L GBETH IP use the version Synopsys DesignWare MAC (version 5.30). It has an extra clock compared to RZ/V2H and has ptp_pps_o interrupts. Add support for RZ/G3L GBETH by reusing device data of RZ/V2H and can be extended to add other functionalities later. Signed-off-by: Biju Das --- drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c b/dr= ivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c index be7f5eb2cdcf..19f34e18bfef 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-renesas-gbeth.c @@ -214,6 +214,7 @@ static const struct renesas_gbeth_of_data renesas_gmac_= of_data =3D { }; =20 static const struct of_device_id renesas_gbeth_match[] =3D { + { .compatible =3D "renesas,r9a08g046-gbeth", .data =3D &renesas_gbeth_of_= data }, { .compatible =3D "renesas,r9a09g077-gbeth", .data =3D &renesas_gmac_of_d= ata }, { .compatible =3D "renesas,rzv2h-gbeth", .data =3D &renesas_gbeth_of_data= }, { /* Sentinel */ } --=20 2.43.0 From nobody Sat Feb 7 05:53:39 2026 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E394A34FF59 for ; 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charset="utf-8" From: Biju Das Drop the unwanted check in rzg3s_cpg_pll_clk_recalc_rate() as the function is SoC specific. Signed-off-by: Biju Das --- drivers/clk/renesas/rzg2l-cpg.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 16771a0101bd..ee92d07c6ff7 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1113,9 +1113,6 @@ static unsigned long rzg3s_cpg_pll_clk_recalc_rate(st= ruct clk_hw *hw, u32 nir, nfr, mr, pr, val, setting; u64 rate; =20 - if (pll_clk->type !=3D CLK_TYPE_G3S_PLL) - return parent_rate; - setting =3D GET_REG_SAMPLL_SETTING(pll_clk->conf); if (setting) { val =3D readl(priv->base + setting); --=20 2.43.0 From nobody Sat Feb 7 05:53:39 2026 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60FE0352923 for ; Wed, 28 Jan 2026 12:58:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 28 Jan 2026 04:58:57 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:e29d:6e0e:72c1:d15d]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf2f3e26sm123344966b.67.2026.01.28.04.58.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 04:58:57 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH net-next 4/8] clk: renesas: rzg2l: Add support for enabling PLLs Date: Wed, 28 Jan 2026 12:58:41 +0000 Message-ID: <20260128125850.425264-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260128125850.425264-1-biju.das.jz@bp.renesas.com> References: <20260128125850.425264-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for enabling PLL clocks in the RZ/G3L CPG driver to turn off some PLLs, if they are not in use(eg: PLL6, PLL7) Introduce `is_enabled` and `enable` callbacks to handle PLL state transitions. With the `enable` callback, PLL will be turned ON only when the PLL consumer device is enabled; otherwise, it will remain off. Define new macros for PLL standby and monitor registers to facilitate this process. Signed-off-by: Biju Das --- drivers/clk/renesas/rzg2l-cpg.c | 67 +++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 4 ++ 2 files changed, 71 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index ee92d07c6ff7..dfb36e6e6a7b 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -58,6 +58,13 @@ #define RZG3S_DIV_NF GENMASK(12, 1) #define RZG3S_SEL_PLL BIT(0) =20 +#define RZG3L_PLL_STBY_OFFSET(x) (GET_REG_SAMPLL_CLK1(x) - 0x4) +#define RZG3L_PLL_STBY_RESETB BIT(0) +#define RZG3L_PLL_STBY_RESETB_WEN BIT(16) +#define RZG3L_PLL_MON_OFFSET(x) (GET_REG_SAMPLL_CLK1(x) + 0x8) +#define RZG3L_PLL_MON_RESETB BIT(0) +#define RZG3L_PLL_MON_LOCK BIT(4) + #define CLK_ON_R(reg) (reg) #define CLK_MON_R(reg) (0x180 + (reg)) #define CLK_RST_R(reg) (reg) @@ -1181,6 +1188,63 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk= *core, return pll_clk->hw.clk; } =20 +static int rzg3l_cpg_pll_clk_is_enabled(struct clk_hw *hw) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + struct rzg2l_cpg_priv *priv =3D pll_clk->priv; + u32 val =3D readl(priv->base + RZG3L_PLL_MON_OFFSET(pll_clk->conf)); + u32 mon_val =3D RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK; + + /* Ensure both RESETB and LOCK bits are set */ + return (mon_val =3D=3D (val & mon_val)); +} + +static int rzg3l_cpg_pll_clk_endisable(struct clk_hw *hw, bool enable) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + struct rzg2l_cpg_priv *priv =3D pll_clk->priv; + u32 stby_offset, mon_offset; + u32 val, mon_val; + int ret; + + stby_offset =3D RZG3L_PLL_STBY_OFFSET(pll_clk->conf); + mon_offset =3D RZG3L_PLL_MON_OFFSET(pll_clk->conf); + + if (enable) { + val =3D RZG3L_PLL_STBY_RESETB_WEN | RZG3L_PLL_STBY_RESETB; + mon_val =3D RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK; + } else { + val =3D RZG3L_PLL_STBY_RESETB_WEN; + mon_val =3D 0; + } + + writel(val, priv->base + stby_offset); + + /* ensure PLL is in normal/stanby mode */ + ret =3D readl_poll_timeout_atomic(priv->base + mon_offset, val, mon_val = =3D=3D + (val & (RZG3L_PLL_MON_RESETB | RZG3L_PLL_MON_LOCK)), + 10, 100); + if (ret) + dev_err(priv->dev, "Failed to %s PLL 0x%x/%pC\n", enable ? + "enable" : "disable", stby_offset, hw->clk); + + return ret; +} + +static int rzg3l_cpg_pll_clk_enable(struct clk_hw *hw) +{ + if (rzg3l_cpg_pll_clk_is_enabled(hw)) + return 0; + + return rzg3l_cpg_pll_clk_endisable(hw, true); +} + +static const struct clk_ops rzg3l_cpg_pll_ops =3D { + .is_enabled =3D rzg3l_cpg_pll_clk_is_enabled, + .enable =3D rzg3l_cpg_pll_clk_enable, + .recalc_rate =3D rzg3s_cpg_pll_clk_recalc_rate, +}; + static struct clk *rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec, void *data) @@ -1264,6 +1328,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk= *core, case CLK_TYPE_SAM_PLL: clk =3D rzg2l_cpg_pll_clk_register(core, priv, &rzg2l_cpg_pll_ops); break; + case CLK_TYPE_G3L_PLL: + clk =3D rzg2l_cpg_pll_clk_register(core, priv, &rzg3l_cpg_pll_ops); + break; case CLK_TYPE_G3S_PLL: clk =3D rzg2l_cpg_pll_clk_register(core, priv, &rzg3s_cpg_pll_ops); break; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 1db413bb433d..7de4cb7af1cc 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -123,6 +123,7 @@ enum clk_types { CLK_TYPE_IN, /* External Clock Input */ CLK_TYPE_FF, /* Fixed Factor Clock */ CLK_TYPE_SAM_PLL, + CLK_TYPE_G3L_PLL, CLK_TYPE_G3S_PLL, =20 /* Clock with divider */ @@ -152,6 +153,9 @@ enum clk_types { DEF_TYPE(_name, _id, _type, .parent =3D _parent) #define DEF_SAMPLL(_name, _id, _parent, _conf) \ DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent =3D _parent, .conf =3D _co= nf) +#define DEF_G3L_PLL(_name, _id, _parent, _conf, _default_rate) \ + DEF_TYPE(_name, _id, CLK_TYPE_G3L_PLL, .parent =3D _parent, .conf =3D _co= nf, \ + .default_rate =3D _default_rate) #define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \ DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent =3D _parent, .conf =3D _co= nf, \ .default_rate =3D _default_rate) --=20 2.43.0 From nobody Sat Feb 7 05:53:39 2026 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 127B535294B for ; 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charset="utf-8" From: Biju Das Add support for PLL6 clk by registering with rzg2l-cpg driver. Signed-off-by: Biju Das --- drivers/clk/renesas/r9a08g046-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index d77934872cf4..cc7d3872e9e4 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -29,6 +29,9 @@ #define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1) #define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1) =20 +/* PLL 1/4/6/7 configuration registers macro. */ +#define G3L_PLL1467_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12= | (setting)) + enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK =3D R9A08G046_CLK_P4_DIV2, @@ -45,6 +48,7 @@ enum clk_ids { CLK_PLL2_DIV2, CLK_PLL3, CLK_PLL3_DIV2, + CLK_PLL6, =20 /* Module Clocks */ MOD_CLK_BASE, @@ -78,6 +82,8 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __= initconst =3D { /* Internal Core Clocks */ DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), + DEF_G3L_PLL(".pll6", CLK_PLL6, CLK_EXTAL, G3L_PLL1467_CONF(0x54, 0x58, 0), + 500000000UL), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), =20 --=20 2.43.0 From nobody Sat Feb 7 05:53:39 2026 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E71EA350D76 for ; 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Wed, 28 Jan 2026 04:58:58 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:e29d:6e0e:72c1:d15d]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf2f3e26sm123344966b.67.2026.01.28.04.58.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 04:58:58 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH net-next 6/8] clk: renesas: r9a08g046: Add clock and reset signals for the GBETH IPs Date: Wed, 28 Jan 2026 12:58:43 +0000 Message-ID: <20260128125850.425264-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260128125850.425264-1-biju.das.jz@bp.renesas.com> References: <20260128125850.425264-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1) IPs found on the RZ/G3L SoC. This includes various dividers and mux clocks needed by these two GBETH IPs. Signed-off-by: Biju Das --- drivers/clk/renesas/r9a08g046-cpg.c | 114 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 6 ++ 2 files changed, 120 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index cc7d3872e9e4..e74bab2df29a 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -18,17 +18,35 @@ #define G3L_CPG_PL2_DDIV (0x204) #define G3L_CPG_PL3_DDIV (0x208) #define G3L_CLKDIVSTATUS (0x280) +#define G3L_CPG_ETH_SSEL (0x410) +#define G3L_CPG_ETH_SDIV (0x434) =20 /* RZ/G3L Specific division configuration. */ #define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2) #define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2) #define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2) +#define G3L_SDIV_ETH_A DDIV_PACK(G3L_CPG_ETH_SDIV, 0, 2) +#define G3L_SDIV_ETH_B DDIV_PACK(G3L_CPG_ETH_SDIV, 4, 1) +#define G3L_SDIV_ETH_C DDIV_PACK(G3L_CPG_ETH_SDIV, 8, 2) +#define G3L_SDIV_ETH_D DDIV_PACK(G3L_CPG_ETH_SDIV, 12, 1) =20 /* RZ/G3L Clock status configuration. */ #define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1) #define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1) #define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1) =20 +/* RZ/G3L Specific clocks select. */ +#define G3L_SEL_ETH0_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 0, 1) +#define G3L_SEL_ETH0_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 1, 1) +#define G3L_SEL_ETH0_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 2, 1) +#define G3L_SEL_ETH0_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 3, 1) +#define G3L_SEL_ETH0_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 4, 1) +#define G3L_SEL_ETH1_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 8, 1) +#define G3L_SEL_ETH1_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 9, 1) +#define G3L_SEL_ETH1_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 10, 1) +#define G3L_SEL_ETH1_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 11, 1) +#define G3L_SEL_ETH1_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 12, 1) + /* PLL 1/4/6/7 configuration registers macro. */ #define G3L_PLL1467_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12= | (setting)) =20 @@ -49,12 +67,29 @@ enum clk_ids { CLK_PLL3, CLK_PLL3_DIV2, CLK_PLL6, + CLK_PLL6_DIV10, + CLK_SEL_ETH0_TX, + CLK_SEL_ETH0_RX, + CLK_SEL_ETH0_RM, + CLK_SEL_ETH1_TX, + CLK_SEL_ETH1_RX, + CLK_SEL_ETH1_RM, + CLK_ETH0_TR, + CLK_ETH0_RM, + CLK_ETH1_TR, + CLK_ETH1_RM, =20 /* Module Clocks */ MOD_CLK_BASE, }; =20 /* Divider tables */ +static const struct clk_div_table dtable_2_20[] =3D { + { 0, 2 }, + { 1, 20 }, + { 0, 0 }, +}; + static const struct clk_div_table dtable_4_128[] =3D { { 0, 4 }, { 1, 2 }, @@ -63,6 +98,13 @@ static const struct clk_div_table dtable_4_128[] =3D { { 0, 0 }, }; =20 +static const struct clk_div_table dtable_4_200[] =3D { + { 0, 4 }, + { 1, 20 }, + { 2, 200 }, + { 0, 0 }, +}; + static const struct clk_div_table dtable_8_256[] =3D { { 0, 8 }, { 1, 16 }, @@ -71,6 +113,18 @@ static const struct clk_div_table dtable_8_256[] =3D { { 0, 0 }, }; =20 +/* Mux clock names tables. */ +static const char * const sel_eth0_tx[] =3D { ".div_eth0_tr", "eth0_txc_tx= _clk" }; +static const char * const sel_eth0_rx[] =3D { ".div_eth0_tr", "eth0_rxc_rx= _clk" }; +static const char * const sel_eth0_rm[] =3D { ".pll6_div10", "eth0_rxc_rx_= clk" }; +static const char * const sel_eth1_tx[] =3D { ".div_eth1_tr", "eth1_txc_tx= _clk" }; +static const char * const sel_eth1_rx[] =3D { ".div_eth1_tr", "eth1_rxc_rx= _clk" }; +static const char * const sel_eth1_rm[] =3D { ".pll6_div10", "eth1_rxc_rx_= clk" }; +static const char * const sel_eth0_clk_tx_i[] =3D { ".sel_eth0_tx", ".div_= eth0_rm" }; +static const char * const sel_eth0_clk_rx_i[] =3D { ".sel_eth0_rx", ".div_= eth0_rm" }; +static const char * const sel_eth1_clk_tx_i[] =3D { ".sel_eth1_tx", ".div_= eth1_rm" }; +static const char * const sel_eth1_clk_rx_i[] =3D { ".sel_eth1_rx", ".div_= eth1_rm" }; + static const struct cpg_core_clk r9a08g046_core_clks[] __initconst =3D { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -86,6 +140,17 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { 500000000UL), DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + DEF_FIXED(".pll6_div10", CLK_PLL6_DIV10, CLK_PLL6, 1, 10), + DEF_MUX(".sel_eth0_tx", CLK_SEL_ETH0_TX, G3L_SEL_ETH0_TX, sel_eth0_tx), + DEF_MUX(".sel_eth0_rx", CLK_SEL_ETH0_RX, G3L_SEL_ETH0_RX, sel_eth0_rx), + DEF_MUX(".sel_eth0_rm", CLK_SEL_ETH0_RM, G3L_SEL_ETH0_RM, sel_eth0_rm), + DEF_MUX(".sel_eth1_tx", CLK_SEL_ETH1_TX, G3L_SEL_ETH1_TX, sel_eth1_tx), + DEF_MUX(".sel_eth1_rx", CLK_SEL_ETH1_RX, G3L_SEL_ETH1_RX, sel_eth1_rx), + DEF_MUX(".sel_eth1_rm", CLK_SEL_ETH1_RM, G3L_SEL_ETH1_RM, sel_eth1_rm), + DEF_DIV(".div_eth0_tr", CLK_ETH0_TR, CLK_PLL6, G3L_SDIV_ETH_A, dtable_4_2= 00), + DEF_DIV(".div_eth1_tr", CLK_ETH1_TR, CLK_PLL6, G3L_SDIV_ETH_C, dtable_4_2= 00), + DEF_DIV(".div_eth0_rm", CLK_ETH0_RM, CLK_SEL_ETH0_RM, G3L_SDIV_ETH_B, dta= ble_2_20), + DEF_DIV(".div_eth1_rm", CLK_ETH1_RM, CLK_SEL_ETH1_RM, G3L_SDIV_ETH_D, dta= ble_2_20), =20 /* Core output clk */ DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL= 2B_STS, @@ -94,6 +159,21 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { dtable_4_128, 0, 0, 0, NULL), DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL= 2A_STS, dtable_4_128, 0, 0, 0, NULL), + DEF_FIXED("HP", R9A08G046_CLK_HP, CLK_PLL6_DIV10, 1, 1), + DEF_MUX_FLAGS("ETHTX01", R9A08G046_CLK_ETHTX01, G3L_SEL_ETH0_CLK_TX_I, se= l_eth0_clk_tx_i, + CLK_SET_RATE_PARENT), + DEF_MUX_FLAGS("ETHRX01", R9A08G046_CLK_ETHRX01, G3L_SEL_ETH0_CLK_RX_I, se= l_eth0_clk_rx_i, + CLK_SET_RATE_PARENT), + DEF_MUX_FLAGS("ETHTX11", R9A08G046_CLK_ETHTX11, G3L_SEL_ETH1_CLK_TX_I, se= l_eth1_clk_tx_i, + CLK_SET_RATE_PARENT), + DEF_MUX_FLAGS("ETHRX11", R9A08G046_CLK_ETHRX11, G3L_SEL_ETH1_CLK_RX_I, se= l_eth1_clk_rx_i, + CLK_SET_RATE_PARENT), + DEF_FIXED("ETHRM0", R9A08G046_CLK_ETHRM0, CLK_ETH0_RM, 1, 1), + DEF_FIXED("ETHTX02", R9A08G046_CLK_ETHTX02, CLK_SEL_ETH0_TX, 1, 1), + DEF_FIXED("ETHRX02", R9A08G046_CLK_ETHRX02, CLK_SEL_ETH0_RX, 1, 1), + DEF_FIXED("ETHRM1", R9A08G046_CLK_ETHRM1, CLK_ETH1_RM, 1, 1), + DEF_FIXED("ETHTX12", R9A08G046_CLK_ETHTX12, CLK_SEL_ETH1_TX, 1, 1), + DEF_FIXED("ETHRX12", R9A08G046_CLK_ETHRX12, CLK_SEL_ETH1_RX, 1, 1), }; =20 static const struct rzg2l_mod_clk r9a08g046_mod_clks[] =3D { @@ -107,6 +187,38 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[]= =3D { MSTOP(BUS_REG1, BIT(2))), DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1, MSTOP(BUS_REG1, BIT(3))), + DEF_MOD("eth0_clk_axi", R9A08G046_ETH0_CLK_AXI, R9A08G046_CLK_P1, 0x57c,= 0, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_MOD("eth1_clk_axi", R9A08G046_ETH1_CLK_AXI, R9A08G046_CLK_P1, 0x57c,= 1, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_MOD("eth0_clk_chi", R9A08G046_ETH0_CLK_CHI, R9A08G046_CLK_P1, 0x57c,= 2, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_MOD("eth1_clk_chi", R9A08G046_ETH1_CLK_CHI, R9A08G046_CLK_P1, 0x57c,= 3, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth0_tx_i", R9A08G046_ETH0_CLK_TX_I, R9A08G046_CLK_ETHTX01, = 0x57c, 4, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth0_tx_180_i", R9A08G046_ETH0_CLK_TX_180_I, R9A08G046_CLK_E= THTX02, 0x57c, 4, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth1_tx_i", R9A08G046_ETH1_CLK_TX_I, R9A08G046_CLK_ETHTX11, = 0x57c, 5, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_COUPLED("eth1_tx_180_i", R9A08G046_ETH1_CLK_TX_180_I, R9A08G046_CLK_E= THTX12, 0x57c, 5, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_COUPLED("eth0_rx_i", R9A08G046_ETH0_CLK_RX_I, R9A08G046_CLK_ETHRX01, = 0x57c, 6, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth0_rx_180_i", R9A08G046_ETH0_CLK_RX_180_I, R9A08G046_CLK_E= THRX02, 0x57c, 6, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_COUPLED("eth1_rx_i", R9A08G046_ETH1_CLK_RX_I, R9A08G046_CLK_ETHRX11, = 0x57c, 7, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_COUPLED("eth1_rx_180_i", R9A08G046_ETH1_CLK_RX_180_I, R9A08G046_CLK_E= THRX12, 0x57c, 7, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_MOD("eth0_ptp_ref_i", R9A08G046_ETH0_CLK_PTP_REF_I, R9A08G046_CLK_HP,= 0x57c, 8, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_MOD("eth1_ptp_ref_i", R9A08G046_ETH1_CLK_PTP_REF_I, R9A08G046_CLK_HP,= 0x57c, 9, + MSTOP(BUS_PERI_COM, BIT(3))), + DEF_MOD("eth0_rmii_i", R9A08G046_ETH0_CLK_RMII_I, R9A08G046_CLK_ETHRM0, = 0x57c, 10, + MSTOP(BUS_PERI_COM, BIT(2))), + DEF_MOD("eth1_rmii_i", R9A08G046_ETH1_CLK_RMII_I, R9A08G046_CLK_ETHRM1, = 0x57c, 11, + MSTOP(BUS_PERI_COM, BIT(3))), DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584= , 0, MSTOP(BUS_MCPU2, BIT(1))), }; @@ -117,6 +229,8 @@ static const struct rzg2l_reset r9a08g046_resets[] =3D { DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0), DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0), DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0), + DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1), DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0), }; =20 diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 7de4cb7af1cc..9abb53483759 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -188,6 +188,12 @@ enum clk_types { .parent_names =3D _parent_names, \ .num_parents =3D ARRAY_SIZE(_parent_names), \ .mux_flags =3D CLK_MUX_READ_ONLY) +#define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flag) \ + DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf =3D _conf, \ + .parent_names =3D _parent_names, \ + .num_parents =3D ARRAY_SIZE(_parent_names), \ + .mux_flags =3D CLK_MUX_HIWORD_MASK, \ + .flag =3D _flag) #define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk= _flags, _notifier) \ DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf =3D _conf, .sconf =3D _sconf,= \ .parent_names =3D _parent_names, \ --=20 2.43.0 From nobody Sat Feb 7 05:53:39 2026 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A004E352C40 for ; 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charset="utf-8" From: Biju Das Renesas RZ/G3L SoC is equipped with 2x Synopsys DesignWare Ethernet (10/100/1000 BASE) with TSN, IP block version 5.30. Add GBETH nodes to R9A08G046 RZ/G3L SoC DTSI. Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 237 +++++++++++++++++++++ 1 file changed, 237 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi index 0922ad642c67..231b118ecc62 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -228,6 +228,236 @@ sdhi1: mmc@11c10000 { /* placeholder */ }; =20 + eth0: ethernet@11c30000 { + compatible =3D "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a"; + reg =3D <0 0x11c30000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3", "ptp-pps-0", + "ptp-pps-1", "ptp-pps-2", "ptp-pps-3"; + clocks =3D <&cpg CPG_MOD R9A08G046_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_CHI>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_PTP_REF_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_TX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH0_CLK_RMII_I>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180", + "rmii"; + resets =3D <&cpg R9A08G046_ETH0_ARESET_N>; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <128>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup0>; + snps,mtl-tx-config =3D <&mtl_tx_setup0>; + snps,txpbl =3D <32>; + snps,rxpbl =3D <32>; + status =3D "disabled"; + + mdio0: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup0: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + }; + + mtl_tx_setup0: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + snps,tx-sched-wrr; + + queue0 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,weight =3D <0x12>; + snps,dcb-algorithm; + snps,priority =3D <0x2>; + }; + + queue2 { + snps,weight =3D <0x14>; + snps,dcb-algorithm; + snps,priority =3D <0x4>; + }; + + queue3 { + snps,weight =3D <0x18>; + snps,dcb-algorithm; + snps,priority =3D <0x8>; + }; + }; + }; + + eth1: ethernet@11c40000 { + compatible =3D "renesas,r9a08g046-gbeth", "snps,dwmac-5.30a"; + reg =3D <0 0x11c40000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "macirq", "eth_wake_irq", "eth_lpi", + "rx-queue-0", "rx-queue-1", "rx-queue-2", + "rx-queue-3", "tx-queue-0", "tx-queue-1", + "tx-queue-2", "tx-queue-3", "ptp-pps-0", + "ptp-pps-1", "ptp-pps-2", "ptp-pps-3"; + clocks =3D <&cpg CPG_MOD R9A08G046_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_CHI>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_PTP_REF_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_TX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RX_180_I>, + <&cpg CPG_MOD R9A08G046_ETH1_CLK_RMII_I>; + clock-names =3D "stmmaceth", "pclk", "ptp_ref", + "tx", "rx", "tx-180", "rx-180", + "rmii"; + resets =3D <&cpg R9A08G046_ETH1_ARESET_N>; + power-domains =3D <&cpg>; + snps,multicast-filter-bins =3D <256>; + snps,perfect-filter-entries =3D <128>; + rx-fifo-depth =3D <8192>; + tx-fifo-depth =3D <8192>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup1>; + snps,mtl-tx-config =3D <&mtl_tx_setup1>; + snps,txpbl =3D <32>; + snps,rxpbl =3D <32>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority =3D <0x1>; + snps,map-to-dma-channel =3D <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority =3D <0x2>; + snps,map-to-dma-channel =3D <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority =3D <0x4>; + snps,map-to-dma-channel =3D <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority =3D <0x8>; + snps,map-to-dma-channel =3D <3>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + snps,tx-sched-wrr; + + queue0 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,weight =3D <0x12>; + snps,dcb-algorithm; + snps,priority =3D <0x2>; + }; + + queue2 { + snps,weight =3D <0x14>; + snps,dcb-algorithm; + snps,priority =3D <0x4>; + }; + + queue3 { + snps,weight =3D <0x18>; + snps,dcb-algorithm; + snps,priority =3D <0x8>; + }; + }; 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Wed, 28 Jan 2026 04:59:00 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:e29d:6e0e:72c1:d15d]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf2f3e26sm123344966b.67.2026.01.28.04.58.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 04:58:59 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH net-next 8/8] arm64: dts: renesas: rzg3l-smarc-som: Enable eth0 (GBETH) interface Date: Wed, 28 Jan 2026 12:58:45 +0000 Message-ID: <20260128125850.425264-9-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260128125850.425264-1-biju.das.jz@bp.renesas.com> References: <20260128125850.425264-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Enable the Gigabit Ethernet Interfaces (GBETH) populated on the RZ/G3L SMARC EVK. The eth1, pincontrol definitions and hotplug support will be added later. Signed-off-by: Biju Das --- .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3l-smarc-som.dtsi index 7c21afaee9bc..f52af01a7eff 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -8,6 +8,10 @@ / { compatible =3D "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r= 9a08g046"; =20 + aliases { + ethernet0 =3D ð0; + }; + memory@48000000 { device_type =3D "memory"; /* First 128MB is reserved for secure area. */ @@ -15,6 +19,37 @@ memory@48000000 { }; }; =20 +ð0 { + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + + status =3D "okay"; +}; + +ð0_rxc_rx_clk { + clock-frequency =3D <125000000>; +}; + &extal_clk { clock-frequency =3D <24000000>; }; + +&mdio0 { + phy0: ethernet-phy@7 { + compatible =3D "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + rxc-skew-psec =3D <1400>; + txc-skew-psec =3D <1400>; + rxdv-skew-psec =3D <0>; + txdv-skew-psec =3D <0>; + rxd0-skew-psec =3D <0>; + rxd1-skew-psec =3D <0>; + rxd2-skew-psec =3D <0>; + rxd3-skew-psec =3D <0>; + txd0-skew-psec =3D <0>; + txd1-skew-psec =3D <0>; + txd2-skew-psec =3D <0>; + txd3-skew-psec =3D <0>; + }; +}; --=20 2.43.0