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Wed, 28 Jan 2026 03:30:37 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Fabrizio Castro , Conor Dooley Subject: [PATCH v2 01/10] dt-bindings: dma: rz-dmac: Document RZ/G3L SoC Date: Wed, 28 Jan 2026 11:30:20 +0000 Message-ID: <20260128113032.337231-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260128113032.337231-1-biju.das.jz@bp.renesas.com> References: <20260128113032.337231-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Document the Renesas RZ/G3L DMAC block. This is identical to the one found on the RZ/G3S SoC. Reviewed-by: Fabrizio Castro Acked-by: Conor Dooley Signed-off-by: Biju Das --- v1->v2: * Collected tags. --- Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/D= ocumentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index d137b9cbaee9..e3311029eb2f 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -19,6 +19,7 @@ properties: - renesas,r9a07g044-dmac # RZ/G2{L,LC} - renesas,r9a07g054-dmac # RZ/V2L - renesas,r9a08g045-dmac # RZ/G3S + - renesas,r9a08g046-dmac # RZ/G3L - const: renesas,rz-dmac =20 - items: --=20 2.43.0 From nobody Sat Feb 7 05:49:10 2026 Received: from mail-ed1-f67.google.com (mail-ed1-f67.google.com [209.85.208.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1ECB733D51D for ; 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charset="utf-8" From: Biju Das Document Renesas RZ/G3L (R9A08G046) SoC variants and the Renesas RZ/G3L SMARC Carrier-II EVK board which is based on the Renesas RZ/G3L SMARC SoM. The RZ/G3L SMARC Carrier-II EVK consists of an RZ/G3L SoM module and a SMARC Carrier-II carrier board. The SoM module sits on top of the carrier board. Reviewed-by: Fabrizio Castro Signed-off-by: Biju Das --- v1->v2: * Squashed the patch#3 and #4 * Documented GE3D/VCP for all SoC variants * Collected tag --- .../devicetree/bindings/soc/renesas/renesas.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/D= ocumentation/devicetree/bindings/soc/renesas/renesas.yaml index f4947ac65460..5c22c51b1533 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -548,6 +548,19 @@ properties: - const: renesas,r9a08g045s33 # PCIe support - const: renesas,r9a08g045 =20 + - description: RZ/G3L (R9A08G046) + items: + - enum: + - renesas,smarc2-evk # RZ SMARC Carrier-II EVK + - enum: + - renesas,rzg3l-smarcm # RZ/G3L SMARC Module (SoM) + - enum: + - renesas,r9a08g046l26 # Dual Cortex-A55 + Cortex-M33 + GE3D= /VCP (14mm LFBGA) + - renesas,r9a08g046l28 # Dual Cortex-A55 + Cortex-M33 + GE3D= /VCP (17mm LFBGA) + - renesas,r9a08g046l46 # Quad Cortex-A55 + Cortex-M33 + GE3D= /VCP (14mm LFBGA) + - renesas,r9a08g046l48 # Quad Cortex-A55 + Cortex-M33 + GE3D= /VCP (17mm LFBGA) + - const: renesas,r9a08g046 + - description: RZ/V2M (R9A09G011) items: - enum: --=20 2.43.0 From nobody Sat Feb 7 05:49:10 2026 Received: from mail-ej1-f66.google.com (mail-ej1-f66.google.com [209.85.218.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C586534D4D8 for ; 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charset="utf-8" From: Biju Das Document RZ/G3L (R9A08G046) SYSC bindings. The SYSC block found on the RZ/G3L SoC is similar to the one found on the RZ/G3S. Acked-by: Conor Dooley Signed-off-by: Biju Das --- v1->v2: * Collected tag. --- .../devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sy= sc.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.= yaml index 4386b2c3fa4d..94ae72eb8fb6 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml @@ -24,6 +24,7 @@ properties: - renesas,r9a07g044-sysc # RZ/G2{L,LC} - renesas,r9a07g054-sysc # RZ/V2L - renesas,r9a08g045-sysc # RZ/G3S + - renesas,r9a08g046-sysc # RZ/G3L =20 reg: maxItems: 1 --=20 2.43.0 From nobody Sat Feb 7 05:49:10 2026 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 824C72D63E8 for ; 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charset="utf-8" From: Biju Das Add SoC identification for the RZ/G3L SoC using the System Controller (SYSC) block. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/soc/renesas/Kconfig | 12 ++++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r9a08g046-sysc.c | 91 ++++++++++++++++++++++++++++ drivers/soc/renesas/rz-sysc.c | 3 + drivers/soc/renesas/rz-sysc.h | 1 + 5 files changed, 108 insertions(+) create mode 100644 drivers/soc/renesas/r9a08g046-sysc.c diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 1e50dc7c31cd..26bed0fdceb0 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -390,6 +390,14 @@ config ARCH_R9A08G045 help This enables support for the Renesas RZ/G3S SoC variants. =20 +config ARCH_R9A08G046 + bool "ARM64 Platform support for R9A08G046 (RZ/G3L)" + default y if ARCH_RENESAS + select ARCH_RZG2L + select SYSC_R9A08G046 + help + This enables support for the Renesas RZ/G3L SoC variants. + config ARCH_R9A09G011 bool "ARM64 Platform support for R9A09G011 (RZ/V2M)" default y if ARCH_RENESAS @@ -474,6 +482,10 @@ config SYSC_R9A08G045 bool "Renesas System controller support for R9A08G045 (RZ/G3S)" if COMPIL= E_TEST select SYSC_RZ =20 +config SYSC_R9A08G046 + bool "Renesas System controller support for R9A08G046 (RZ/G3L)" if COMPIL= E_TEST + select SYSC_RZ + config SYS_R9A09G047 bool "Renesas System controller support for R9A09G047 (RZ/G3E)" if COMPIL= E_TEST select SYSC_RZ diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 33d44d964d61..655dbcb08747 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -7,6 +7,7 @@ ifdef CONFIG_SMP obj-$(CONFIG_ARCH_R9A06G032) +=3D r9a06g032-smp.o endif obj-$(CONFIG_SYSC_R9A08G045) +=3D r9a08g045-sysc.o +obj-$(CONFIG_SYSC_R9A08G046) +=3D r9a08g046-sysc.o obj-$(CONFIG_SYS_R9A09G047) +=3D r9a09g047-sys.o obj-$(CONFIG_SYS_R9A09G056) +=3D r9a09g056-sys.o obj-$(CONFIG_SYS_R9A09G057) +=3D r9a09g057-sys.o diff --git a/drivers/soc/renesas/r9a08g046-sysc.c b/drivers/soc/renesas/r9a= 08g046-sysc.c new file mode 100644 index 000000000000..fd98df196d0a --- /dev/null +++ b/drivers/soc/renesas/r9a08g046-sysc.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3L System controller (SYSC) driver + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include +#include +#include + +#include "rz-sysc.h" + +#define SYS_XSPI_MAP_STAADD_CS0 0x348 +#define SYS_XSPI_MAP_ENDADD_CS0 0x34c +#define SYS_XSPI_MAP_STAADD_CS1 0x350 +#define SYS_XSPI_MAP_ENDADD_CS1 0x354 +#define SYS_GETH0_CFG 0x380 +#define SYS_GETH1_CFG 0x390 +#define SYS_PCIE_CFG 0x3a0 +#define SYS_PCIE_MON 0x3a4 +#define SYS_PCIE_PHY 0x3b4 +#define SYS_I2C0_CFG 0x400 +#define SYS_I2C1_CFG 0x410 +#define SYS_I2C2_CFG 0x420 +#define SYS_I2C3_CFG 0x430 +#define SYS_I3C_CFG 0x440 +#define SYS_PWRRDY_N 0xd70 +#define SYS_IPCONT_SEL_CLONECH 0xe2c + +static bool rzg3l_regmap_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case SYS_XSPI_MAP_STAADD_CS0: + case SYS_XSPI_MAP_ENDADD_CS0: + case SYS_XSPI_MAP_STAADD_CS1: + case SYS_XSPI_MAP_ENDADD_CS1: + case SYS_GETH0_CFG: + case SYS_GETH1_CFG: + case SYS_PCIE_CFG: + case SYS_PCIE_MON: + case SYS_PCIE_PHY: + case SYS_I2C0_CFG: + case SYS_I2C1_CFG: + case SYS_I2C2_CFG: + case SYS_I2C3_CFG: + case SYS_I3C_CFG: + case SYS_PWRRDY_N: + case SYS_IPCONT_SEL_CLONECH: + return true; + default: + return false; + } +} + +static bool rzg3l_regmap_writeable_reg(struct device *dev, unsigned int re= g) +{ + switch (reg) { + case SYS_XSPI_MAP_STAADD_CS0: + case SYS_XSPI_MAP_ENDADD_CS0: + case SYS_XSPI_MAP_STAADD_CS1: + case SYS_XSPI_MAP_ENDADD_CS1: + case SYS_PCIE_CFG: + case SYS_PCIE_PHY: + case SYS_I2C0_CFG: + case SYS_I2C1_CFG: + case SYS_I2C2_CFG: + case SYS_I2C3_CFG: + case SYS_I3C_CFG: + case SYS_PWRRDY_N: + case SYS_IPCONT_SEL_CLONECH: + return true; + default: + return false; + } +} + +static const struct rz_sysc_soc_id_init_data rzg3l_sysc_soc_id_init_data _= _initconst =3D { + .family =3D "RZ/G3L", + .id =3D 0x87d9447, + .devid_offset =3D 0xa04, + .revision_mask =3D GENMASK(31, 28), + .specific_id_mask =3D GENMASK(27, 0), +}; + +const struct rz_sysc_init_data rzg3l_sysc_init_data __initconst =3D { + .soc_id_init_data =3D &rzg3l_sysc_soc_id_init_data, + .readable_reg =3D rzg3l_regmap_readable_reg, + .writeable_reg =3D rzg3l_regmap_writeable_reg, + .max_register =3D 0xe2c, +}; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index ae727d9c8cc5..0d3b7f52f846 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -88,6 +88,9 @@ static const struct of_device_id rz_sysc_match[] =3D { #ifdef CONFIG_SYSC_R9A08G045 { .compatible =3D "renesas,r9a08g045-sysc", .data =3D &rzg3s_sysc_init_da= ta }, #endif +#ifdef CONFIG_SYSC_R9A08G046 + { .compatible =3D "renesas,r9a08g046-sysc", .data =3D &rzg3l_sysc_init_da= ta }, +#endif #ifdef CONFIG_SYS_R9A09G047 { .compatible =3D "renesas,r9a09g047-sys", .data =3D &rzg3e_sys_init_data= }, #endif diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index 88929bf21cb1..921ee0d26c47 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -46,6 +46,7 @@ struct rz_sysc_init_data { }; =20 extern const struct rz_sysc_init_data rzg3e_sys_init_data; +extern const struct rz_sysc_init_data rzg3l_sysc_init_data; extern const struct rz_sysc_init_data rzg3s_sysc_init_data; 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Wed, 28 Jan 2026 03:30:39 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Conor Dooley Subject: [PATCH v2 05/10] dt-bindings: clock: Document RZ/G3L SoC Date: Wed, 28 Jan 2026 11:30:24 +0000 Message-ID: <20260128113032.337231-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260128113032.337231-1-biju.das.jz@bp.renesas.com> References: <20260128113032.337231-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Document the device tree bindings for the Renesas RZ/G3L SoC Clock Pulse Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has 5 clocks compared to 1 clock on other SoCs. Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clock, module clock outputs, as listed in section 4.4.2 ("Clock List r1.00") and add Reset definitions referring to registers CPG_RST_* in Section 4.4.3 ("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025). Acked-by: Conor Dooley Signed-off-by: Biju Das --- v1->v2: * Documented external ethernet clocks as it is a clock source for MUX inside CPG * Updated commit description. * Keep the tag from Conor as it is trivial change for adding more clks. --- .../bindings/clock/renesas,rzg2l-cpg.yaml | 40 ++- include/dt-bindings/clock/r9a08g046-cpg.h | 339 ++++++++++++++++++ 2 files changed, 374 insertions(+), 5 deletions(-) create mode 100644 include/dt-bindings/clock/r9a08g046-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml= b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index 8c18616e5c4d..c0ce687d83ee 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -28,19 +28,30 @@ properties: - renesas,r9a07g044-cpg # RZ/G2{L,LC} - renesas,r9a07g054-cpg # RZ/V2L - renesas,r9a08g045-cpg # RZ/G3S + - renesas,r9a08g046-cpg # RZ/G3L - renesas,r9a09g011-cpg # RZ/V2M =20 reg: maxItems: 1 =20 clocks: - maxItems: 1 + minItems: 1 + items: + - description: Clock source to CPG can be either from external clock + input (EXCLK) or crystal oscillator (XIN/XOUT). + - description: ETH0 TXC clock input + - description: ETH0 RXC clock input + - description: ETH1 TXC clock input + - description: ETH1 RXC clock input =20 clock-names: - description: - Clock source to CPG can be either from external clock input (EXCLK) = or - crystal oscillator (XIN/XOUT). - const: extal + minItems: 1 + items: + - const: extal + - const: eth0_txc_tx_clk + - const: eth0_rxc_rx_clk + - const: eth1_txc_tx_clk + - const: eth1_rxc_rx_clk =20 '#clock-cells': description: | @@ -74,6 +85,25 @@ required: - '#power-domain-cells' - '#reset-cells' =20 +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a08g046-cpg + then: + properties: + clocks: + minItems: 5 + clock-names: + minItems: 5 + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + additionalProperties: false =20 examples: diff --git a/include/dt-bindings/clock/r9a08g046-cpg.h b/include/dt-binding= s/clock/r9a08g046-cpg.h new file mode 100644 index 000000000000..d8304a73efdf --- /dev/null +++ b/include/dt-bindings/clock/r9a08g046-cpg.h @@ -0,0 +1,339 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__ + +#include + +/* R9A08G046 CPG Core Clocks */ +#define R9A08G046_CLK_I 0 +#define R9A08G046_CLK_IC0 1 +#define R9A08G046_CLK_IC1 2 +#define R9A08G046_CLK_IC2 3 +#define R9A08G046_CLK_IC3 4 +#define R9A08G046_CLK_P0 5 +#define R9A08G046_CLK_P1 6 +#define R9A08G046_CLK_P2 7 +#define R9A08G046_CLK_P3 8 +#define R9A08G046_CLK_P4 9 +#define R9A08G046_CLK_P5 10 +#define R9A08G046_CLK_P6 11 +#define R9A08G046_CLK_P7 12 +#define R9A08G046_CLK_P8 13 +#define R9A08G046_CLK_P9 14 +#define R9A08G046_CLK_P10 15 +#define R9A08G046_CLK_P13 16 +#define R9A08G046_CLK_P14 17 +#define R9A08G046_CLK_P15 18 +#define R9A08G046_CLK_P16 19 +#define R9A08G046_CLK_P17 20 +#define R9A08G046_CLK_P18 21 +#define R9A08G046_CLK_P19 22 +#define R9A08G046_CLK_P20 23 +#define R9A08G046_CLK_M0 24 +#define R9A08G046_CLK_M1 25 +#define R9A08G046_CLK_M2 26 +#define R9A08G046_CLK_M3 27 +#define R9A08G046_CLK_M4 28 +#define R9A08G046_CLK_M5 29 +#define R9A08G046_CLK_M6 30 +#define R9A08G046_CLK_AT 31 +#define R9A08G046_CLK_B 32 +#define R9A08G046_CLK_ETHTX01 33 +#define R9A08G046_CLK_ETHTX02 34 +#define R9A08G046_CLK_ETHRX01 35 +#define R9A08G046_CLK_ETHRX02 36 +#define R9A08G046_CLK_ETHRM0 37 +#define R9A08G046_CLK_ETHTX11 38 +#define R9A08G046_CLK_ETHTX12 39 +#define R9A08G046_CLK_ETHRX11 40 +#define R9A08G046_CLK_ETHRX12 41 +#define R9A08G046_CLK_ETHRM1 42 +#define R9A08G046_CLK_G 43 +#define R9A08G046_CLK_HP 44 +#define R9A08G046_CLK_SD0 45 +#define R9A08G046_CLK_SD1 46 +#define R9A08G046_CLK_SD2 47 +#define R9A08G046_CLK_SPI0 48 +#define R9A08G046_CLK_SPI1 49 +#define R9A08G046_CLK_S0 50 +#define R9A08G046_CLK_SWD 51 +#define R9A08G046_OSCCLK 52 +#define R9A08G046_OSCCLK2 53 +#define R9A08G046_CLK_P4_DIV2 54 + +/* R9A08G046 Module Clocks */ +#define R9A08G046_CA55_SCLK 0 +#define R9A08G046_CA55_PCLK 1 +#define R9A08G046_CA55_ATCLK 2 +#define R9A08G046_CA55_GICCLK 3 +#define R9A08G046_CA55_PERICLK 4 +#define R9A08G046_CA55_ACLK 5 +#define R9A08G046_CA55_TSCLK 6 +#define R9A08G046_CA55_CORECLK0 7 +#define R9A08G046_CA55_CORECLK1 8 +#define R9A08G046_CA55_CORECLK2 9 +#define R9A08G046_CA55_CORECLK3 10 +#define R9A08G046_SRAM_ACPU_ACLK0 11 +#define R9A08G046_SRAM_ACPU_ACLK1 12 +#define R9A08G046_SRAM_ACPU_ACLK2 13 +#define R9A08G046_GIC600_GICCLK 14 +#define R9A08G046_IA55_CLK 15 +#define R9A08G046_IA55_PCLK 16 +#define R9A08G046_MHU_PCLK 17 +#define R9A08G046_SYC_CNT_CLK 18 +#define R9A08G046_DMAC_ACLK 19 +#define R9A08G046_DMAC_PCLK 20 +#define R9A08G046_OSTM0_PCLK 21 +#define R9A08G046_OSTM1_PCLK 22 +#define R9A08G046_OSTM2_PCLK 23 +#define R9A08G046_MTU_X_MCK_MTU3 24 +#define R9A08G046_POE3_CLKM_POE 25 +#define R9A08G046_GPT_PCLK 26 +#define R9A08G046_POEG_A_CLKP 27 +#define R9A08G046_POEG_B_CLKP 28 +#define R9A08G046_POEG_C_CLKP 29 +#define R9A08G046_POEG_D_CLKP 30 +#define R9A08G046_WDT0_PCLK 31 +#define R9A08G046_WDT0_CLK 32 +#define R9A08G046_WDT1_PCLK 33 +#define R9A08G046_WDT1_CLK 34 +#define R9A08G046_WDT2_PCLK 35 +#define R9A08G046_WDT2_CLK 36 +#define R9A08G046_XSPI_HCLK 37 +#define R9A08G046_XSPI_ACLK 38 +#define R9A08G046_XSPI_CLK 39 +#define R9A08G046_XSPI_CLKX2 40 +#define R9A08G046_SDHI0_IMCLK 41 +#define R9A08G046_SDHI0_IMCLK2 42 +#define R9A08G046_SDHI0_CLK_HS 43 +#define R9A08G046_SDHI0_IACLKS 44 +#define R9A08G046_SDHI0_IACLKM 45 +#define R9A08G046_SDHI1_IMCLK 46 +#define R9A08G046_SDHI1_IMCLK2 47 +#define R9A08G046_SDHI1_CLK_HS 48 +#define R9A08G046_SDHI1_IACLKS 49 +#define R9A08G046_SDHI1_IACLKM 50 +#define R9A08G046_SDHI2_IMCLK 51 +#define R9A08G046_SDHI2_IMCLK2 52 +#define R9A08G046_SDHI2_CLK_HS 53 +#define R9A08G046_SDHI2_IACLKS 54 +#define R9A08G046_SDHI2_IACLKM 55 +#define R9A08G046_GE3D_CLK 56 +#define R9A08G046_GE3D_AXI_CLK 57 +#define R9A08G046_GE3D_ACE_CLK 58 +#define R9A08G046_ISU_ACLK 59 +#define R9A08G046_ISU_PCLK 60 +#define R9A08G046_H264_CLK_A 61 +#define R9A08G046_H264_CLK_P 62 +#define R9A08G046_CRU_SYSCLK 63 +#define R9A08G046_CRU_VCLK 64 +#define R9A08G046_CRU_PCLK 65 +#define R9A08G046_CRU_ACLK 66 +#define R9A08G046_MIPI_DSI_PLLCLK 67 +#define R9A08G046_MIPI_DSI_SYSCLK 68 +#define R9A08G046_MIPI_DSI_ACLK 69 +#define R9A08G046_MIPI_DSI_PCLK 70 +#define R9A08G046_MIPI_DSI_VCLK 71 +#define R9A08G046_MIPI_DSI_LPCLK 72 +#define R9A08G046_LVDS_PLLCLK 73 +#define R9A08G046_LVDS_CLK_DOT0 74 +#define R9A08G046_LVDS_PCLK 75 +#define R9A08G046_LCDC_CLK_A 76 +#define R9A08G046_LCDC_CLK_D 77 +#define R9A08G046_LCDC_CLK_P 78 +#define R9A08G046_SSI0_PCLK2 79 +#define R9A08G046_SSI0_PCLK_SFR 80 +#define R9A08G046_SSI1_PCLK2 81 +#define R9A08G046_SSI1_PCLK_SFR 82 +#define R9A08G046_SSI2_PCLK2 83 +#define R9A08G046_SSI2_PCLK_SFR 84 +#define R9A08G046_SSI3_PCLK2 85 +#define R9A08G046_SSI3_PCLK_SFR 86 +#define R9A08G046_USB_U2H0_HCLK 87 +#define R9A08G046_USB_U2H1_HCLK 88 +#define R9A08G046_USB_U2P0_EXR_CPUCLK 89 +#define R9A08G046_USB_U2P1_EXR_CPUCLK 90 +#define R9A08G046_USB_PCLK 91 +#define R9A08G046_USB_SCLK 92 +#define R9A08G046_ETH0_CLK_AXI 93 +#define R9A08G046_ETH0_CLK_CHI 94 +#define R9A08G046_ETH0_CLK_TX_I 95 +#define R9A08G046_ETH0_CLK_RX_I 96 +#define R9A08G046_ETH0_CLK_TX_180_I 97 +#define R9A08G046_ETH0_CLK_RX_180_I 98 +#define R9A08G046_ETH0_CLK_RMII_I 99 +#define R9A08G046_ETH0_CLK_PTP_REF_I 100 +#define R9A08G046_ETH1_CLK_AXI 101 +#define R9A08G046_ETH1_CLK_CHI 102 +#define R9A08G046_ETH1_CLK_TX_I 103 +#define R9A08G046_ETH1_CLK_RX_I 104 +#define R9A08G046_ETH1_CLK_TX_180_I 105 +#define R9A08G046_ETH1_CLK_RX_180_I 106 +#define R9A08G046_ETH1_CLK_RMII_I 107 +#define R9A08G046_ETH1_CLK_PTP_REF_I 108 +#define R9A08G046_I2C0_PCLK 109 +#define R9A08G046_I2C1_PCLK 110 +#define R9A08G046_I2C2_PCLK 111 +#define R9A08G046_I2C3_PCLK 112 +#define R9A08G046_SCIF0_CLK_PCK 113 +#define R9A08G046_SCIF1_CLK_PCK 114 +#define R9A08G046_SCIF2_CLK_PCK 115 +#define R9A08G046_SCIF3_CLK_PCK 116 +#define R9A08G046_SCIF4_CLK_PCK 117 +#define R9A08G046_SCIF5_CLK_PCK 118 +#define R9A08G046_RSCI0_PCLK 119 +#define R9A08G046_RSCI0_TCLK 120 +#define R9A08G046_RSCI1_PCLK 121 +#define R9A08G046_RSCI1_TCLK 122 +#define R9A08G046_RSCI2_PCLK 123 +#define R9A08G046_RSCI2_TCLK 124 +#define R9A08G046_RSCI3_PCLK 125 +#define R9A08G046_RSCI3_TCLK 126 +#define R9A08G046_RSPI0_PCLK 127 +#define R9A08G046_RSPI0_TCLK 128 +#define R9A08G046_RSPI1_PCLK 129 +#define R9A08G046_RSPI1_TCLK 130 +#define R9A08G046_RSPI2_PCLK 131 +#define R9A08G046_RSPI2_TCLK 132 +#define R9A08G046_CANFD_PCLK 133 +#define R9A08G046_CANFD_CLK_RAM 134 +#define R9A08G046_GPIO_HCLK 135 +#define R9A08G046_ADC0_ADCLK 136 +#define R9A08G046_ADC0_PCLK 137 +#define R9A08G046_ADC1_ADCLK 138 +#define R9A08G046_ADC1_PCLK 139 +#define R9A08G046_TSU_PCLK 140 +#define R9A08G046_PDM_PCLK 141 +#define R9A08G046_PDM_CCLK 142 +#define R9A08G046_PCI_ACLK 143 +#define R9A08G046_PCI_CLKL1PM 144 +#define R9A08G046_PCI_CLK_PMU 145 +#define R9A08G046_SPDIF_PCLK 146 +#define R9A08G046_I3C_TCLK 147 +#define R9A08G046_I3C_PCLK 148 +#define R9A08G046_VBAT_BCLK 149 +#define R9A08G046_BSC_X_BCK_BSC 150 + +/* R9A08G046 Resets */ +#define R9A08G046_CA55_RST0_0 0 +#define R9A08G046_CA55_RST0_1 1 +#define R9A08G046_CA55_RST0_2 2 +#define R9A08G046_CA55_RST0_3 3 +#define R9A08G046_CA55_RST4_0 4 +#define R9A08G046_CA55_RST4_1 5 +#define R9A08G046_CA55_RST4_2 6 +#define R9A08G046_CA55_RST4_3 7 +#define R9A08G046_CA55_RST8 8 +#define R9A08G046_CA55_RST9 9 +#define R9A08G046_CA55_RST10 10 +#define R9A08G046_CA55_RST11 11 +#define R9A08G046_CA55_RST12 12 +#define R9A08G046_CA55_RST13 13 +#define R9A08G046_CA55_RST14 14 +#define R9A08G046_CA55_RST15 15 +#define R9A08G046_CA55_RST16 16 +#define R9A08G046_SRAM_ACPU_ARESETN0 17 +#define R9A08G046_SRAM_ACPU_ARESETN1 18 +#define R9A08G046_SRAM_ACPU_ARESETN2 19 +#define R9A08G046_GIC600_GICRESET_N 20 +#define R9A08G046_GIC600_DBG_GICRESET_N 21 +#define R9A08G046_IA55_RESETN 22 +#define R9A08G046_MHU_RESETN 23 +#define R9A08G046_SYC_RESETN 24 +#define R9A08G046_DMAC_ARESETN 25 +#define R9A08G046_DMAC_RST_ASYNC 26 +#define R9A08G046_GTM0_PRESETZ 27 +#define R9A08G046_GTM1_PRESETZ 28 +#define R9A08G046_GTM2_PRESETZ 29 +#define R9A08G046_MTU_X_PRESET_MTU3 30 +#define R9A08G046_POE3_RST_M_REG 31 +#define R9A08G046_GPT_RST_C 32 +#define R9A08G046_POEG_A_RST 33 +#define R9A08G046_POEG_B_RST 34 +#define R9A08G046_POEG_C_RST 35 +#define R9A08G046_POEG_D_RST 36 +#define R9A08G046_WDT0_PRESETN 37 +#define R9A08G046_WDT1_PRESETN 38 +#define R9A08G046_WDT2_PRESETN 39 +#define R9A08G046_XSPI_HRESETN 40 +#define R9A08G046_XSPI_ARESETN 41 +#define R9A08G046_SDHI0_IXRST 42 +#define R9A08G046_SDHI1_IXRST 43 +#define R9A08G046_SDHI2_IXRST 44 +#define R9A08G046_SDHI0_IXRSTAXIM 45 +#define R9A08G046_SDHI0_IXRSTAXIS 46 +#define R9A08G046_SDHI1_IXRSTAXIM 47 +#define R9A08G046_SDHI1_IXRSTAXIS 48 +#define R9A08G046_SDHI2_IXRSTAXIM 49 +#define R9A08G046_SDHI2_IXRSTAXIS 50 +#define R9A08G046_GE3D_RESETN 51 +#define R9A08G046_GE3D_AXI_RESETN 52 +#define R9A08G046_GE3D_ACE_RESETN 53 +#define R9A08G046_ISU_ARESETN 54 +#define R9A08G046_ISU_PRESETN 55 +#define R9A08G046_H264_X_RESET_VCP 56 +#define R9A08G046_H264_CP_PRESET_P 57 +#define R9A08G046_CRU_CMN_RSTB 58 +#define R9A08G046_CRU_PRESETN 59 +#define R9A08G046_CRU_ARESETN 60 +#define R9A08G046_MIPI_DSI_CMN_RSTB 61 +#define R9A08G046_MIPI_DSI_ARESET_N 62 +#define R9A08G046_MIPI_DSI_PRESET_N 63 +#define R9A08G046_LCDC_RESET_N 64 +#define R9A08G046_SSI0_RST_M2_REG 65 +#define R9A08G046_SSI1_RST_M2_REG 66 +#define R9A08G046_SSI2_RST_M2_REG 67 +#define R9A08G046_SSI3_RST_M2_REG 68 +#define R9A08G046_USB_U2H0_HRESETN 69 +#define R9A08G046_USB_U2H1_HRESETN 70 +#define R9A08G046_USB_U2P0_EXL_SYSRST 71 +#define R9A08G046_USB_PRESETN 72 +#define R9A08G046_USB_U2P1_EXL_SYSRST 73 +#define R9A08G046_ETH0_ARESET_N 74 +#define R9A08G046_ETH1_ARESET_N 75 +#define R9A08G046_I2C0_MRST 76 +#define R9A08G046_I2C1_MRST 77 +#define R9A08G046_I2C2_MRST 78 +#define R9A08G046_I2C3_MRST 79 +#define R9A08G046_SCIF0_RST_SYSTEM_N 80 +#define R9A08G046_SCIF1_RST_SYSTEM_N 81 +#define R9A08G046_SCIF2_RST_SYSTEM_N 82 +#define R9A08G046_SCIF3_RST_SYSTEM_N 83 +#define R9A08G046_SCIF4_RST_SYSTEM_N 84 +#define R9A08G046_SCIF5_RST_SYSTEM_N 85 +#define R9A08G046_RSPI0_PRESETN 86 +#define R9A08G046_RSPI1_PRESETN 87 +#define R9A08G046_RSPI2_PRESETN 88 +#define R9A08G046_RSPI0_TRESETN 89 +#define R9A08G046_RSPI1_TRESETN 90 +#define R9A08G046_RSPI2_TRESETN 91 +#define R9A08G046_CANFD_RSTP_N 92 +#define R9A08G046_CANFD_RSTC_N 93 +#define R9A08G046_GPIO_RSTN 94 +#define R9A08G046_GPIO_PORT_RESETN 95 +#define R9A08G046_GPIO_SPARE_RESETN 96 +#define R9A08G046_ADC0_PRESETN 97 +#define R9A08G046_ADC0_ADRST_N 98 +#define R9A08G046_ADC1_PRESETN 99 +#define R9A08G046_ADC1_ADRST_N 100 +#define R9A08G046_TSU_PRESETN 101 +#define R9A08G046_PDM_PRESETN 102 +#define R9A08G046_PCI_ARESETN 103 +#define R9A08G046_SPDIF_RST 104 +#define R9A08G046_I3C_TRESETN 105 +#define R9A08G046_I3C_PRESETN 106 +#define R9A08G046_VBAT_BRESETN 107 +#define R9A08G046_RSCI0_PRESETN 108 +#define R9A08G046_RSCI1_PRESETN 109 +#define R9A08G046_RSCI2_PRESETN 110 +#define R9A08G046_RSCI3_PRESETN 111 +#define R9A08G046_RSCI0_TRESETN 112 +#define R9A08G046_RSCI1_TRESETN 113 +#define R9A08G046_RSCI2_TRESETN 114 +#define R9A08G046_RSCI3_TRESETN 115 +#define R9A08G046_LVDS_RESET_N 116 + +#endif /* __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__ */ --=20 2.43.0 From nobody Sat Feb 7 05:49:10 2026 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by 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ESMTPSA id a640c23a62f3a-b8dbf1baa42sm114400366b.46.2026.01.28.03.30.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 03:30:40 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Magnus Damm Cc: Biju Das , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 06/10] clk: renesas: Add support for RZ/G3L SoC Date: Wed, 28 Jan 2026 11:30:25 +0000 Message-ID: <20260128113032.337231-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260128113032.337231-1-biju.das.jz@bp.renesas.com> References: <20260128113032.337231-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The clock structure for RZ/G3L is almost identical to RZ/G3S SoC with more IP blocks such as LCDC, CRU, LVDS and GPU. Add minimal clock and reset entries required to boot the system on Renesas RZ/G3L SMARC EVK and binds it with the RZ/G2L CPG core driver. Signed-off-by: Biju Das --- v1->v2: * Added CLK_ETH{0,1}_TXC_TX_CLK_IN and CLK_ETH{0,1}_RXC_RX_CLK_IN clocks. * Dropped R9A08G046_IA55_PCLK from critical clock list. --- drivers/clk/renesas/Kconfig | 7 +- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a08g046-cpg.c | 144 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.c | 6 ++ drivers/clk/renesas/rzg2l-cpg.h | 1 + 5 files changed, 158 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/renesas/r9a08g046-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 6a5a04664990..0203ecbb3882 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -39,6 +39,7 @@ config CLK_RENESAS select CLK_R9A07G044 if ARCH_R9A07G044 select CLK_R9A07G054 if ARCH_R9A07G054 select CLK_R9A08G045 if ARCH_R9A08G045 + select CLK_R9A08G046 if ARCH_R9A08G046 select CLK_R9A09G011 if ARCH_R9A09G011 select CLK_R9A09G047 if ARCH_R9A09G047 select CLK_R9A09G056 if ARCH_R9A09G056 @@ -194,6 +195,10 @@ config CLK_R9A08G045 bool "RZ/G3S clock support" if COMPILE_TEST select CLK_RZG2L =20 +config CLK_R9A08G046 + bool "RZ/G3L clock support" if COMPILE_TEST + select CLK_RZG2L + config CLK_R9A09G011 bool "RZ/V2M clock support" if COMPILE_TEST select CLK_RZG2L @@ -250,7 +255,7 @@ config CLK_RCAR_USB2_CLOCK_SEL This is a driver for R-Car USB2 clock selector =20 config CLK_RZG2L - bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST + bool "RZ/{G2{L,UL},G3{S,L},V2L} family clock support" if COMPILE_TEST select RESET_CONTROLLER =20 config CLK_RZV2H diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index d28eb276a153..bd2bed91ab29 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_R9A07G043) +=3D r9a07g043-cpg.o obj-$(CONFIG_CLK_R9A07G044) +=3D r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A07G054) +=3D r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A08G045) +=3D r9a08g045-cpg.o +obj-$(CONFIG_CLK_R9A08G046) +=3D r9a08g046-cpg.o obj-$(CONFIG_CLK_R9A09G011) +=3D r9a09g011-cpg.o obj-$(CONFIG_CLK_R9A09G047) +=3D r9a09g047-cpg.o obj-$(CONFIG_CLK_R9A09G056) +=3D r9a09g056-cpg.o diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c new file mode 100644 index 000000000000..d77934872cf4 --- /dev/null +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3L CPG driver + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "rzg2l-cpg.h" + +/* RZ/G3L Specific registers. */ +#define G3L_CPG_PL2_DDIV (0x204) +#define G3L_CPG_PL3_DDIV (0x208) +#define G3L_CLKDIVSTATUS (0x280) + +/* RZ/G3L Specific division configuration. */ +#define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2) +#define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2) +#define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2) + +/* RZ/G3L Clock status configuration. */ +#define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1) +#define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1) +#define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1) + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK =3D R9A08G046_CLK_P4_DIV2, + + /* External Input Clocks */ + CLK_EXTAL, + CLK_ETH0_TXC_TX_CLK_IN, + CLK_ETH0_RXC_RX_CLK_IN, + CLK_ETH1_TXC_TX_CLK_IN, + CLK_ETH1_RXC_RX_CLK_IN, + + /* Internal Core Clocks */ + CLK_PLL2, + CLK_PLL2_DIV2, + CLK_PLL3, + CLK_PLL3_DIV2, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +/* Divider tables */ +static const struct clk_div_table dtable_4_128[] =3D { + { 0, 4 }, + { 1, 2 }, + { 2, 16 }, + { 3, 128 }, + { 0, 0 }, +}; + +static const struct clk_div_table dtable_8_256[] =3D { + { 0, 8 }, + { 1, 16 }, + { 2, 32 }, + { 3, 256 }, + { 0, 0 }, +}; + +static const struct cpg_core_clk r9a08g046_core_clks[] __initconst =3D { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("eth0_txc_tx_clk", CLK_ETH0_TXC_TX_CLK_IN), + DEF_INPUT("eth0_rxc_rx_clk", CLK_ETH0_RXC_RX_CLK_IN), + DEF_INPUT("eth1_txc_tx_clk", CLK_ETH1_TXC_TX_CLK_IN), + DEF_INPUT("eth1_rxc_rx_clk", CLK_ETH1_RXC_RX_CLK_IN), + + /* Internal Core Clocks */ + DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), + DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2), + + /* Core output clk */ + DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL= 2B_STS, + dtable_8_256, 0, 0, 0, NULL), + DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL= 3A_STS, + dtable_4_128, 0, 0, 0, NULL), + DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL= 2A_STS, + dtable_4_128, 0, 0, 0, NULL), +}; + +static const struct rzg2l_mod_clk r9a08g046_mod_clks[] =3D { + DEF_MOD("gic_gicclk", R9A08G046_GIC600_GICCLK, R9A08G046_CLK_P1, 0x514, = 0, + MSTOP(BUS_PERI_COM, BIT(12))), + DEF_MOD("ia55_pclk", R9A08G046_IA55_PCLK, R9A08G046_CLK_P0, 0x518, 0, + MSTOP(BUS_PERI_CPU, BIT(13))), + DEF_MOD("ia55_clk", R9A08G046_IA55_CLK, R9A08G046_CLK_P1, 0x518, 1, + MSTOP(BUS_PERI_CPU, BIT(13))), + DEF_MOD("dmac_aclk", R9A08G046_DMAC_ACLK, R9A08G046_CLK_P3, 0x52c, 0, + MSTOP(BUS_REG1, BIT(2))), + DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1, + MSTOP(BUS_REG1, BIT(3))), + DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584= , 0, + MSTOP(BUS_MCPU2, BIT(1))), +}; + +static const struct rzg2l_reset r9a08g046_resets[] =3D { + DEF_RST(R9A08G046_GIC600_GICRESET_N, 0x814, 0), + DEF_RST(R9A08G046_GIC600_DBG_GICRESET_N, 0x814, 1), + DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0), + DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0), + DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1), + DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0), +}; + +static const unsigned int r9a08g046_crit_mod_clks[] __initconst =3D { + MOD_CLK_BASE + R9A08G046_GIC600_GICCLK, + MOD_CLK_BASE + R9A08G046_IA55_CLK, + MOD_CLK_BASE + R9A08G046_DMAC_ACLK, +}; + +const struct rzg2l_cpg_info r9a08g046_cpg_info =3D { + /* Core Clocks */ + .core_clks =3D r9a08g046_core_clks, + .num_core_clks =3D ARRAY_SIZE(r9a08g046_core_clks), + .last_dt_core_clk =3D LAST_DT_CORE_CLK, + .num_total_core_clks =3D MOD_CLK_BASE, + + /* Critical Module Clocks */ + .crit_mod_clks =3D r9a08g046_crit_mod_clks, + .num_crit_mod_clks =3D ARRAY_SIZE(r9a08g046_crit_mod_clks), + + /* Module Clocks */ + .mod_clks =3D r9a08g046_mod_clks, + .num_mod_clks =3D ARRAY_SIZE(r9a08g046_mod_clks), + .num_hw_mod_clks =3D R9A08G046_BSC_X_BCK_BSC + 1, + + /* Resets */ + .resets =3D r9a08g046_resets, + .num_resets =3D R9A08G046_LVDS_RESET_N + 1, /* Last reset ID + 1 */ + + .has_clk_mon_regs =3D true, +}; diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index c0584bab58a3..f4deb5d3b837 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -2093,6 +2093,12 @@ static const struct of_device_id rzg2l_cpg_match[] = =3D { .data =3D &r9a08g045_cpg_info, }, #endif +#ifdef CONFIG_CLK_R9A08G046 + { + .compatible =3D "renesas,r9a08g046-cpg", + .data =3D &r9a08g046_cpg_info, + }, +#endif #ifdef CONFIG_CLK_R9A09G011 { .compatible =3D "renesas,r9a09g011-cpg", diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 55e815be16c8..1db413bb433d 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -309,6 +309,7 @@ extern const struct rzg2l_cpg_info r9a07g043_cpg_info; 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Wed, 28 Jan 2026 03:30:41 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:e29d:6e0e:72c1:d15d]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf1baa42sm114400366b.46.2026.01.28.03.30.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 03:30:41 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC Date: Wed, 28 Jan 2026 11:30:26 +0000 Message-ID: <20260128113032.337231-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260128113032.337231-1-biju.das.jz@bp.renesas.com> References: <20260128113032.337231-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add the initial DTSI for the RZ/G3L SoC. The files in this commit have the following meaning: - r9a08g046.dtsi: RZ/G3L family SoC common parts - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts Added place holders to reuse the code for Renesas SMARC II carrier board. Signed-off-by: Biju Das --- v1->v2: * Added external clocks eth{0,1}_txc_tx_clk and eth{0,1}_rxc_rx_clk as it needed for cpg as it is a clock source for mux. * Updated cpg node --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 251 ++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi | 13 + 2 files changed, 264 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi new file mode 100644 index 000000000000..0922ad642c67 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3L SoC + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible =3D "renesas,r9a08g046"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + audio_clk1: audio-clk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency =3D <0>; + }; + + audio_clk2: audio-clk2 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency =3D <0>; + }; + + can_clk: can-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency =3D <0>; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a55"; + reg =3D <0>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + cpu1: cpu@100 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + cpu2: cpu@200 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + cpu3: cpu@300 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible =3D "cache"; + cache-unified; + cache-size =3D <0x80000>; + cache-level =3D <3>; + }; + }; + + eth0_txc_tx_clk: eth0-txc-tx-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + eth0_rxc_rx_clk: eth0-rxc-rx-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + eth1_txc_tx_clk: eth1-txc-tx-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + eth1_rxc_rx_clk: eth1-rxc-rx-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + extal_clk: extal-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board. */ + clock-frequency =3D <0>; + }; + + psci { + compatible =3D "arm,psci-1.0", "arm,psci-0.2"; + method =3D "smc"; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + scif0: serial@100ac000 { + compatible =3D "renesas,scif-r9a08g046", "renesas,scif-r9a07g044"; + reg =3D <0 0x100ac000 0 0x400>; + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks =3D <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>; + clock-names =3D "fck"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>; + status =3D "disabled"; + }; + + i2c0: i2c@100ae000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x100AE000 0 0x400>; + /* placeholder */ + }; + + canfd: can@100c0000 { + reg =3D <0 0x100c0000 0 0x20000>; + /* placeholder */ + }; + + cpg: clock-controller@11010000 { + compatible =3D "renesas,r9a08g046-cpg"; + reg =3D <0 0x11010000 0 0x10000>; + clocks =3D <&extal_clk>, + <ð0_txc_tx_clk>, <ð0_rxc_rx_clk>, + <ð1_txc_tx_clk>, <ð1_rxc_rx_clk>; + clock-names =3D "extal", + "eth0_txc_tx_clk", "eth0_rxc_rx_clk", + "eth1_txc_tx_clk", "eth1_rxc_rx_clk"; + #clock-cells =3D <2>; + #reset-cells =3D <1>; + #power-domain-cells =3D <0>; + }; + + sysc: system-controller@11020000 { + compatible =3D "renesas,r9a08g046-sysc"; + reg =3D <0 0x11020000 0 0x10000>; + interrupts =3D , + , + , + ; + interrupt-names =3D "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + }; + + pinctrl: pinctrl@11030000 { + reg =3D <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + }; + + dmac: dma-controller@11820000 { + compatible =3D "renesas,r9a08g046-dmac", "renesas,rz-dmac"; + reg =3D <0 0x11820000 0 0x10000>, + <0 0x11830000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks =3D <&cpg CPG_MOD R9A08G046_DMAC_ACLK>, + <&cpg CPG_MOD R9A08G046_DMAC_PCLK>; + clock-names =3D "main", "register"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A08G046_DMAC_ARESETN>, + <&cpg R9A08G046_DMAC_RST_ASYNC>; + reset-names =3D "arst", "rst_async"; + #dma-cells =3D <1>; + dma-channels =3D <16>; + }; + + sdhi1: mmc@11c10000 { + reg =3D <0x0 0x11c10000 0 0x10000>; + /* placeholder */ + }; + + gic: interrupt-controller@12400000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x12400000 0 0x20000>, + <0x0 0x12440000 0 0x80000>; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D ; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + interrupt-names =3D "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 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charset="utf-8" From: Biju Das Add initial support for the RZ/G3L SMARC SoM with 2GB memory and extal clk. Signed-off-by: Biju Das --- v1->v2: * Dropped gpio.h header file. --- .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3l-smarc-som.dtsi new file mode 100644 index 000000000000..7c21afaee9bc --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for R9A08G046L48 SMARC SoM board. + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +/ { + compatible =3D "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r= 9a08g046"; + + memory@48000000 { + device_type =3D "memory"; + /* First 128MB is reserved for secure area. */ + reg =3D <0x0 0x48000000 0x0 0x78000000>; + }; +}; + +&extal_clk { + clock-frequency =3D <24000000>; +}; --=20 2.43.0 From nobody Sat Feb 7 05:49:10 2026 Received: from mail-ej1-f67.google.com (mail-ej1-f67.google.com [209.85.218.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A55134EEEC for ; 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Wed, 28 Jan 2026 03:30:42 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:e29d:6e0e:72c1:d15d]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf1baa42sm114400366b.46.2026.01.28.03.30.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 03:30:42 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 09/10] arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS Date: Wed, 28 Jan 2026 11:30:28 +0000 Message-ID: <20260128113032.337231-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260128113032.337231-1-biju.das.jz@bp.renesas.com> References: <20260128113032.337231-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das SMARC2 board dtsi is common for multiple SoCs. So move usb3 nodes to board DTS as some SOCs (eg: RZ/G3{S,L}) does not support USB3. Signed-off-by: Biju Das --- v1->v2: * No change --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 6 ++++++ arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 8 -------- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a09g047e57-smarc.dts index 696903dc7a63..cc75f6fdf7f5 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -248,7 +248,13 @@ &sdhi1 { vqmmc-supply =3D <&vqmmc_sd1_pvdd>; }; =20 +&usb3_phy { + status =3D "okay"; +}; + &xhci { pinctrl-0 =3D <&usb3_pins>; pinctrl-names =3D "default"; + + status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/b= oot/dts/renesas/renesas-smarc2.dtsi index b607b5d6c259..69c0101ff7f5 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -107,11 +107,3 @@ &sdhi1 { =20 status =3D "okay"; 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Wed, 28 Jan 2026 03:30:43 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 10/10] arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK board Date: Wed, 28 Jan 2026 11:30:29 +0000 Message-ID: <20260128113032.337231-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260128113032.337231-1-biju.das.jz@bp.renesas.com> References: <20260128113032.337231-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add the initial device tree for the Renesas RZ/G3L SMARC EVK board. Added placeholders to avoid compilation error with the common code in renesas-smarc2.dtsi. Signed-off-by: Biju Das --- v1->v2: * Dropped scif node as it is already included in common platform file. --- arch/arm64/boot/dts/renesas/Makefile | 2 + .../boot/dts/renesas/r9a08g046l48-smarc.dts | 37 +++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index 1fab1b50f20e..0153e772c231 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -179,6 +179,8 @@ dtb-$(CONFIG_ARCH_R9A08G045) +=3D r9a08g045s33-smarc-pm= od1-type-3a.dtbo r9a08g045s33-smarc-pmod1-type-3a-dtbs :=3D r9a08g045s33-smarc.dtb r9a08g04= 5s33-smarc-pmod1-type-3a.dtbo dtb-$(CONFIG_ARCH_R9A08G045) +=3D r9a08g045s33-smarc-pmod1-type-3a.dtb =20 +dtb-$(CONFIG_ARCH_R9A08G046) +=3D r9a08g046l48-smarc.dtb + dtb-$(CONFIG_ARCH_R9A09G011) +=3D r9a09g011-v2mevk2.dtb =20 dtb-$(CONFIG_ARCH_R9A09G047) +=3D r9a09g047e57-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a08g046l48-smarc.dts new file mode 100644 index 000000000000..86db86335d5e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3L SMARC EVK board + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +/dts-v1/; + +/* Add place holder to avoid compilation error with renesas-smarc2.dtsi */ +#define KEY_1_GPIO 1 +#define KEY_2_GPIO 2 +#define KEY_3_GPIO 3 + +#include +#include +#include "r9a08g046l48.dtsi" +#include "rzg3l-smarc-som.dtsi" +#include "renesas-smarc2.dtsi" + +/ { + model =3D "Renesas SMARC EVK version 2 based on r9a08g046l48"; + compatible =3D "renesas,smarc2-evk", "renesas,rzg3l-smarcm", + "renesas,r9a08g046l48", "renesas,r9a08g046"; + + aliases { + serial3 =3D &scif0; + }; +}; + +&keys { + status =3D "disabled"; + + /delete-node/ key-1; + /delete-node/ key-2; + /delete-node/ key-3; +}; --=20 2.43.0