From nobody Sat Feb 7 05:49:39 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B29DC345749 for ; Wed, 28 Jan 2026 11:24:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769599489; cv=none; b=DDOM9ZLkKJsOLIDn51Mdrdw3YqDMQIFrosUVaRqYGQsHaDZUeIVWqcrLDUMtgObEfvf6TOyo4iEZ5V3NM2SO3BPTdzKPjyZbF1zJdHxrHRfb83VCSUyNiajdu4lKzFlwuNMXdnD5/C8d2k+Ay/a1/meSbNVU5OCAiniaad4oRxg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769599489; c=relaxed/simple; bh=DbLPeovYiwjXpn5dbWMK4U8Irz//NWlC2tACaOAzwNI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hTF13FVm1hJraQXveKEqAilTC8tO/GkonvA+EthUjjXTtCf3p4XVDikj25LXPGu4YMN6/Ak3TNoUt3sVU5WxMpAkZLZr3AnGoXCLXt2fZ5KivXmdfvidGE9t/i2k7ISLWaJZdVNa1RqWiU4qVVOKot7fNzzWIUFR2uwi4jcQeYM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=pXlzDfPq; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=g/bv2MSX; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="pXlzDfPq"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="g/bv2MSX" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60S923IH1406310 for ; Wed, 28 Jan 2026 11:24:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=+Sy9zUDZs56 f6JnqKzFkwx6XwPXTc9MqxOFBhYwgs2A=; b=pXlzDfPqPTKlaz46J7jRQdlXg7Z WxENcRFC433nlc8E4DoqJlywKtUw9E++MFHibHEt5xi/qm5ltMsVnn456T9hx75X AwUcy6HD1u8+7FJZToCO747Ihj1xPkCjK+g6IvIOb5GWwzFCD5wO2iwnwyahKFH6 mPPgVxVK88tjR/u6I/BEzr94maGzro+ySIKIq1PW/Ee5qVyoVosM5ZhPwwMMf6Di NTNd2lKXU20wIU8SfSAUgodddX/OtW4SaA/a0fNW4q1/MwiiTLOUg/uej9MiYBAk gWMAZ0pZ4gF9qswb0qmyGZB2imKx2G0n7FrCjKsB8pCDLptmimKgLgEcf7A== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4by4dytjry-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 28 Jan 2026 11:24:43 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2a0a8c465c1so5622025ad.1 for ; Wed, 28 Jan 2026 03:24:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1769599483; x=1770204283; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+Sy9zUDZs56f6JnqKzFkwx6XwPXTc9MqxOFBhYwgs2A=; b=g/bv2MSXVpSH0nEaj6PmIMvc5nKwKoDxWUydqYZOVP76Zcv0N3y3VpbzGGrVqn7GQZ Iq2sxMJ52fXxkzthO1jTu7aGf67y013QUhuDdWzrpH+PvFfYOqjGimfbtkbQ8VKPcpII v2VHH3SPlefe43DbQEn9WIglPSIxYBzoSrUfbzR8KJJPRNZOL602rnhhxbHyqrjqnhUv vmEH4uhXqNrljEIiiuEseJPZocoAaBF57e46xNEQkZm99w4NVPXeowyTjHJyhegDAgQJ tUK2MPLZVpG6307urE0llSwZtiMvydSAg2gJnr2G8Z9PDyUVaE8rrHwRF2odBd1fFc68 S+9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769599483; x=1770204283; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=+Sy9zUDZs56f6JnqKzFkwx6XwPXTc9MqxOFBhYwgs2A=; b=OLWaAGqKXBllI1baIBex0dfhVz/J66mbZ5hwBVGHK6Od0KiPS8d7xcd7qt0B8riHn7 Bea9NrhW2ekshIJeSbiuso7kyJMim/TYSKH3llKlPK07unXHP3QfDXrOCpiCEP2muezb KYWJ0CONPyXZm4595OpQVE6lEVVJgkXKnk+Fctm1O/Y17eRBc1cdlNxjH/tdZYF6Htyx fpjKznNo+llzLp5Mx38NzXljaSvfLaMdiK+qpQxbaG2iUJqRq2szGCW3gQamyBJGvEHc 4ntPfyKCu1iduGq/IJ9OwBvrGOejB7D/YH68hss5GPu0tnOWBqmFM2ZOEGZi84Xxkb4O E2AQ== X-Forwarded-Encrypted: i=1; AJvYcCXeG+nz1ckFKmexnoNi5vJoYJFEuAwaArFQE0Bux/M0uWWPyGUm1/HUB8RFpdnS84Bn5dS8bfvrSk/+bkc=@vger.kernel.org X-Gm-Message-State: AOJu0YzUvYAkV5I+yOdapXIzzWE0/gnAWStXVEhiY7lBzAX7y4Y+3+Se 77Cg9rfw7c9Y66uRY1ThjBYnoWRXU+8Db3zI9bT60+gFrqRjb4Vaw4G/LwosuG6fFYmGe1tsYBX Hibz1hjkmEicOY8quTNjcbcW5qBdF5lQAXyEG4KaSt8PYZJP4UBRB6zFarL9m6g5Wmxw= X-Gm-Gg: AZuq6aIsu7+N7n0SowV/yQXt2Rvox6dnFWTfflWh38zGBNbTI88IAWRHxlsGORFlBR3 GwFsAQc8L/TGqL8KaEHunxgxQxkuIgGNl2j8rpy6vCwgGIrdbHgoAj7gexGqKi/Oe/z+ovdM1ks Tloavu/lrwiOfHO459y1rGuIhyhKK8+xXmZcPLTencLQLR3RA1uQx09TsN5ngRVHBU9liCJ1ZbL l8JfeFAg0/o3IzVHca1iZfx0OiAezy8K3GjiS/v4xliB9l7BxuCg19tdTwEmz5j3MnukVzaVFt/ +2h+hvgWn/l1LuavhH7XZUPvn3oqJwQCDuAaYXIcZDSZ9PunyTSv4YHizRwwrxyb8h8s9rnRHzU zBpGI7znMyZM/Vkk0kDdBXheFPz+vmKLKhtdiVyRMOHsw X-Received: by 2002:a17:902:d2cc:b0:2a7:bbe0:f01f with SMTP id d9443c01a7336-2a87120f624mr46348235ad.2.1769599482740; Wed, 28 Jan 2026 03:24:42 -0800 (PST) X-Received: by 2002:a17:902:d2cc:b0:2a7:bbe0:f01f with SMTP id d9443c01a7336-2a87120f624mr46347955ad.2.1769599482206; Wed, 28 Jan 2026 03:24:42 -0800 (PST) Received: from hu-jprakash-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a88b4c40a8sm21984605ad.51.2026.01.28.03.24.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 03:24:41 -0800 (PST) From: Jishnu Prakash To: jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org, daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org, subbaraman.narayanamurthy@oss.qualcomm.com, david.collins@oss.qualcomm.com, anjelique.melendez@oss.qualcomm.com, kamal.wadhwa@oss.qualcomm.com Cc: rui.zhang@intel.com, lukasz.luba@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, jishnu.prakash@oss.qualcomm.com, quic_kotarake@quicinc.com, neil.armstrong@linaro.org, stephan.gerhold@linaro.org, Krzysztof Kozlowski , Jonathan Cameron Subject: [PATCH V9 1/4] dt-bindings: iio: adc: Split out QCOM VADC channel properties Date: Wed, 28 Jan 2026 16:54:17 +0530 Message-Id: <20260128112420.695518-2-jishnu.prakash@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260128112420.695518-1-jishnu.prakash@oss.qualcomm.com> References: <20260128112420.695518-1-jishnu.prakash@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=XqT3+FF9 c=1 sm=1 tr=0 ts=6979f1fb cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=KKAkSRfTAAAA:8 a=i0EeH86SAAAA:8 a=EUspDBNiAAAA:8 a=4vDKtjJwf6yegxfEYBcA:9 a=1OuFwYUASf3TG4hYMiVC:22 a=sptkURWiP4Gy88Gu7hUp:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: -A4snKg4uIA_g5RteWOu8940SYTJXVLt X-Proofpoint-ORIG-GUID: -A4snKg4uIA_g5RteWOu8940SYTJXVLt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI4MDA5MyBTYWx0ZWRfX/68cRrrXHS0f t2Jf43lfiw44PlyKA7yg/OHaFjdn7CoZEdjaDGYmzD4eyl4S26jGXSwAuF2TCXOvYAiz6YRJLpA Tk8jD7iArx/klNn+6o+cM8HbgzkpKT/8O84dfulyabjU/Yq6oLxlRm50XEQIlBhZXAL6Pgsack4 Fp2lM82LtQNI7DLCJMCUewMjkQa5vbzLXO03/cE+0irm3M8h2IU1lxz1nw7bcwZVHOUatOLXalS j68I17WgfQ8U88plXHF9wLNtUylfmOcnJcHUHnD3v1u2bgIm6ab0O48uiLwmfog/9CFpZHJxOcz lcG2MSChZltOn8qxLrwOj1vCqH0zvKTXo/a62GsZ7sss0dqSmeJNqPJcU5H4eipuPEes443Stde kmfMy5lbZXwYNzPZakTTc25/fF96Fpp2s3pQkoOhbEbpvN9g0Wse7mqeEIU1xEKw1VBm/9TXruI KheGe/uuupYO7mqnbFQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-28_02,2026-01-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601280093 Content-Type: text/plain; charset="utf-8" Split out the common channel properties for QCOM VADC devices into a separate file so that it can be included as a reference for devices using them. This will be needed for the upcoming ADC5 Gen3 binding support patch, as ADC5 Gen3 also uses all of these common properties. Reviewed-by: Krzysztof Kozlowski Acked-by: Jonathan Cameron Signed-off-by: Jishnu Prakash --- Changes since v7: - Removed binding file paths mentioned under `reg` property description in Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc-common.yaml, and updated the description slightly, to simplify it and avoid any dependenci= es on patch 1 from the earlier series. - Removed an extra blank line present in Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml in previous versions. Changes since v6: - Collected Acked-by tag from Jonathan. Changes since v5: - Collected Reviewed-by tag from Krzysztof. .../iio/adc/qcom,spmi-vadc-common.yaml | 84 +++++++++++++++++++ .../bindings/iio/adc/qcom,spmi-vadc.yaml | 76 +---------------- 2 files changed, 86 insertions(+), 74 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vad= c-common.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc-commo= n.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc-common.ya= ml new file mode 100644 index 000000000000..3ae252c17b91 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc-common.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SPMI PMIC ADC channels + +maintainers: + - Jishnu Prakash + +description: + This defines the common properties used to define Qualcomm VADC channels. + +properties: + reg: + description: + ADC channel number (PMIC-specific for versions after PMIC5 ADC). + maxItems: 1 + + label: + description: + ADC input of the platform as seen in the schematics. + For thermistor inputs connected to generic AMUX or GPIO inputs + these can vary across platform for the same pins. Hence select + the platform schematics name for this channel. + + qcom,decimation: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + This parameter is used to decrease ADC sampling rate. + Quicker measurements can be made by reducing decimation ratio. + + qcom,pre-scaling: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Used for scaling the channel input signal before the signal is + fed to VADC. The configuration for this node is to know the + pre-determined ratio and use it for post scaling. It is a pair of + integers, denoting the numerator and denominator of the fraction by = which + input signal is multiplied. For example, <1 3> indicates the signal = is scaled + down to 1/3 of its value before ADC measurement. + If property is not found default value depending on chip will be use= d. + oneOf: + - items: + - const: 1 + - enum: [ 1, 3, 4, 6, 20, 8, 10, 16 ] + - items: + - const: 10 + - const: 81 + + qcom,ratiometric: + type: boolean + description: | + Channel calibration type. + - For compatible property "qcom,spmi-vadc", if this property is + specified VADC will use the VDD reference (1.8V) and GND for + channel calibration. If property is not found, channel will be + calibrated with 0.625V and 1.25V reference channels, also + known as absolute calibration. + - For other compatible properties, if this property is specified + VADC will use the VDD reference (1.875V) and GND for channel + calibration. If property is not found, channel will be calibrated + with 0V and 1.25V reference channels, also known as absolute calib= ration. + + qcom,hw-settle-time: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Time between AMUX getting configured and the ADC starting + conversion. The 'hw_settle_time' is an index used from valid values + and programmed in hardware to achieve the hardware settling delay. + + qcom,avg-samples: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Number of samples to be used for measurement. + Averaging provides the option to obtain a single measurement + from the ADC that is an average of multiple samples. The value + selected is 2^(value). + +required: + - reg + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml = b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml index b9dc04b0d307..16c80709a3ee 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -56,7 +56,7 @@ required: patternProperties: "^channel@[0-9a-f]+$": type: object - additionalProperties: false + unevaluatedProperties: false description: | Represents the external channels which are connected to the ADC. For compatible property "qcom,spmi-vadc" following channels, also kn= own as @@ -64,79 +64,7 @@ patternProperties: configuration nodes should be defined: VADC_REF_625MV and/or VADC_SPARE1(based on PMIC version) VADC_REF_12= 50MV, VADC_GND_REF and VADC_VDD_VADC. - - properties: - reg: - maxItems: 1 - description: | - ADC channel number. - See include/dt-bindings/iio/qcom,spmi-vadc.h - For PMIC7 ADC, the channel numbers are specified separately per = PMIC - in the PMIC-specific files in include/dt-bindings/iio/. - - label: - description: | - ADC input of the platform as seen in the schematics. - For thermistor inputs connected to generic AMUX or GPIO inputs - these can vary across platform for the same pins. Hence select - the platform schematics name for this channel. - - qcom,decimation: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - This parameter is used to decrease ADC sampling rate. - Quicker measurements can be made by reducing decimation ratio. - - qcom,pre-scaling: - description: | - Used for scaling the channel input signal before the signal is - fed to VADC. The configuration for this node is to know the - pre-determined ratio and use it for post scaling. It is a pair= of - integers, denoting the numerator and denominator of the fracti= on by which - input signal is multiplied. For example, <1 3> indicates the s= ignal is scaled - down to 1/3 of its value before ADC measurement. - If property is not found default value depending on chip will = be used. - $ref: /schemas/types.yaml#/definitions/uint32-array - oneOf: - - items: - - const: 1 - - enum: [ 1, 3, 4, 6, 20, 8, 10, 16 ] - - items: - - const: 10 - - const: 81 - - qcom,ratiometric: - description: | - Channel calibration type. - - For compatible property "qcom,spmi-vadc", if this property is - specified VADC will use the VDD reference (1.8V) and GND for - channel calibration. If property is not found, channel will = be - calibrated with 0.625V and 1.25V reference channels, also - known as absolute calibration. - - For compatible property "qcom,spmi-adc5", "qcom,spmi-adc7" a= nd - "qcom,spmi-adc-rev2", if this property is specified VADC wil= l use - the VDD reference (1.875V) and GND for channel calibration. = If - property is not found, channel will be calibrated with 0V an= d 1.25V - reference channels, also known as absolute calibration. - type: boolean - - qcom,hw-settle-time: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - Time between AMUX getting configured and the ADC starting - conversion. The 'hw_settle_time' is an index used from valid v= alues - and programmed in hardware to achieve the hardware settling de= lay. - - qcom,avg-samples: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - Number of samples to be used for measurement. - Averaging provides the option to obtain a single measurement - from the ADC that is an average of multiple samples. The value - selected is 2^(value). - - required: - - reg + $ref: /schemas/iio/adc/qcom,spmi-vadc-common.yaml =20 allOf: - if: --=20 2.25.1 From nobody Sat Feb 7 05:49:39 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0865B21CC5A for ; Wed, 28 Jan 2026 11:24:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769599496; cv=none; b=N2qPPw34fYWuBRoBt7XNoV841IRJTPqjHS4jKdCuV25SzfKqT+VdyyMB8B3nIGcxiwiPVnV1UdvGXhNXPR1JWVTF9OJu1O9UjD+rQAKUJw0U/kVqnwUIPq3vErsZr9mpqY2ATXptbKXOVa6ZW6WOHohDpBuaAUAO7Jb1TUy/Woc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769599496; c=relaxed/simple; bh=CbgzOaYDkc3bXhiSUZkzlP8DjhXVBP0eRFGEsmWlQbQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=H5Nf7GEH4wvpNy6tfBpQqZhlwXtN/CvYmtxua0gnJOXd7PCbkQ5Cdq2yyBf98TZ/Z6PmCNRr2G4/grQETRhn8g2li/4YQK0OKI6jo7h7Mk61nRbGDUCOFTi7jpgwQOdoBPyPvDdKRmnWnN1nDv4MloiSZ3wtVC+RoHIM/tL3GxI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=NEZ1O9C1; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=blXiCWjk; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="NEZ1O9C1"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="blXiCWjk" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60S92ccw041993 for ; Wed, 28 Jan 2026 11:24:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=yRCNcS5A6Eu GBIPJ6FqXwxvOo4jjK2JrobpZz5iBr1c=; b=NEZ1O9C1xjmXUug5MGg9HJlfDQZ VLfM7SzWKCQhIf3apuStnyMQF5RT1FWABL2S0tqvYAqQ6g/GndyzTQTtC6dW4Ajv pX14Qf4R83YEZiLuX+ylcwSNse+uB26O8ZoQqXqd5a9+Sm+Bkqt0CgJD0Eg6dmIt Qzv13YpxZ0tih04/8idz9dQTw88A4ZQx/yZBaIT6gPIF+u4bvPYzDQiXVXGSDDaQ 97whNgBIQdeXFyQvZcOWT/oNCvozwxU0G6vgeNBZfhreqoxnPHAuW2PzXgX3jSM/ j9flU9UXYPO8ab2Wt1q2m9ukTd8d1GLuRdXZnS1eveYZrw2Z8G4IOS0DhfQ== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4by355ttq0-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 28 Jan 2026 11:24:52 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-c6310f81285so9593381a12.0 for ; Wed, 28 Jan 2026 03:24:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1769599492; x=1770204292; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yRCNcS5A6EuGBIPJ6FqXwxvOo4jjK2JrobpZz5iBr1c=; b=blXiCWjkjDlrOiP8vQnH3fkTVOL05cLzr5Bw9CW47lR3+mfxzleoW4xgHhZv/x40QB xSyHYB+xaPNiteTE+lPVoq/Xm0DMsAnZVExA9cyAfuDqZObpM0mjXc541V8fEvX4Sn8A NqJNLa7yOv52kYW6GhleiVaIpOxm17qWsSLGLugQ2Lr+q/e0kJIWMyR8Wz7FauXGRgSX 8VKwdkQ5dhVlI9XlVZuPo5B2HaBSEMsoq4ie3RBEZx79+knNHvksF9cmrrl3VrLFZ3vM 6037EC/BSYyTUkUdA4wfO4Ko6s+YUqhe7nGs+DUUD6hWUVUkaRwlr2nm/bdwWQfhidbj 7+Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769599492; x=1770204292; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=yRCNcS5A6EuGBIPJ6FqXwxvOo4jjK2JrobpZz5iBr1c=; b=Wcs2tAET56BuvtITcTNLqwBAsBEbKTcgF7OnP/UbIhm9HIpElBWfQ8hdAatRofG81E /N805UftBOx6uYeCUgewxj0B9+k89NXFafO2Fbk9FG+UMxT7BYbqZ0isW9mgjzmlqKvy EYegV5thdTTMPF65AwDlr2wK+6WeZx9Wylg3rU/BT17QYXDTLWrqlm4rTDr8INc7mN6k P7c1OBHFhUnj6JgP9FX0UZSHndvUNeJo+R0POxDDk117k8SOT9JG2JoF0zyKTgG8S/tD mUIFiynxWSeITAziOjMEMbujpzsg6sN5nvIsmRZKPX6AIf5FGgUX2jfYCm0B/FgQdaiN yFLg== X-Forwarded-Encrypted: i=1; AJvYcCWZXdu3QHGvt/EvzFAfyqZyRegcWcOJmAC5d48wC+0gwWXc4H118YOPhS/RZFnXXE/pjfArPabY8FSgkFo=@vger.kernel.org X-Gm-Message-State: AOJu0YyPk9/yv0OX6sAozgR6GNpEbjNsY8PIx6I+8M0PcF2+NaQ+coTE QRZERyBaXXQGDseJ0/FK2GxgWJKJxCG7KKfmCqjQ9VCJ9jjrOdbhSRDPZUTU3O9hHXvEFhxeAPK ZEmRIsJMsf7s3TXvFr8Ucnt43mqM12EJhz8pP+VSqCr8BBZLIxcfo24oGOajcmBkuAO0= X-Gm-Gg: AZuq6aIZTPTXR7idUlsLWXirQMiZqsJIQVBEZwGLsVVoybqet+ji8vHEzc7WEwjwkic rRZPJFmtQiUTGL4Jy35XK6qMFVhjtFOV/x5CF79jAaoTGUWNwgRTnDB3oI33CnDTwKcpMHqsJxI 06VUCHPfth+9pp2zZ4o+o9+vo65wamZphTYVFogiPR3ZMmTc+9G03kRhABbjOf8hLt1+W9jteL4 QEZoJuzxalYlMVcdSekAY49T6CAbjk2teIkgu1Hj7HglD4FZpCF3EaMT1HoiXOIwagkabTktWJ+ q/pKiEzuaRwaOTuO2RuEXGZ9VyT0zkk6Y2AdaqKBJYtIrFPf6NdOL+vaNF8uEto96n41/SQ2zsA h7AERRCs/4s6MnQT1/m/RAjVYs9eR1DRArtq8AJhr9EbJ X-Received: by 2002:a05:6a20:9f03:b0:35f:46d3:f28e with SMTP id adf61e73a8af0-38ec6555b6amr4437356637.43.1769599491999; Wed, 28 Jan 2026 03:24:51 -0800 (PST) X-Received: by 2002:a05:6a20:9f03:b0:35f:46d3:f28e with SMTP id adf61e73a8af0-38ec6555b6amr4437315637.43.1769599491459; Wed, 28 Jan 2026 03:24:51 -0800 (PST) Received: from hu-jprakash-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a88b4c40a8sm21984605ad.51.2026.01.28.03.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 03:24:51 -0800 (PST) From: Jishnu Prakash To: jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org, daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org, subbaraman.narayanamurthy@oss.qualcomm.com, david.collins@oss.qualcomm.com, anjelique.melendez@oss.qualcomm.com, kamal.wadhwa@oss.qualcomm.com Cc: rui.zhang@intel.com, lukasz.luba@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, jishnu.prakash@oss.qualcomm.com, quic_kotarake@quicinc.com, neil.armstrong@linaro.org, stephan.gerhold@linaro.org, Jonathan Cameron , Krzysztof Kozlowski Subject: [PATCH V9 2/4] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC Date: Wed, 28 Jan 2026 16:54:18 +0530 Message-Id: <20260128112420.695518-3-jishnu.prakash@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260128112420.695518-1-jishnu.prakash@oss.qualcomm.com> References: <20260128112420.695518-1-jishnu.prakash@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=YNWSCBGx c=1 sm=1 tr=0 ts=6979f204 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=gEfo2CItAAAA:8 a=i0EeH86SAAAA:8 a=YrMGt2jeDSw4g2R_97MA:9 a=x9snwWr2DeNwDh03kgHS:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: i2Slo5oh4CTYvvebWaMd8aqaXZUXFAtq X-Proofpoint-GUID: i2Slo5oh4CTYvvebWaMd8aqaXZUXFAtq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI4MDA5MyBTYWx0ZWRfXyE91Im4OUpTt pJp/VngtJk42w9Y2oUXnYysKfwJttuWobU4wPAETSoZgxMEFC+4TqnlIPxk400eh2waIWR6VDHQ RlFWFmjRekOleP2KDh1XkcrsNDjiGlhCfYknlENMpoYd5mendTt/Ia4p98JnTgJTC5NwKSGrgys /Xt4E/2kNIIZgiwtKOpqZf+7HWC8KxUz1o1GFOso2+9daryRN/3U3tkgdCke8xMZTyg69vlaTHv gExZWgg3RnZbRoxfwv1sv3xxaVAUG0HxaTe6L659Q231MKgBBmLtd59fjY98qTM9JedqsczFs5j D7SaqD/FHufD8zawoeHSxMT26uupSL6QvqWsWHNsDHQIHKdmw9UOilzgg0j+2yE2LB+ZW+JCZKV pVcvxjuKzoiQpamvNh7VfATm5n7y5zomPNU8st6OFTaYz68an0r//9yuJ5jILqCkuTaKg7mwiS0 +NBWGrRf/Qgq+rO+jWQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-28_02,2026-01-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 spamscore=0 impostorscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601280093 Content-Type: text/plain; charset="utf-8" For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs going through PBS(Programmable Boot Sequence) firmware through a single register interface. This interface is implemented on SDAM (Shared Direct Access Memory) peripherals on the master PMIC PMK8550 rather than a dedicated ADC peripheral. Add documentation for PMIC5 Gen3 ADC and update SPMI PMIC bindings to allow ADC5 Gen3 as adc@ subnode. Acked-by: Jonathan Cameron Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jishnu Prakash --- Changes since v7: - Dropped ADC5 GEN3 channel macro definitions from bindings, based on discussion with Krzysztof concluded here:=20 https://lore.kernel.org/all/d10e2eea-4b86-4e1a-b7a0-54c55907a605@oss.qual= comm.com/, to be added separately in other patches. - Fixed quotes to use only double quotes for "#address-cells", "#size-cells" and "#io-channel-cells" properties, to address Krzysztof's comment. - Removed inclusion of ADC channel macro header files from ADC5 Gen3 example and replaced the macros used in the "reg" properties in channel nodes with the actual hex values. - Removed update made under `reg` property in Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc-common.yaml which referenced ADC macro binding files, to align with change made in patch 1 of this series. Changes since v6: - Updated SPMI PMIC bindings to allow ADC5 Gen3 as adc@ subnode, to address Neil's comment. - Replaced 2025 copyright in newly added files with yearless copyright, following new internal guidelines. - Collected Acked-by tag from Jonathan. Changes since v5: - Addressed following comments from Krzysztof: - Increased line wrap length for top-level device description. - Added more details in binding description explaining how number of SDAM peripherals used for ADC is allocated per SoC. - Dropped "interrupt-names" property. - Moved `required` block to after the list of all properties. - Dropped | from patternProperties description. - Renamed per-PMIC binding files listing ADC channel macro names. - Addressed following comments from Jonathan: - Moved ref before description, under patternProperties. - Arranged enum under qcom,hw-settle-time as groups of 8. Changes since v4: - Added ADC5 Gen3 documentation in a separate new file to avoid complicating existing VADC documentation file further to accomodate this device, as suggested by reviewers. Changes since v3: - Added ADC5 Gen3 documentation changes in existing qcom,spmi-vadc.yaml file instead of adding separate file and updated top-level constraints in docu= mentation file based on discussion with reviewers. - Dropped default SID definitions. - Addressed other reviewer comments. Changes since v2: - Moved ADC5 Gen3 documentation into a separate new file. Changes since v1: - Updated properties separately for all compatibles to clarify usage of new properties and updates in usage of old properties for ADC5 Gen3. - Avoided updating 'adc7' name to 'adc5 gen2' and just left a comment mentioning this convention. - Used predefined channel IDs in individual PMIC channel definitions instead of numeric IDs. - Addressed other comments from reviewers. .../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml | 151 ++++++++++++++++++ .../bindings/iio/adc/qcom,spmi-vadc.yaml | 2 + .../bindings/mfd/qcom,spmi-pmic.yaml | 1 + 3 files changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc= 5-gen3.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.= yaml b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml new file mode 100644 index 000000000000..149f4af8f4b8 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC ADC5 Gen3 + +maintainers: + - Jishnu Prakash + +description: | + SPMI PMIC5 Gen3 voltage ADC (ADC) provides interface to clients to read + voltage. It is a 16-bit sigma-delta ADC. It also performs the same therm= al + monitoring function as the existing ADC_TM devices. + + The interface is implemented on SDAM (Shared Direct Access Memory) perip= herals + on the master PMIC rather than a dedicated ADC peripheral. The number of= PMIC + SDAM peripherals allocated for ADC is not correlated with the PMIC used,= it is + programmed in FW (PBS) and is fixed per SOC, based on the SOC requiremen= ts. + All boards using a particular (SOC + master PMIC) combination will have = the + same number of ADC SDAMs supported on that PMIC. + +properties: + compatible: + const: qcom,spmi-adc5-gen3 + + reg: + items: + - description: SDAM0 base address in the SPMI PMIC register map + - description: SDAM1 base address + minItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#io-channel-cells": + const: 1 + + "#thermal-sensor-cells": + const: 1 + + interrupts: + items: + - description: SDAM0 end of conversion (EOC) interrupt + - description: SDAM1 EOC interrupt + minItems: 1 + +patternProperties: + "^channel@[0-9a-f]+$": + type: object + unevaluatedProperties: false + $ref: /schemas/iio/adc/qcom,spmi-vadc-common.yaml + description: + Represents the external channels which are connected to the ADC. + + properties: + qcom,decimation: + enum: [ 85, 340, 1360 ] + default: 1360 + + qcom,hw-settle-time: + enum: [ 15, 100, 200, 300, 400, 500, 600, 700, + 1000, 2000, 4000, 8000, 16000, 32000, 64000, 128000 ] + default: 15 + + qcom,avg-samples: + enum: [ 1, 2, 4, 8, 16 ] + default: 1 + + qcom,adc-tm: + description: + ADC_TM is a threshold monitoring feature in HW which can be enab= led + on any ADC channel, to trigger an IRQ for threshold violation. In + earlier ADC generations, it was implemented in a separate device + (documented in Documentation/devicetree/bindings/thermal/qcom-sp= mi-adc-tm5.yaml.) + In Gen3, this feature can be enabled in the same ADC device for = any + channel and threshold monitoring and IRQ triggering are handled = in FW + (PBS) instead of another dedicated HW block. + This property indicates ADC_TM monitoring is done on this channe= l. + type: boolean + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - "#io-channel-cells" + - interrupts + +additionalProperties: false + +examples: + - | + #include + + pmic { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@9000 { + compatible =3D "qcom,spmi-adc5-gen3"; + reg =3D <0x9000>, <0x9100>; + interrupts =3D <0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #io-channel-cells =3D <1>; + #thermal-sensor-cells =3D <1>; + + /* PMK8550 Channel nodes */ + channel@3 { + reg =3D <0x3>; + label =3D "pmk8550_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@44 { + reg =3D <0x44>; + label =3D "pmk8550_xo_therm"; + qcom,pre-scaling =3D <1 1>; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,adc-tm; + }; + + /* PM8550 Channel nodes */ + channel@103 { + reg =3D <0x103>; + label =3D "pm8550_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@78f { + reg =3D <0x78f>; + label =3D "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling =3D <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg =3D <0x203>; + label =3D "pm8550vs_c_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml = b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml index 16c80709a3ee..72188041e8b5 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.yaml @@ -15,6 +15,8 @@ description: | voltage. The VADC is a 15-bit sigma-delta ADC. SPMI PMIC5/PMIC7 voltage ADC (ADC) provides interface to clients to read voltage. The VADC is a 16-bit sigma-delta ADC. + Note that PMIC7 ADC is the generation between PMIC5 and PMIC5 Gen3 ADC, + it can be considered like PMIC5 Gen2. =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Do= cumentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index 65c80e3b4500..cc5de26bbf57 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -129,6 +129,7 @@ patternProperties: "^adc@[0-9a-f]+$": type: object oneOf: + - $ref: /schemas/iio/adc/qcom,spmi-adc5-gen3.yaml# - $ref: /schemas/iio/adc/qcom,spmi-iadc.yaml# - $ref: /schemas/iio/adc/qcom,spmi-rradc.yaml# - $ref: /schemas/iio/adc/qcom,spmi-vadc.yaml# --=20 2.25.1 From nobody Sat Feb 7 05:49:39 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77F932FB0BA for ; Wed, 28 Jan 2026 11:25:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769599506; cv=none; b=aqdRu/GcI71iglaUOCdiZRjQ5Wn5+YKmuaNc1mhWiQ+vWpzydOppM/qEINnGNgzP+6EVWoVx29refDZfwYcsrQhkdWpG6rAUQt5MV0vm6PcQxPnCHw97DB73VIeTX0lAaxwuYQgMtKnk2WpECr2GiBj/kpBcWNAgpi7w22sbr7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769599506; c=relaxed/simple; bh=0k7H37+zug5opDdoeWI3/3ruPxuiDSi0u6QQ1NepEtU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tKzHvZsiV/wsHjOzIcZNpMCwk03XjLTLaV937kPThsUsFwU6NwFHidiUYvc5bSvgG0KbpCzc0YvoSwcAzfqCUYwC/xzkSHTposMY4mZisACf+6jDQO4l5nnQHFoIceFnB/olZ03L9ulXZYXj8SqurdmDjhR/vtfk0cB9Am9JlQ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=QIeDPzan; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=OU2KxILa; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="QIeDPzan"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="OU2KxILa" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60S923EC1406292 for ; Wed, 28 Jan 2026 11:25:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=3KWVi4Y5EfG LqCGxzxYMqVhko38niAHTJr8Kb3uj2IM=; b=QIeDPzanyXhiPmLSEyowr4SEg5k QedBzXxncLliOZNGUsFBPTZsjC1BIZdTUl4q1ym/xb0kuIEiG0+Wxz9X6ch1z4nn 8aXa8/ki8FPXbqIlltplrYq4xOjN5eDh1VZ+wIUH0QtcfYUF5vamZTgdgDsp80Fm I7g6nXOvY9XOTJpXLxgTS8j/dRDusmgdLikeB+HgffmVpTELFcGD54a2Z5iT1Xry iuS/vP9uK7DIOyZqJciqhQACPcb7zR4Z7d9XRY5VEqut+pxSRKBazA699fzprCvq cAkkMYlezhdYIoTRXkp/bBWnWOq0ZjJ3NK9TzcCc+OR/58zG/fMI1tbVn4w== Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4by4dytjt9-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 28 Jan 2026 11:25:02 +0000 (GMT) Received: by mail-pg1-f197.google.com with SMTP id 41be03b00d2f7-c5291b89733so4024930a12.0 for ; Wed, 28 Jan 2026 03:25:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1769599502; x=1770204302; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3KWVi4Y5EfGLqCGxzxYMqVhko38niAHTJr8Kb3uj2IM=; b=OU2KxILaq6xNVoAFQd18FVQYPlC4sgIRpNzrdfxZzDWe6+7c0dWNR5TGLyEnN5Wu8E YrK7sig19OULwF0gjxAXaLpK0yR3+IsS7izmENZ3jUW4GLKPirPxnmuopVii0Rqr8gF9 AbKVD8HPjutTGnb0eJRPVaPI7laEnWYtJBz8Fai6llWhAeTVodU6eMd1GvYzKTgTRpc4 hs1zubULxCoKJpXWm307zqyLgbiJxfP9kcDnS5jFRzmmIj6kQssq2NaZF/Zw3HcP9ex+ bJd86uvg4a4ry8u2/irdBDp2kWIOtUoFgHFd93y0bWVRY4on0P13YKHLt/MbokQ2R2iH ugsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769599502; x=1770204302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=3KWVi4Y5EfGLqCGxzxYMqVhko38niAHTJr8Kb3uj2IM=; b=dvvTkJXB0Ll1Yt6Q/wDdpJpYMKgRQbpzv5IjUdL1cNCHNJHNbW1qNre36pPyQO4jZ2 h2FREYHpX5VCy4GFsSMv6aP76DI399MFnCACyoLBUfMgTGa8Fk3kvFyyPdnzQVYi6Lvr P0gimwu0N5HQVW0Xw4BPfM0QnWQNG9fbd645jfMbAaOs9VqujCFGiCtRxKtBvju1lCtJ LYSJIHsZ7DlkHmRyeGi8eLJqKlXPJDhPZmABDAvGg3qzYt24FDtR7Laal4s/aAmrC5t/ HSd7ppl8DEtlYVJIrhEWkPcP8LuSdebG9XKBwdjJrkaOtBEcFaIaX8w1O2BcxSVV8dCH XRIA== X-Forwarded-Encrypted: i=1; AJvYcCVbHJF2gTeeRLXYKtPfiYPSW0Q+MJ+9UxGTduV5AYlkRDtBwxm9+s6+/5Hb+fQOfgOIbFXNzqVKpvULJwU=@vger.kernel.org X-Gm-Message-State: AOJu0YzCYG7tMHheq9F+6JbN9Bq7vr9s+VcoShmGDhB9mjEXrPVFbuIY Ku254Zi6m5TON4nP/UD4q5B7B5Zr+4R1EI7w5NSRAnVtLDsbuSGHD03on7DCA8NKEux12U32N37 hrZd5gdrRnsWNmBiXMCxBJItQCy2Bnnz9AEyCm/4ye0o3wLGWrZybMCuZ03k80MxijKQ= X-Gm-Gg: AZuq6aKn6A042EoLcUWovtU9d11JfsXBlmSddVHYkWVwz0T1pihtPHlKciEV1tiKacx A+iWoc13hDQNjWwPr5CjA1O3pxG7zWwYFDCrOYLi8un1jjO1xp3cFzxG22PCJhlk46QYllyIWZw Z/bR8MTKvW6MmBJ8CrNkjwTDqwrMZofaGh5hfI61kGuF5LGZ2BnWrVq0sNUpXNDct6PHS7EB6Ke 7bZhilkNw1E+gfmQxUfZT5uCQQCsQtLHL5tVHwH+CzY+9QiSDXp3fdh1n6bV+riD+FqT6/pQsz8 qNSsrhi2KZ9knH9GMOODpESWIMNWFgXjUqXzQ+txTQVHbk9VPHg0nONqIZP4pLKMLlZ5L+YA/W4 /tJ4dIkOPmrvcmwR2YewFCxSrzrWBoSMsik6ctrFiAiT6 X-Received: by 2002:a05:6a20:43a9:b0:38d:fe2a:4b0a with SMTP id adf61e73a8af0-38ec6323b81mr4818484637.33.1769599501155; Wed, 28 Jan 2026 03:25:01 -0800 (PST) X-Received: by 2002:a05:6a20:43a9:b0:38d:fe2a:4b0a with SMTP id adf61e73a8af0-38ec6323b81mr4818430637.33.1769599500296; Wed, 28 Jan 2026 03:25:00 -0800 (PST) Received: from hu-jprakash-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a88b4c40a8sm21984605ad.51.2026.01.28.03.24.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 03:24:59 -0800 (PST) From: Jishnu Prakash To: jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org, daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org, subbaraman.narayanamurthy@oss.qualcomm.com, david.collins@oss.qualcomm.com, anjelique.melendez@oss.qualcomm.com, kamal.wadhwa@oss.qualcomm.com Cc: rui.zhang@intel.com, lukasz.luba@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, jishnu.prakash@oss.qualcomm.com, quic_kotarake@quicinc.com, neil.armstrong@linaro.org, stephan.gerhold@linaro.org Subject: [PATCH V9 3/4] iio: adc: Add support for QCOM PMIC5 Gen3 ADC Date: Wed, 28 Jan 2026 16:54:19 +0530 Message-Id: <20260128112420.695518-4-jishnu.prakash@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260128112420.695518-1-jishnu.prakash@oss.qualcomm.com> References: <20260128112420.695518-1-jishnu.prakash@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=XqT3+FF9 c=1 sm=1 tr=0 ts=6979f20e cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=hLksN_2OI4otqoaXwe4A:9 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: RwrIPZydyJ_TyTq7cDugLmGU3c4qYBWf X-Proofpoint-ORIG-GUID: RwrIPZydyJ_TyTq7cDugLmGU3c4qYBWf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI4MDA5MyBTYWx0ZWRfX6Q1D8/leJU9t t/qFWo+VUcULiolNADaqFB7mdtYDHxlKzQ8Jle1okyiGleC25OqtQi6P+7UA7tnOGFokowSzZjU 6heY3CQ8QkrpuaTYyToDgjFtfi5iu6wbl+GvlXoE0eJRXFM/vcJPlyUU6u9NBDg090f3OrUITkB 2PA7Sa/1/5qP+7AGYayaWLkE6KPUEl4eBpoMlAJ9tpEJlsuWgeM6/kO9NgXSMGCkanMmo/PvhBG TZbVcRIyB+JDNXKKd7I0U9IfrvfOQuyauSpJIYL34ZWZnB6Pb2WoMhuytr7lp4O3zDFFDetQblH FWTImA2vtoAAGAtKnKIMPM6mDp97IgQdte+U6Yno9VWoCjaicNj03zFjt6wf7buF+ToyhzAUEKs zT502mpqT1LsjnHfGnWbI24GsBJ/ZZzN85eLm1BdDdS/KDoH7mqcf2molGujgkzJCqwUBFiVxc0 trG6axzKEDbm4uFEFPw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-28_02,2026-01-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601280093 Content-Type: text/plain; charset="utf-8" The ADC architecture on PMIC5 Gen3 is similar to that on PMIC5 Gen2, with all SW communication to ADC going through PMK8550 which communicates with other PMICs through PBS. One major difference is that the register interface used here is that of an SDAM (Shared Direct Access Memory) peripheral present on PMK8550. There may be more than one SDAM used for ADC5 Gen3 and each has eight channels, which may be used for either immediate reads (same functionality as previous PMIC5 and PMIC5 Gen2 ADC peripherals) or recurring measurements (same as ADC_TM functionality). By convention, we reserve the first channel of the first SDAM for all immediate reads and use the remaining channels across all SDAMs for ADC_TM monitoring functionality. Add support for PMIC5 Gen3 ADC driver for immediate read functionality. ADC_TM is implemented as an auxiliary thermal driver under this ADC driver. Signed-off-by: Jishnu Prakash --- Changes since v8: - Dropped the common module (drivers/iio/adc/qcom-adc5-gen3-common.c) and m= oved all of its contents to drivers/iio/adc/qcom-spmi-adc5-gen3.c as suggested= by Dmitry. - Made following changes to address Dmitry's comment to use module_auxiliar= y_driver() in auxiliary driver patch, by simplifying auxiliary device structures: - Added function pointer for TM interrupt handler callback under struct a= dc5_chip (to be called in case of TM interrupt on first SDAM), to replace the tm_event_notify() callback. - Add new exported function (adc5_gen3_register_tm_event_notifier()) to b= e called by TM auxiliary driver in its probe to initialize the above callback fu= nction. - Updated adc5_gen3_isr() to call this TM callback function instead of tm_event_notify() callback from the wrapper struct adc_tm5_auxiliary_dr= v. - Completely dropped the above wrapper struct definition. - Made following changes to address Jonathan's comments: - Updated header files included in drivers/iio/adc/qcom-spmi-adc5-gen3.c = and=20 include/linux/iio/adc/qcom-adc5-gen3-common.h to follow IWYU (include-w= hat-you-use) principles. - Dropped comment inside adc5_chip struct definition describing mutex loc= k. - Dropped ADC5_GEN3_TEMP_ALARM_LITE channel as it had some inaccuracy issue= , which is being debugged internally. Will add it in a separate patch along with = channel user. - Replaced dev_err() with dev_err_probe() in adc5_get_fw_data. Changes since v7: - Addressed following comments from Jonathan: - Included regmap header file in drivers/iio/adc/qcom-adc5-gen3-common.c. - Increased comment wrap length in adc5_gen3_configure() and=20 struct adc5_chip definition. - Updated error checks in adc5_gen3_isr() to remove NULL check for adrv_tm and keep (!adrv_tm->tm_event_notify) error check alone within if() condition. - Removed sid initialization in adc5_gen3_get_fw_channel_data() - Added definitions for ADC channel macros used in adc5_gen3_chans_pmic[] in include/linux/iio/adc/qcom-adc5-gen3-common.h instead of=20 include/dt-bindings/iio/adc/qcom,spmi-vadc.h, as this latter file will be moved out of bindings folder in a separate change. Also removed its inclusion in drivers/iio/adc/qcom-spmi-adc5-gen3.c. - Cleaned up local variable declarations in adc5_gen3_isr() and adc5_gen3_get_fw_channel_data() and added local variable for adc->dev in adc5_get_fw_data(). - Fixed error message after platform_get_irq() call in adc5_gen3_probe() to print IRQ number correctly. - Added a check in adc5_gen3_get_fw_channel_data() to exit with error if ADC channel value obtained from `reg` channel property is not among the supported ones in the array adc5_gen3_chans_pmic[]. - Corrected the value used in checking for max valid ADC channel value, in adc5_gen3_get_fw_channel_data(). Changes since v6: - Addressed following comments from Jonathan: - Moved functions exported in drivers/iio/adc/qcom-adc5-gen3-common.c into namespace "QCOM_SPMI_ADC5_GEN3". - Increased line wrap length for comments. - Added local variable for adc->dev in adc5_gen3_isr(). - Shifted debug print showing IRQ status registers in adc5_gen3_isr() to before tm_status[] check. - Fixed indentation and brackets in adc5_gen3_get_fw_channel_data(). - Cleaned up array formatting in adc5_gen3_data_pmic struct. - Used scoped variant of device_for_each_child_node() in adc5_get_fw_data= (). - Updated auxiliary device cleanup handling to fix memory freeing issues, by adding empty auxiliary device release function. - Used devm_mutex_init() in adc5_gen3_probe(). - Updated virtual channel macro name from V_CHAN to ADC5_GEN3_V_CHAN. - Set IIO device name to "spmi-adc5-gen3". - Added __acquires and __releases macros for exported mutex lock and unlock functions in drivers/iio/adc/qcom-spmi-adc5-gen3.c. - Added error check to fail probe in case adding auxiliary TM device fails. - Replaced 2025 copyright in newly added files with yearless copyright, following new internal guidelines. Changes since v5: - Addressed following comments from Jonathan: - Corrected line wrap length in Kconfig and driver files. - Replaced usleep_range() with fsleep() in adc5_gen3_poll_wait_hs() - Corrected all files to follow kernel-doc formatting fully. - Removed IIO_CHAN_INFO_RAW case in adc5_gen3_read_raw() - Cleaned up formatting in adc5_gen3_data_pmic struct and in other struct definitions. - Updated adc5_gen3_add_aux_tm_device() to keep errors alone out of line. - Split mutex function exported to ADC_TM driver into separate functions for acquiring and releasing mutex. - Removed num_sdams member from struct adc5_chip. - Fixed dev_err_probe() print in adc5_gen3_probe(). - Updated logic for acquiring IRQ numbers to account for removing "interrupt-names" DT property. - Included bitfield.h header file in drivers/iio/adc/qcom-adc5-gen3-common.c to fix kernel bot error. Changes since v4: - Moved out common funtions from newly added .h file into a separate .c file to avoid duplicating them and updated interrupt name, as suggested by Krzysztof. Updated namespace export symbol statement to have a string as second argument to follow framework change. Changes since v3: - Split out TM functionality into auxiliary driver in separate patch and added required changes in main driver, as suggested by Dmitry. - Addressed other reviewer comments in main driver patch.=20 Changes since v1: - Removed datashet_name usage and implemented read_label() function - In probe, updated channel property in iio_chan_spec from individual channel to virtual channel and set indexed property to 1, due to the above change. - Updated order of checks in ISR - Removed the driver remove callback and replaced with callbacks in a devm_add_action call in probe. - Addressed other comments from reviewers. drivers/iio/adc/Kconfig | 26 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/qcom-spmi-adc5-gen3.c | 860 ++++++++++++++++++ include/linux/iio/adc/qcom-adc5-gen3-common.h | 211 +++++ 4 files changed, 1098 insertions(+) create mode 100644 drivers/iio/adc/qcom-spmi-adc5-gen3.c create mode 100644 include/linux/iio/adc/qcom-adc5-gen3-common.h diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 58da8255525e..5300e9236ba8 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1329,6 +1329,32 @@ config QCOM_SPMI_ADC5 To compile this driver as a module, choose M here: the module will be called qcom-spmi-adc5. =20 +config QCOM_SPMI_ADC5_GEN3 + tristate "Qualcomm Technologies Inc. SPMI PMIC5 GEN3 ADC" + depends on SPMI && THERMAL + select REGMAP_SPMI + select QCOM_VADC_COMMON + select AUXILIARY_BUS + help + IIO Voltage PMIC5 Gen3 ADC driver for Qualcomm Technologies Inc. + + The driver supports reading multiple channels. The ADC is a 16-bit + sigma-delta ADC. The hardware supports calibrated results for + conversion requests and clients include reading phone power supply + voltage, on board system thermistors connected to the PMIC ADC, + PMIC die temperature, charger temperature, battery current, USB + voltage input and voltage signals connected to supported PMIC GPIO + pins. The hardware supports internal pull-up for thermistors and can + choose between a 30k, 100k or 400k ohm pull up using the ADC channels. + + In addition, the same driver supports ADC thermal monitoring devices + too. They appear as thermal zones with multiple trip points. A thermal + client sets threshold temperature for both warm and cool trips and + gets updated when a threshold is reached. + + To compile this driver as a module, choose M here: the module will + be called qcom-spmi-adc5-gen3. + config RCAR_GYRO_ADC tristate "Renesas R-Car GyroADC driver" depends on ARCH_RCAR_GEN2 || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 7cc8f9a12f76..cb1874fd7912 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -113,6 +113,7 @@ obj-$(CONFIG_PAC1934) +=3D pac1934.o obj-$(CONFIG_PALMAS_GPADC) +=3D palmas_gpadc.o obj-$(CONFIG_QCOM_PM8XXX_XOADC) +=3D qcom-pm8xxx-xoadc.o obj-$(CONFIG_QCOM_SPMI_ADC5) +=3D qcom-spmi-adc5.o +obj-$(CONFIG_QCOM_SPMI_ADC5_GEN3) +=3D qcom-spmi-adc5-gen3.o obj-$(CONFIG_QCOM_SPMI_IADC) +=3D qcom-spmi-iadc.o obj-$(CONFIG_QCOM_SPMI_RRADC) +=3D qcom-spmi-rradc.o obj-$(CONFIG_QCOM_SPMI_VADC) +=3D qcom-spmi-vadc.o diff --git a/drivers/iio/adc/qcom-spmi-adc5-gen3.c b/drivers/iio/adc/qcom-s= pmi-adc5-gen3.c new file mode 100644 index 000000000000..f8168a14b907 --- /dev/null +++ b/drivers/iio/adc/qcom-spmi-adc5-gen3.c @@ -0,0 +1,860 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ADC5_GEN3_VADC_SDAM 0x0 + +struct adc5_chip; + +/** + * struct adc5_channel_prop - ADC channel structure + * @common_props: structure with ADC channel properties (common to TM usag= e). + * @adc_tm: indicates TM type if the channel is used for TM measurements. + * @chip: pointer to top-level ADC device structure. + */ +struct adc5_channel_prop { + struct adc5_channel_common_prop common_props; + int adc_tm; + struct adc5_chip *chip; +}; + +/** + * struct adc5_chip - ADC private structure. + * @dev: SPMI ADC5 Gen3 device. + * @dev_data: Top-level ADC device data. + * @nchannels: number of ADC channels. + * @chan_props: array of ADC channel properties. + * @iio_chans: array of IIO channels specification. + * @complete: ADC result notification after interrupt is received. + * @lock: ADC lock for access to the peripheral, to prevent concurrent + * requests from multiple clients. + * @data: software configuration data. + * @n_tm_channels: number of ADC channels used for TM measurements. + * @handler: TM callback to be called for threshold violation interrupt + * on first SDAM. + * @tm_aux: pointer to auxiliary TM device. + */ +struct adc5_chip { + struct device *dev; + struct adc5_device_data dev_data; + unsigned int nchannels; + struct adc5_channel_prop *chan_props; + struct iio_chan_spec *iio_chans; + struct completion complete; + struct mutex lock; + const struct adc5_data *data; + unsigned int n_tm_channels; + void (*handler)(struct auxiliary_device *tm_aux); + struct auxiliary_device *tm_aux; +}; + +int adc5_gen3_read(struct adc5_device_data *adc, unsigned int sdam_index, + u16 offset, u8 *data, int len) +{ + return regmap_bulk_read(adc->regmap, + adc->base[sdam_index].base_addr + offset, + data, len); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_read, "QCOM_SPMI_ADC5_GEN3"); + +int adc5_gen3_write(struct adc5_device_data *adc, unsigned int sdam_index, + u16 offset, u8 *data, int len) +{ + return regmap_bulk_write(adc->regmap, + adc->base[sdam_index].base_addr + offset, + data, len); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_write, "QCOM_SPMI_ADC5_GEN3"); + +static int adc5_gen3_read_voltage_data(struct adc5_chip *adc, u16 *data) +{ + u8 rslt[2]; + int ret; + + ret =3D adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_CH_DATA0(0), rslt, sizeof(rslt)); + if (ret) + return ret; + + *data =3D get_unaligned_le16(rslt); + + if (*data =3D=3D ADC5_USR_DATA_CHECK) { + dev_err(adc->dev, "Invalid data:%#x\n", *data); + return -EINVAL; + } + + dev_dbg(adc->dev, "voltage raw code:%#x\n", *data); + + return 0; +} + +void adc5_gen3_update_dig_param(struct adc5_channel_common_prop *prop, u8 = *data) +{ + /* Update calibration select and decimation ratio select */ + *data &=3D ~(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK | ADC5_GEN3_DIG_PARAM_DEC_R= ATIO_SEL_MASK); + *data |=3D FIELD_PREP(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK, prop->cal_method); + *data |=3D FIELD_PREP(ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK, prop->decim= ation); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_update_dig_param, "QCOM_SPMI_ADC5_GEN3"); + +#define ADC5_GEN3_READ_CONFIG_REGS 7 + +static int adc5_gen3_configure(struct adc5_chip *adc, + struct adc5_channel_common_prop *prop) +{ + u8 buf[ADC5_GEN3_READ_CONFIG_REGS]; + u8 conv_req =3D 0; + int ret; + + ret =3D adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_SID, + buf, sizeof(buf)); + if (ret) + return ret; + + /* Write SID */ + buf[0] =3D FIELD_PREP(ADC5_GEN3_SID_MASK, prop->sid); + + /* + * Use channel 0 by default for immediate conversion and to indicate + * there is an actual conversion request + */ + buf[1] =3D ADC5_GEN3_CHAN_CONV_REQ | 0; + + buf[2] =3D ADC5_GEN3_TIME_IMMEDIATE; + + /* Digital param selection */ + adc5_gen3_update_dig_param(prop, &buf[3]); + + /* Update fast average sample value */ + buf[4] =3D FIELD_PREP(ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK, + prop->avg_samples) | ADC5_GEN3_FAST_AVG_CTL_EN; + + /* Select ADC channel */ + buf[5] =3D prop->channel; + + /* Select HW settle delay for channel */ + buf[6] =3D FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, + prop->hw_settle_time_us); + + reinit_completion(&adc->complete); + + ret =3D adc5_gen3_write(&adc->dev_data, ADC5_GEN3_VADC_SDAM, ADC5_GEN3_SI= D, + buf, sizeof(buf)); + if (ret) + return ret; + + conv_req =3D ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_CONV_REQ, &conv_req, sizeof(conv_req)); +} + +/* + * Worst case delay from PBS in readying handshake bit can be up to 15ms,= when + * PBS is busy running other simultaneous transactions, while in the best = case, + * it is already ready at this point. Assigning polling delay and retry co= unt + * accordingly. + */ + +#define ADC5_GEN3_HS_DELAY_US 100 +#define ADC5_GEN3_HS_RETRY_COUNT 150 + +int adc5_gen3_poll_wait_hs(struct adc5_device_data *adc, + unsigned int sdam_index) +{ + u8 conv_req =3D ADC5_GEN3_CONV_REQ_REQ; + int ret, count; + u8 status =3D 0; + + for (count =3D 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) { + ret =3D adc5_gen3_read(adc, sdam_index, ADC5_GEN3_HS, &status, sizeof(st= atus)); + if (ret) + return ret; + + if (status =3D=3D ADC5_GEN3_HS_READY) { + ret =3D adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CONV_REQ, + &conv_req, sizeof(conv_req)); + if (ret) + return ret; + + if (!conv_req) + return 0; + } + + fsleep(ADC5_GEN3_HS_DELAY_US); + } + + pr_err("Setting HS ready bit timed out, sdam_index:%d, status:%#x\n", + sdam_index, status); + return -ETIMEDOUT; +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_poll_wait_hs, "QCOM_SPMI_ADC5_GEN3"); + +int adc5_gen3_status_clear(struct adc5_device_data *adc, + int sdam_index, u16 offset, u8 *val, int len) +{ + u8 value; + int ret; + + ret =3D adc5_gen3_write(adc, sdam_index, offset, val, len); + if (ret) + return ret; + + /* To indicate conversion request is only to clear a status */ + value =3D 0; + ret =3D adc5_gen3_write(adc, sdam_index, ADC5_GEN3_PERPH_CH, &value, + sizeof(value)); + if (ret) + return ret; + + value =3D ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc, sdam_index, ADC5_GEN3_CONV_REQ, &value, + sizeof(value)); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_status_clear, "QCOM_SPMI_ADC5_GEN3"); + +/* + * Worst case delay from PBS for conversion time can be up to 500ms, when = PBS + * has timed out twice, once for the initial attempt and once for a retry = of + * the same transaction. + */ + +#define ADC5_GEN3_CONV_TIMEOUT_MS 501 + +static int adc5_gen3_do_conversion(struct adc5_chip *adc, + struct adc5_channel_common_prop *prop, + u16 *data_volt) +{ + unsigned long rc; + int ret; + u8 val; + + guard(mutex)(&adc->lock); + ret =3D adc5_gen3_poll_wait_hs(&adc->dev_data, ADC5_GEN3_VADC_SDAM); + if (ret) + return ret; + + ret =3D adc5_gen3_configure(adc, prop); + if (ret) { + dev_err(adc->dev, "ADC configure failed with %d\n", ret); + return ret; + } + + /* No support for polling mode at present */ + rc =3D wait_for_completion_timeout(&adc->complete, + msecs_to_jiffies(ADC5_GEN3_CONV_TIMEOUT_MS)); + if (!rc) { + dev_err(adc->dev, "Reading ADC channel %s timed out\n", + prop->label); + return -ETIMEDOUT; + } + + ret =3D adc5_gen3_read_voltage_data(adc, data_volt); + if (ret) + return ret; + + val =3D BIT(0); + return adc5_gen3_status_clear(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_EOC_CLR, &val, 1); +} + +static irqreturn_t adc5_gen3_isr(int irq, void *dev_id) +{ + struct adc5_chip *adc =3D dev_id; + struct device *dev =3D adc->dev; + struct auxiliary_device *adev; + u8 status, eoc_status, val; + u8 tm_status[2]; + int ret; + + ret =3D adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_STATUS1, &status, sizeof(status)); + if (ret) { + dev_err(dev, "adc read status1 failed with %d\n", ret); + return IRQ_HANDLED; + } + + ret =3D adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_EOC_STS, &eoc_status, sizeof(eoc_status)); + if (ret) { + dev_err(dev, "adc read eoc status failed with %d\n", ret); + return IRQ_HANDLED; + } + + if (status & ADC5_GEN3_STATUS1_CONV_FAULT) { + dev_err_ratelimited(dev, + "Unexpected conversion fault, status:%#x, eoc_status:%#x\n", + status, eoc_status); + val =3D ADC5_GEN3_CONV_ERR_CLR_REQ; + adc5_gen3_status_clear(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_CONV_ERR_CLR, &val, 1); + return IRQ_HANDLED; + } + + /* CHAN0 is the preconfigured channel for immediate conversion */ + if (eoc_status & ADC5_GEN3_EOC_CHAN_0) + complete(&adc->complete); + + ret =3D adc5_gen3_read(&adc->dev_data, ADC5_GEN3_VADC_SDAM, + ADC5_GEN3_TM_HIGH_STS, tm_status, sizeof(tm_status)); + if (ret) { + dev_err(dev, "adc read TM status failed with %d\n", ret); + return IRQ_HANDLED; + } + + dev_dbg(dev, "Interrupt status:%#x, EOC status:%#x, high:%#x, low:%#x\n", + status, eoc_status, tm_status[0], tm_status[1]); + + if (tm_status[0] || tm_status[1]) { + adev =3D adc->tm_aux; + if (!adev || !adev->dev.driver) { + dev_err(dev, "adc_tm auxiliary device not initialized\n"); + return IRQ_HANDLED; + } + + adc->handler(adev); + } + + return IRQ_HANDLED; +} + +static int adc5_gen3_fwnode_xlate(struct iio_dev *indio_dev, + const struct fwnode_reference_args *iiospec) +{ + struct adc5_chip *adc =3D iio_priv(indio_dev); + int i, v_channel; + + for (i =3D 0; i < adc->nchannels; i++) { + v_channel =3D ADC5_GEN3_V_CHAN(adc->chan_props[i].common_props); + if (v_channel =3D=3D iiospec->args[0]) + return i; + } + + return -ENOENT; +} + +static int adc5_gen3_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct adc5_chip *adc =3D iio_priv(indio_dev); + struct adc5_channel_common_prop *prop; + u16 adc_code_volt; + int ret; + + prop =3D &adc->chan_props[chan->address].common_props; + + switch (mask) { + case IIO_CHAN_INFO_PROCESSED: + ret =3D adc5_gen3_do_conversion(adc, prop, &adc_code_volt); + if (ret) + return ret; + + ret =3D qcom_adc5_hw_scale(prop->scale_fn_type, prop->prescale, + adc->data, adc_code_volt, val); + if (ret) + return ret; + + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int adc5_gen3_read_label(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, char *label) +{ + struct adc5_chip *adc =3D iio_priv(indio_dev); + struct adc5_channel_prop *prop; + + prop =3D &adc->chan_props[chan->address]; + return sprintf(label, "%s\n", prop->common_props.label); +} + +static const struct iio_info adc5_gen3_info =3D { + .read_raw =3D adc5_gen3_read_raw, + .read_label =3D adc5_gen3_read_label, + .fwnode_xlate =3D adc5_gen3_fwnode_xlate, +}; + +struct adc5_channels { + unsigned int prescale_index; + enum iio_chan_type type; + long info_mask; + enum vadc_scale_fn_type scale_fn_type; +}; + +/* In these definitions, _pre refers to an index into adc5_prescale_ratios= . */ +#define ADC5_CHAN(_type, _mask, _pre, _scale) \ + { \ + .prescale_index =3D _pre, \ + .type =3D _type, \ + .info_mask =3D _mask, \ + .scale_fn_type =3D _scale, \ + }, \ + +#define ADC5_CHAN_TEMP(_pre, _scale) \ + ADC5_CHAN(IIO_TEMP, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \ + +#define ADC5_CHAN_VOLT(_pre, _scale) \ + ADC5_CHAN(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \ + +#define ADC5_CHAN_CUR(_pre, _scale) \ + ADC5_CHAN(IIO_CURRENT, BIT(IIO_CHAN_INFO_PROCESSED), _pre, _scale) \ + +static const struct adc5_channels adc5_gen3_chans_pmic[ADC5_MAX_CHANNEL] = =3D { + [ADC5_GEN3_REF_GND] =3D ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_1P25VREF] =3D ADC5_CHAN_VOLT(0, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_VPH_PWR] =3D ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_VBAT_SNS_QBG] =3D ADC5_CHAN_VOLT(1, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_USB_SNS_V_16] =3D ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_VIN_DIV16_MUX] =3D ADC5_CHAN_TEMP(8, SCALE_HW_CALIB_DEFAULT) + [ADC5_GEN3_DIE_TEMP] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_PMIC_THERM_PM7) + [ADC5_GEN3_AMUX1_THM_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX2_THM_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX3_THM_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX4_THM_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX5_THM_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX6_THM_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX1_GPIO_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX2_GPIO_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX3_GPIO_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) + [ADC5_GEN3_AMUX4_GPIO_100K_PU] =3D ADC5_CHAN_TEMP(0, + SCALE_HW_CALIB_THERM_100K_PU_PM7) +}; + +static int adc5_gen3_get_fw_channel_data(struct adc5_chip *adc, + struct adc5_channel_prop *prop, + struct fwnode_handle *fwnode) +{ + const char *name =3D fwnode_get_name(fwnode); + const struct adc5_data *data =3D adc->data; + struct device *dev =3D adc->dev; + const char *channel_name; + u32 chan, value, sid; + u32 varr[2]; + int ret; + + ret =3D fwnode_property_read_u32(fwnode, "reg", &chan); + if (ret < 0) + return dev_err_probe(dev, ret, "invalid channel number %s\n", + name); + + /* + * Value read from "reg" is virtual channel number + * virtual channel number =3D sid << 8 | channel number + */ + sid =3D FIELD_GET(ADC5_GEN3_VIRTUAL_SID_MASK, chan); + chan =3D FIELD_GET(ADC5_GEN3_CHANNEL_MASK, chan); + + if (chan > ADC5_MAX_CHANNEL) + return dev_err_probe(dev, -EINVAL, + "%s invalid channel number %d\n", + name, chan); + + prop->common_props.channel =3D chan; + prop->common_props.sid =3D sid; + + if (!adc->data->adc_chans[chan].info_mask) + return dev_err_probe(dev, -EINVAL, "Channel %#x not supported\n", chan); + + channel_name =3D name; + fwnode_property_read_string(fwnode, "label", &channel_name); + prop->common_props.label =3D channel_name; + + value =3D data->decimation[ADC5_DECIMATION_DEFAULT]; + fwnode_property_read_u32(fwnode, "qcom,decimation", &value); + ret =3D qcom_adc5_decimation_from_dt(value, data->decimation); + if (ret < 0) + return dev_err_probe(dev, ret, "%#x invalid decimation %d\n", + chan, value); + prop->common_props.decimation =3D ret; + + prop->common_props.prescale =3D adc->data->adc_chans[chan].prescale_index; + ret =3D fwnode_property_read_u32_array(fwnode, "qcom,pre-scaling", varr, = 2); + if (!ret) { + ret =3D qcom_adc5_prescaling_from_dt(varr[0], varr[1]); + if (ret < 0) + return dev_err_probe(dev, ret, + "%#x invalid pre-scaling <%d %d>\n", + chan, varr[0], varr[1]); + prop->common_props.prescale =3D ret; + } + + value =3D data->hw_settle_1[VADC_DEF_HW_SETTLE_TIME]; + fwnode_property_read_u32(fwnode, "qcom,hw-settle-time", &value); + ret =3D qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1); + if (ret < 0) + return dev_err_probe(dev, ret, + "%#x invalid hw-settle-time %d us\n", + chan, value); + prop->common_props.hw_settle_time_us =3D ret; + + value =3D BIT(VADC_DEF_AVG_SAMPLES); + fwnode_property_read_u32(fwnode, "qcom,avg-samples", &value); + ret =3D qcom_adc5_avg_samples_from_dt(value); + if (ret < 0) + return dev_err_probe(dev, ret, "%#x invalid avg-samples %d\n", + chan, value); + prop->common_props.avg_samples =3D ret; + + if (fwnode_property_read_bool(fwnode, "qcom,ratiometric")) + prop->common_props.cal_method =3D ADC5_RATIOMETRIC_CAL; + else + prop->common_props.cal_method =3D ADC5_ABSOLUTE_CAL; + + prop->adc_tm =3D fwnode_property_read_bool(fwnode, "qcom,adc-tm"); + if (prop->adc_tm) { + adc->n_tm_channels++; + if (adc->n_tm_channels > (adc->dev_data.num_sdams * 8 - 1)) + return dev_err_probe(dev, -EINVAL, + "Number of TM nodes %u greater than channels supported:%u\n", + adc->n_tm_channels, + adc->dev_data.num_sdams * 8 - 1); + } + + return 0; +} + +static const struct adc5_data adc5_gen3_data_pmic =3D { + .full_scale_code_volt =3D 0x70e4, + .adc_chans =3D adc5_gen3_chans_pmic, + .info =3D &adc5_gen3_info, + .decimation =3D (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) + { 85, 340, 1360 }, + .hw_settle_1 =3D (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) + { 15, 100, 200, 300, + 400, 500, 600, 700, + 1000, 2000, 4000, 8000, + 16000, 32000, 64000, 128000 }, +}; + +static const struct of_device_id adc5_match_table[] =3D { + { + .compatible =3D "qcom,spmi-adc5-gen3", + .data =3D &adc5_gen3_data_pmic, + }, + { } +}; +MODULE_DEVICE_TABLE(of, adc5_match_table); + +static int adc5_get_fw_data(struct adc5_chip *adc) +{ + const struct adc5_channels *adc_chan; + struct adc5_channel_prop *chan_props; + struct iio_chan_spec *iio_chan; + struct device *dev =3D adc->dev; + unsigned int index =3D 0; + int ret; + + adc->nchannels =3D device_get_child_node_count(dev); + if (!adc->nchannels) + return dev_err_probe(dev, -EINVAL, "No ADC channels found\n"); + + adc->iio_chans =3D devm_kcalloc(dev, adc->nchannels, + sizeof(*adc->iio_chans), GFP_KERNEL); + if (!adc->iio_chans) + return -ENOMEM; + + adc->chan_props =3D devm_kcalloc(dev, adc->nchannels, + sizeof(*adc->chan_props), GFP_KERNEL); + if (!adc->chan_props) + return -ENOMEM; + + chan_props =3D adc->chan_props; + adc->n_tm_channels =3D 0; + iio_chan =3D adc->iio_chans; + adc->data =3D device_get_match_data(dev); + + device_for_each_child_node_scoped(dev, child) { + ret =3D adc5_gen3_get_fw_channel_data(adc, chan_props, child); + if (ret) + return ret; + + chan_props->chip =3D adc; + adc_chan =3D &adc->data->adc_chans[chan_props->common_props.channel]; + chan_props->common_props.scale_fn_type =3D adc_chan->scale_fn_type; + + iio_chan->channel =3D ADC5_GEN3_V_CHAN(chan_props->common_props); + iio_chan->info_mask_separate =3D adc_chan->info_mask; + iio_chan->type =3D adc_chan->type; + iio_chan->address =3D index; + iio_chan->indexed =3D 1; + iio_chan++; + chan_props++; + index++; + } + + return 0; +} + +static void adc5_gen3_uninit_aux(void *data) +{ + auxiliary_device_uninit(data); +} + +static void adc5_gen3_delete_aux(void *data) +{ + auxiliary_device_delete(data); +} + +static void adc5_gen3_aux_device_release(struct device *dev) {} + +static int adc5_gen3_add_aux_tm_device(struct adc5_chip *adc) +{ + struct tm5_aux_dev_wrapper *aux_device; + int i, ret, i_tm =3D 0; + + aux_device =3D devm_kzalloc(adc->dev, sizeof(*aux_device), GFP_KERNEL); + if (!aux_device) + return -ENOMEM; + + aux_device->aux_dev.name =3D "adc5_tm_gen3"; + aux_device->aux_dev.dev.parent =3D adc->dev; + aux_device->aux_dev.dev.release =3D adc5_gen3_aux_device_release; + + aux_device->tm_props =3D devm_kcalloc(adc->dev, adc->n_tm_channels, + sizeof(*aux_device->tm_props), + GFP_KERNEL); + if (!aux_device->tm_props) + return -ENOMEM; + + aux_device->dev_data =3D &adc->dev_data; + + for (i =3D 0; i < adc->nchannels; i++) { + if (!adc->chan_props[i].adc_tm) + continue; + aux_device->tm_props[i_tm] =3D adc->chan_props[i].common_props; + i_tm++; + } + + device_set_of_node_from_dev(&aux_device->aux_dev.dev, adc->dev); + + aux_device->n_tm_channels =3D adc->n_tm_channels; + + ret =3D auxiliary_device_init(&aux_device->aux_dev); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(adc->dev, adc5_gen3_uninit_aux, + &aux_device->aux_dev); + if (ret) + return ret; + + ret =3D auxiliary_device_add(&aux_device->aux_dev); + if (ret) + return ret; + ret =3D devm_add_action_or_reset(adc->dev, adc5_gen3_delete_aux, + &aux_device->aux_dev); + if (ret) + return ret; + + adc->tm_aux =3D &aux_device->aux_dev; + + return 0; +} + +void adc5_gen3_mutex_lock(struct device *dev) + __acquires(&adc->lock) +{ + struct iio_dev *indio_dev =3D dev_get_drvdata(dev->parent); + struct adc5_chip *adc =3D iio_priv(indio_dev); + + mutex_lock(&adc->lock); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_mutex_lock, "QCOM_SPMI_ADC5_GEN3"); + +void adc5_gen3_mutex_unlock(struct device *dev) + __releases(&adc->lock) +{ + struct iio_dev *indio_dev =3D dev_get_drvdata(dev->parent); + struct adc5_chip *adc =3D iio_priv(indio_dev); + + mutex_unlock(&adc->lock); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_mutex_unlock, "QCOM_SPMI_ADC5_GEN3"); + +int adc5_gen3_get_scaled_reading(struct device *dev, + struct adc5_channel_common_prop *common_props, + int *val) +{ + struct iio_dev *indio_dev =3D dev_get_drvdata(dev->parent); + struct adc5_chip *adc =3D iio_priv(indio_dev); + u16 adc_code_volt; + int ret; + + ret =3D adc5_gen3_do_conversion(adc, common_props, &adc_code_volt); + if (ret) + return ret; + + return qcom_adc5_hw_scale(common_props->scale_fn_type, + common_props->prescale, + adc->data, adc_code_volt, val); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_get_scaled_reading, "QCOM_SPMI_ADC5_GEN3"); + +int adc5_gen3_therm_code_to_temp(struct device *dev, + struct adc5_channel_common_prop *common_props, + u16 code, int *val) +{ + struct iio_dev *indio_dev =3D dev_get_drvdata(dev->parent); + struct adc5_chip *adc =3D iio_priv(indio_dev); + + return qcom_adc5_hw_scale(common_props->scale_fn_type, + common_props->prescale, + adc->data, code, val); +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_therm_code_to_temp, "QCOM_SPMI_ADC5_GEN3"); + +void adc5_gen3_register_tm_event_notifier(struct device *dev, + void (*handler)(struct auxiliary_device *)) +{ + struct iio_dev *indio_dev =3D dev_get_drvdata(dev->parent); + struct adc5_chip *adc =3D iio_priv(indio_dev); + + adc->handler =3D handler; +} +EXPORT_SYMBOL_NS_GPL(adc5_gen3_register_tm_event_notifier, "QCOM_SPMI_ADC5= _GEN3"); + +static int adc5_gen3_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct iio_dev *indio_dev; + struct adc5_chip *adc; + struct regmap *regmap; + int ret, i; + u32 *reg; + + regmap =3D dev_get_regmap(dev->parent, NULL); + if (!regmap) + return -ENODEV; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*adc)); + if (!indio_dev) + return -ENOMEM; + + adc =3D iio_priv(indio_dev); + adc->dev_data.regmap =3D regmap; + adc->dev =3D dev; + + ret =3D device_property_count_u32(dev, "reg"); + if (ret < 0) + return ret; + + adc->dev_data.num_sdams =3D ret; + + reg =3D devm_kcalloc(dev, adc->dev_data.num_sdams, sizeof(u32), + GFP_KERNEL); + if (!reg) + return -ENOMEM; + + ret =3D device_property_read_u32_array(dev, "reg", reg, + adc->dev_data.num_sdams); + if (ret) + return dev_err_probe(dev, ret, + "Failed to read reg property\n"); + + adc->dev_data.base =3D devm_kcalloc(dev, adc->dev_data.num_sdams, + sizeof(*adc->dev_data.base), + GFP_KERNEL); + if (!adc->dev_data.base) + return -ENOMEM; + + platform_set_drvdata(pdev, indio_dev); + init_completion(&adc->complete); + ret =3D devm_mutex_init(dev, &adc->lock); + if (ret) + return ret; + + for (i =3D 0; i < adc->dev_data.num_sdams; i++) { + adc->dev_data.base[i].base_addr =3D reg[i]; + + ret =3D platform_get_irq(pdev, i); + if (ret < 0) + return dev_err_probe(dev, ret, + "Getting IRQ %d failed\n", i); + + adc->dev_data.base[i].irq =3D ret; + + adc->dev_data.base[i].irq_name =3D devm_kasprintf(dev, GFP_KERNEL, + "sdam%d", i); + if (!adc->dev_data.base[i].irq_name) + return -ENOMEM; + } + + ret =3D devm_request_irq(dev, adc->dev_data.base[ADC5_GEN3_VADC_SDAM].irq, + adc5_gen3_isr, 0, + adc->dev_data.base[ADC5_GEN3_VADC_SDAM].irq_name, + adc); + if (ret) + return dev_err_probe(dev, ret, + "Failed to request SDAM%d irq\n", + ADC5_GEN3_VADC_SDAM); + + ret =3D adc5_get_fw_data(adc); + if (ret) + return ret; + + if (adc->n_tm_channels > 0) { + ret =3D adc5_gen3_add_aux_tm_device(adc); + if (ret) + dev_err_probe(dev, ret, + "Failed to add auxiliary TM device\n"); + } + + indio_dev->name =3D "spmi-adc5-gen3"; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->info =3D &adc5_gen3_info; + indio_dev->channels =3D adc->iio_chans; + indio_dev->num_channels =3D adc->nchannels; + + return devm_iio_device_register(dev, indio_dev); +} + +static struct platform_driver adc5_gen3_driver =3D { + .driver =3D { + .name =3D "qcom-spmi-adc5-gen3", + .of_match_table =3D adc5_match_table, + }, + .probe =3D adc5_gen3_probe, +}; +module_platform_driver(adc5_gen3_driver); + +MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 Gen3 ADC driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("QCOM_SPMI_ADC5_GEN3"); diff --git a/include/linux/iio/adc/qcom-adc5-gen3-common.h b/include/linux/= iio/adc/qcom-adc5-gen3-common.h new file mode 100644 index 000000000000..89c552a77341 --- /dev/null +++ b/include/linux/iio/adc/qcom-adc5-gen3-common.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Code used in the main and auxiliary Qualcomm PMIC voltage ADCs + * of type ADC5 Gen3. + */ + +#ifndef QCOM_ADC5_GEN3_COMMON_H +#define QCOM_ADC5_GEN3_COMMON_H + +#include +#include +#include +#include +#include +#include +#include + +#define ADC5_GEN3_HS 0x45 +#define ADC5_GEN3_HS_BUSY BIT(7) +#define ADC5_GEN3_HS_READY BIT(0) + +#define ADC5_GEN3_STATUS1 0x46 +#define ADC5_GEN3_STATUS1_CONV_FAULT BIT(7) +#define ADC5_GEN3_STATUS1_THR_CROSS BIT(6) +#define ADC5_GEN3_STATUS1_EOC BIT(0) + +#define ADC5_GEN3_TM_EN_STS 0x47 +#define ADC5_GEN3_TM_HIGH_STS 0x48 +#define ADC5_GEN3_TM_LOW_STS 0x49 + +#define ADC5_GEN3_EOC_STS 0x4a +#define ADC5_GEN3_EOC_CHAN_0 BIT(0) + +#define ADC5_GEN3_EOC_CLR 0x4b +#define ADC5_GEN3_TM_HIGH_STS_CLR 0x4c +#define ADC5_GEN3_TM_LOW_STS_CLR 0x4d +#define ADC5_GEN3_CONV_ERR_CLR 0x4e +#define ADC5_GEN3_CONV_ERR_CLR_REQ BIT(0) + +#define ADC5_GEN3_SID 0x4f +#define ADC5_GEN3_SID_MASK GENMASK(3, 0) + +#define ADC5_GEN3_PERPH_CH 0x50 +#define ADC5_GEN3_CHAN_CONV_REQ BIT(7) + +#define ADC5_GEN3_TIMER_SEL 0x51 +#define ADC5_GEN3_TIME_IMMEDIATE 0x1 + +#define ADC5_GEN3_DIG_PARAM 0x52 +#define ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK GENMASK(5, 4) +#define ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK GENMASK(3, 2) + +#define ADC5_GEN3_FAST_AVG 0x53 +#define ADC5_GEN3_FAST_AVG_CTL_EN BIT(7) +#define ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK GENMASK(2, 0) + +#define ADC5_GEN3_ADC_CH_SEL_CTL 0x54 +#define ADC5_GEN3_DELAY_CTL 0x55 +#define ADC5_GEN3_HW_SETTLE_DELAY_MASK GENMASK(3, 0) + +#define ADC5_GEN3_CH_EN 0x56 +#define ADC5_GEN3_HIGH_THR_INT_EN BIT(1) +#define ADC5_GEN3_LOW_THR_INT_EN BIT(0) + +#define ADC5_GEN3_LOW_THR0 0x57 +#define ADC5_GEN3_LOW_THR1 0x58 +#define ADC5_GEN3_HIGH_THR0 0x59 +#define ADC5_GEN3_HIGH_THR1 0x5a + +#define ADC5_GEN3_CH_DATA0(channel) (0x5c + (channel) * 2) +#define ADC5_GEN3_CH_DATA1(channel) (0x5d + (channel) * 2) + +#define ADC5_GEN3_CONV_REQ 0xe5 +#define ADC5_GEN3_CONV_REQ_REQ BIT(0) + +#define ADC5_GEN3_VIRTUAL_SID_MASK GENMASK(15, 8) +#define ADC5_GEN3_CHANNEL_MASK GENMASK(7, 0) +#define ADC5_GEN3_V_CHAN(x) \ + (FIELD_PREP(ADC5_GEN3_VIRTUAL_SID_MASK, (x).sid) | (x).channel) + +/* ADC channels for PMIC5 Gen3 */ +#define ADC5_GEN3_REF_GND 0x00 +#define ADC5_GEN3_1P25VREF 0x01 +#define ADC5_GEN3_DIE_TEMP 0x03 +#define ADC5_GEN3_USB_SNS_V_16 0x11 +#define ADC5_GEN3_VIN_DIV16_MUX 0x12 +#define ADC5_GEN3_VPH_PWR 0x8e +#define ADC5_GEN3_VBAT_SNS_QBG 0x8f +/* 100k pull-up channels */ +#define ADC5_GEN3_AMUX1_THM_100K_PU 0x44 +#define ADC5_GEN3_AMUX2_THM_100K_PU 0x45 +#define ADC5_GEN3_AMUX3_THM_100K_PU 0x46 +#define ADC5_GEN3_AMUX4_THM_100K_PU 0x47 +#define ADC5_GEN3_AMUX5_THM_100K_PU 0x48 +#define ADC5_GEN3_AMUX6_THM_100K_PU 0x49 +#define ADC5_GEN3_AMUX1_GPIO_100K_PU 0x4a +#define ADC5_GEN3_AMUX2_GPIO_100K_PU 0x4b +#define ADC5_GEN3_AMUX3_GPIO_100K_PU 0x4c +#define ADC5_GEN3_AMUX4_GPIO_100K_PU 0x4d + +#define ADC5_MAX_CHANNEL 0xc0 + +enum adc5_cal_method { + ADC5_NO_CAL =3D 0, + ADC5_RATIOMETRIC_CAL, + ADC5_ABSOLUTE_CAL, +}; + +enum adc5_time_select { + MEAS_INT_DISABLE =3D 0, + MEAS_INT_IMMEDIATE, + MEAS_INT_50MS, + MEAS_INT_100MS, + MEAS_INT_1S, + MEAS_INT_NONE, +}; + +/** + * struct adc5_sdam_data - data per SDAM allocated for adc usage + * @base_addr: base address for the ADC SDAM peripheral. + * @irq_name: ADC IRQ name. + * @irq: ADC IRQ number. + */ +struct adc5_sdam_data { + u16 base_addr; + const char *irq_name; + int irq; +}; + +/** + * struct adc5_device_data - Top-level ADC device data + * @regmap: ADC peripheral register map field. + * @base: array of SDAM data. + * @num_sdams: number of ADC SDAM peripherals. + */ +struct adc5_device_data { + struct regmap *regmap; + struct adc5_sdam_data *base; + int num_sdams; +}; + +/** + * struct adc5_channel_common_prop - ADC channel properties (common to ADC= and TM). + * @channel: channel number, refer to the channel list. + * @cal_method: calibration method. + * @decimation: sampling rate supported for the channel. + * @sid: ID of PMIC owning the channel. + * @label: Channel name used in device tree. + * @prescale: channel scaling performed on the input signal. + * @hw_settle_time_us: the time between AMUX being configured and the + * start of conversion in uS. + * @avg_samples: ability to provide single result from the ADC + * that is an average of multiple measurements. + * @scale_fn_type: Represents the scaling function to convert voltage + * physical units desired by the client for the channel. + */ +struct adc5_channel_common_prop { + unsigned int channel; + enum adc5_cal_method cal_method; + unsigned int decimation; + unsigned int sid; + const char *label; + unsigned int prescale; + unsigned int hw_settle_time_us; + unsigned int avg_samples; + enum vadc_scale_fn_type scale_fn_type; +}; + +/** + * struct tm5_aux_dev_wrapper - wrapper structure around TM auxiliary devi= ce + * @aux_dev: TM auxiliary device structure. + * @dev_data: Top-level ADC device data. + * @tm_props: Array of common ADC channel properties for TM channels. + * @n_tm_channels: number of TM channels. + */ +struct tm5_aux_dev_wrapper { + struct auxiliary_device aux_dev; + struct adc5_device_data *dev_data; + struct adc5_channel_common_prop *tm_props; + unsigned int n_tm_channels; +}; + +int adc5_gen3_read(struct adc5_device_data *adc, unsigned int sdam_index, + u16 offset, u8 *data, int len); + +int adc5_gen3_write(struct adc5_device_data *adc, unsigned int sdam_index, + u16 offset, u8 *data, int len); + +int adc5_gen3_poll_wait_hs(struct adc5_device_data *adc, + unsigned int sdam_index); + +void adc5_gen3_update_dig_param(struct adc5_channel_common_prop *prop, + u8 *data); + +int adc5_gen3_status_clear(struct adc5_device_data *adc, + int sdam_index, u16 offset, u8 *val, int len); + +void adc5_gen3_mutex_lock(struct device *dev); +void adc5_gen3_mutex_unlock(struct device *dev); +int adc5_gen3_get_scaled_reading(struct device *dev, + struct adc5_channel_common_prop *common_props, + int *val); +int adc5_gen3_therm_code_to_temp(struct device *dev, + struct adc5_channel_common_prop *common_props, + u16 code, int *val); +void adc5_gen3_register_tm_event_notifier(struct device *dev, + void (*handler)(struct auxiliary_device *)); + +#endif /* QCOM_ADC5_GEN3_COMMON_H */ --=20 2.25.1 From nobody Sat Feb 7 05:49:39 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EE01344DAA for ; Wed, 28 Jan 2026 11:25:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769599514; cv=none; b=cdixxAyX8MNilOLylkJZm+vlielqIcikr43sxqu2Hm00O1/jhX+roNBil3AkMuA6jj2yxacCLRmSlPpwg4MDpXgWjsE/rvUOn9NWmJq8wvmxuS8TdfZ7TZw6aWckdEcC/l7OMI0gfM7WbeYGFYirIpo+dHxZ8wfwKbrW4uPVjS8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769599514; c=relaxed/simple; bh=YOyMUcSsoOnMFFZkmId+XY6USdOgi/AIyjcronYhjAA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kAf/H+o6WcBKSUprVUmu/rGfCsX2gYo8tApjF5PP7vB9hFZtAguBQOao5KDlE89lg3d59e6eqMWWwJkYL4pST1NC2IpSrRimZyqHNHOxkIHLrHbG8gla091FT9K46MXwAKlt/WAX9Yk8kW88tJJ6Unh6wO0MRNRrLeT4w/lGSKw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Sswz/VM/; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=GNcdSG54; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Sswz/VM/"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="GNcdSG54" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60S91pUB3442357 for ; Wed, 28 Jan 2026 11:25:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=J6p1ok0DhZB sttXfqglVymlRJfi6l/6YHmiMOfWpk9E=; b=Sswz/VM/W2g6KhFkG32y3WOTV5y WO+lccGnsHstw+IaG5EZnoH+BvnFX5VA0GRVJfDn1F4iDVpGdOgprUlcs1oql2TH wzhXaNqFsicm8T4mKCrgfoK2E6HzTEEooSeFi6tXImHdGcZVxx3rq9AZcp6Pafqo ti3TRSEIrVYNhNyGTyNJvZ5cs8PlcbLvTChoJV0sIMEGH+t9T3/n9NCb0eL6nA/+ R2/21Ueqc9h1+Sy5b8EY2m15JqgXp86Ruav4yUbkfMe35vBXx7I0DoP61sVMcr1I OrH0fRswKVxNQh0nCU0R1Lc/yPGS6qSxriCDnR+RUPPl1vuFCV4Y4jyH+nw== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4byanaheph-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 28 Jan 2026 11:25:10 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-29f2b45ecffso106196285ad.2 for ; Wed, 28 Jan 2026 03:25:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1769599510; x=1770204310; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J6p1ok0DhZBsttXfqglVymlRJfi6l/6YHmiMOfWpk9E=; b=GNcdSG54Y4btTPUNYRT0XQvbcGjC70O5kRX+vJpRK4LO5v46WQqjHtSCn2Ft6kg0kP aumq8QAEX1CI67gOYnuDg9jr4Fn6ie2DHPZC4pTLMVOtN7ZCEgyjQ1veVl//wFqhm1HJ Q91YzKOIfOJycggrcfHu3eBRv/i69Z6avE2XCWdzFS5ScPTCmf5f7icr1YYAx9U+LP3T WjBZIoOz4n8MCApurfKNN7K4/OjEiBgo3bHpTFvpGmywgFFYR3tkIP/lT8IYxj1ptg3K 1bXqwnO8Vca6EkpNpvVXxYOx35dn6+8lg3J2llgaYjr9hV40IpmPtDOp7+JilsRmF4FC cXTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769599510; x=1770204310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=J6p1ok0DhZBsttXfqglVymlRJfi6l/6YHmiMOfWpk9E=; b=cCHiVFKV/2XcpMI7w0TzcQscyVzOvYPLWQBhG3x0zqblutL14tpoTtJJw9MyURQAqS 69MdAGNPvuILpXlEAV1+1PpqEEAqZdC3dsjcHOoClHPyIE0oft2CEp9kpdkTARfsEnaK OruIaQaF+JP3Ao2xbPtXMebfGCypsYg2u2eUgPh9KIiIRzBAaUvJZv2pkZ50Vg18LkFe L5v1bZ4b052Gf6825siCMZE34rhPp+PpeQTRfl8xOE9+WUFTa5R0Ggd1CmiaVRUGyooK rHpXMyiEqzvPvLDFliKxFlQgigOoYnYJ5TmRP532R0JmQce4o9qyml1GQpUNM1i1oYJe PfpQ== X-Forwarded-Encrypted: i=1; AJvYcCUA8lVSQ3f3LsUsb/3jml7pGu8Tk/1yHa8JBAnyvzVEKgIitgzZtetsgX7WoJNz/4NACS2qyqHZ3LWir8s=@vger.kernel.org X-Gm-Message-State: AOJu0Yzo22HrOD8qcCNrjrFKEHxwt4VzERAuLsq2yK2MptvmyB3AFwp/ EgrqGEi3HKACa6WuX5r7FPshS8KoiVbwEckAWOxGwJtqIogti7KHz+r69dimGmMQv7FxIP6G5Ks aeoI/SkVh0lsKNw55nwy9nJpGxP++lCc6S3n6PiAjTGAjh475XPCpfo/ydrN1mUh63QM= X-Gm-Gg: AZuq6aJ0cPRbKvDFjaU0a7yhWecQ9vqlMJmBI0ZzoGrXVR60udeCRWT9k2XvGZ3ZfdN pxk+ol1kB21Y5KykLdsbYLi77FtuCPfH0yRBK5E6JLBKjYb0jQezSCP1hd0ClrUnwBX5yigLdKt 7s/DD8bXeeLMccAm2ZpOe/g1jT2jFHzJtIkCErQpK3Sivw7BYgQWjLp2aUxwGK7M7AcBdPDRRxR +C/w/XcjSgfCFH4sX4LQfS4QCgvQFOHKTMk5voMZ5nTQA61Jf8qFhsCf3w5AFctqNMoWhiy91pl x8ptLOtUZWQYBzOuEWX76ZbqOIWRfTaSKNmADDGqg57/AMaPQ0XahmVRCzdv+BDGyTev1FEVbDc zQh8Te8bpTqs1CAUZW1dK9UQQg/iYBOZ3L8J/0hi+ZNig X-Received: by 2002:a17:902:e807:b0:2a0:b44e:9ab6 with SMTP id d9443c01a7336-2a870d330a9mr52359265ad.7.1769599509716; Wed, 28 Jan 2026 03:25:09 -0800 (PST) X-Received: by 2002:a17:902:e807:b0:2a0:b44e:9ab6 with SMTP id d9443c01a7336-2a870d330a9mr52358785ad.7.1769599509091; Wed, 28 Jan 2026 03:25:09 -0800 (PST) Received: from hu-jprakash-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a88b4c40a8sm21984605ad.51.2026.01.28.03.25.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 03:25:08 -0800 (PST) From: Jishnu Prakash To: jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org, daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org, subbaraman.narayanamurthy@oss.qualcomm.com, david.collins@oss.qualcomm.com, anjelique.melendez@oss.qualcomm.com, kamal.wadhwa@oss.qualcomm.com Cc: rui.zhang@intel.com, lukasz.luba@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, jishnu.prakash@oss.qualcomm.com, quic_kotarake@quicinc.com, neil.armstrong@linaro.org, stephan.gerhold@linaro.org Subject: [PATCH V9 4/4] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring Date: Wed, 28 Jan 2026 16:54:20 +0530 Message-Id: <20260128112420.695518-5-jishnu.prakash@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260128112420.695518-1-jishnu.prakash@oss.qualcomm.com> References: <20260128112420.695518-1-jishnu.prakash@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: QlIOD-DrJL4wvhjFlLsfoY3nJa5UD_Uq X-Proofpoint-ORIG-GUID: QlIOD-DrJL4wvhjFlLsfoY3nJa5UD_Uq X-Authority-Analysis: v=2.4 cv=N58k1m9B c=1 sm=1 tr=0 ts=6979f217 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=hpoCfrBzasziBmgo1UAA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI4MDA5MyBTYWx0ZWRfX6kPMk2eDEAhM o6fblQvnY/2zxD/dMFb1N7QBtCe9XtpHKkBDyV14u1TUArjBzGcies+UICmU0YhJD8kToRzxsIK 4t2Zby5NW2+Pq5re+5+LydoGHaOjUyH6XZznmiqZSN72HNeMuXs0TwsR9/++iB048Xhn0Ou3jjs 88yUn0vy/SwTTJ4iSKBtldDZ89xmeKRsQMAuX01SkCY1+9nNRZON+boC124L1MLO9RqaJ0lerE0 RnFLcNzk7bFM6vcRLYZS4EwT5opiQ5eVUtBOWJ1/sP1lQeMQQCM8YXRcmLZqcVltUK63kSE1kIW K6HDjovyPNuo4oN0fwCT689cuxPZmUc5+f9POA1sJ/9w6Rd4h/3dVRdLiPOONV9YhJ2qLcdmA6s i+hWe4p5rREjSiuruiaBANO3bKia35MMiKAJPROq7BbYWLHvrl+FX0xje4awj/u3rEL+tzUa2WR svBqzOy8STKjaWyD4Dg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-28_02,2026-01-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 adultscore=0 clxscore=1015 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601280093 Content-Type: text/plain; charset="utf-8" Add support for ADC_TM part of PMIC5 Gen3. This is an auxiliary driver under the Gen3 ADC driver, which implements the threshold setting and interrupt generating functionalities of QCOM ADC_TM drivers, used to support thermal trip points. Signed-off-by: Jishnu Prakash --- Changes since v8: - Made following changes to address Dmitry's comment to use module_auxiliar= y_driver(): - Dropped the wrapper struct containing the auxiliary driver (struct adc_= tm5_auxiliary_drv) which was originally meant to expose the TM interrupt callback to be ca= lled by main driver and replaced it with standalone definition of the auxiliary= _driver struct. - Added call to adc5_gen3_register_tm_event_notifier() in probe to initia= lize the TM callback for main driver. - Replaced the module_init() and module_exit() calls with module_auxiliar= y_driver(). - Made following changes to address Jonathan's comments: - Updated header files included in drivers/thermal/qcom/qcom-spmi-adc-tm5= -gen3.c to follow IWYU (include-what-you-use) principles. - Added a DEFINE_GUARD() definition for mutex lock/unlock functions and r= eplaced their existing calls with guard() and scoped_guard() statements using t= his definition. - Moved some variable declarations in tm_handler_work() to inside the for= () loop. - Fixed if() check condition for low_temp in adc_tm5_gen3_set_trip_temp(). - Dropped the wrapper function adc_tm5_gen3_disable_channel() around _adc_tm5_gen3_disable_channel() as it only calls the inner function with = no other actions. - Replaced a pr_debug() call with dev_dbg() in tm_handler_work(). Changes since v7: - Addressed following comments from Jonathan: - Replaced {0} with { } in tm_handler_work() - Simplified logic for setting upper_set and lower_set into a single line each, in tm_handler_work() - Cleaned up local variable declarations and high/low threshold check in adc_tm5_gen3_configure() - Moved cleanup action to disable all ADC_TM channels to probe end and added comment to describe it. - Fixed { } formatting in adctm5_auxiliary_id_table[]. Changes since v6: - Addressed following comments from Jonathan: - Added error check for devm_thermal_add_hwmon_sysfs() call. - Used local variable `dev` in multiple places in adc_tm5_probe(). in place of `&aux_dev->dev` and `adc_tm5->dev`. - Added a comment to explain cleanup action calling adc5_gen3_clear_work() near probe end. - Fixed return statement at probe end to return last called API's return value directly. Changes since v5: - Addressed following comments from Jonathan: - Corrected all files to follow kernel-doc formatting fully. - Cleaned up formatting in struct definitions. - Used sizeof() to specify length in register read/write calls instead of using integers directly. - Added comments in adc_tm5_probe() for skipping first SDAM for IRQ request and for usage of auxiliary_set_drvdata(). - Corrected line wrap length driver file. - Moved INIT_WORK() and auxiliary_set_drvdata() to earlier locations to ensure they are ready when needed. Changes since v4: - Fixed a compilation error and updated dependencies in config as suggested by Krzysztof. drivers/thermal/qcom/Kconfig | 9 + drivers/thermal/qcom/Makefile | 1 + drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c | 512 ++++++++++++++++++ 3 files changed, 522 insertions(+) create mode 100644 drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c diff --git a/drivers/thermal/qcom/Kconfig b/drivers/thermal/qcom/Kconfig index a6bb01082ec6..1acb11e4ac80 100644 --- a/drivers/thermal/qcom/Kconfig +++ b/drivers/thermal/qcom/Kconfig @@ -21,6 +21,15 @@ config QCOM_SPMI_ADC_TM5 Thermal client sets threshold temperature for both warm and cool and gets updated when a threshold is reached. =20 +config QCOM_SPMI_ADC_TM5_GEN3 + tristate "Qualcomm SPMI PMIC Thermal Monitor ADC5 Gen3" + depends on QCOM_SPMI_ADC5_GEN3 + help + This enables the auxiliary thermal driver for the ADC5 Gen3 thermal + monitoring device. It shows up as a thermal zone with multiple trip poi= nts. + Thermal client sets threshold temperature for both warm and cool and + gets updated when a threshold is reached. + config QCOM_SPMI_TEMP_ALARM tristate "Qualcomm SPMI PMIC Temperature Alarm" depends on OF && SPMI && IIO diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index 0fa2512042e7..828d9e7bc797 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -4,5 +4,6 @@ obj-$(CONFIG_QCOM_TSENS) +=3D qcom_tsens.o qcom_tsens-y +=3D tsens.o tsens-v2.o tsens-v1.o tsens-v0_1.o \ tsens-8960.o obj-$(CONFIG_QCOM_SPMI_ADC_TM5) +=3D qcom-spmi-adc-tm5.o +obj-$(CONFIG_QCOM_SPMI_ADC_TM5_GEN3) +=3D qcom-spmi-adc-tm5-gen3.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) +=3D qcom-spmi-temp-alarm.o obj-$(CONFIG_QCOM_LMH) +=3D lmh.o diff --git a/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c b/drivers/therma= l/qcom/qcom-spmi-adc-tm5-gen3.c new file mode 100644 index 000000000000..b72fd7ee36c0 --- /dev/null +++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c @@ -0,0 +1,512 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../thermal_hwmon.h" + +struct adc_tm5_gen3_chip; + +/** + * struct adc_tm5_gen3_channel_props - ADC_TM channel structure + * @timer: time period of recurring TM measurement. + * @tm_chan_index: TM channel number used (ranging from 1-7). + * @sdam_index: SDAM on which this TM channel lies. + * @common_props: structure with common ADC channel properties. + * @high_thr_en: TM high threshold crossing detection enabled. + * @low_thr_en: TM low threshold crossing detection enabled. + * @chip: ADC TM device. + * @tzd: pointer to thermal device corresponding to TM channel. + * @last_temp: last temperature that caused threshold violation, + * or a thermal TM channel. + * @last_temp_set: indicates if last_temp is stored. + */ +struct adc_tm5_gen3_channel_props { + unsigned int timer; + unsigned int tm_chan_index; + unsigned int sdam_index; + struct adc5_channel_common_prop common_props; + bool high_thr_en; + bool low_thr_en; + struct adc_tm5_gen3_chip *chip; + struct thermal_zone_device *tzd; + int last_temp; + bool last_temp_set; +}; + +/** + * struct adc_tm5_gen3_chip - ADC Thermal Monitoring device structure + * @dev_data: Top-level ADC device data. + * @chan_props: Array of ADC_TM channel structures. + * @nchannels: number of TM channels allocated + * @dev: SPMI ADC5 Gen3 device. + * @tm_handler_work: handler for TM interrupt for threshold violation. + */ +struct adc_tm5_gen3_chip { + struct adc5_device_data *dev_data; + struct adc_tm5_gen3_channel_props *chan_props; + unsigned int nchannels; + struct device *dev; + struct work_struct tm_handler_work; +}; + +DEFINE_GUARD(adc5_gen3, struct adc_tm5_gen3_chip *, adc5_gen3_mutex_lock(_= T->dev), + adc5_gen3_mutex_unlock(_T->dev)) + +static int get_sdam_from_irq(struct adc_tm5_gen3_chip *adc_tm5, int irq) +{ + int i; + + for (i =3D 0; i < adc_tm5->dev_data->num_sdams; i++) { + if (adc_tm5->dev_data->base[i].irq =3D=3D irq) + return i; + } + return -ENOENT; +} + +static irqreturn_t adctm5_gen3_isr(int irq, void *dev_id) +{ + struct adc_tm5_gen3_chip *adc_tm5 =3D dev_id; + int ret, sdam_num; + u8 tm_status[2]; + u8 status, val; + + sdam_num =3D get_sdam_from_irq(adc_tm5, irq); + if (sdam_num < 0) { + dev_err(adc_tm5->dev, "adc irq %d not associated with an sdam\n", + irq); + return IRQ_HANDLED; + } + + ret =3D adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_STATUS1, + &status, sizeof(status)); + if (ret) { + dev_err(adc_tm5->dev, "adc read status1 failed with %d\n", ret); + return IRQ_HANDLED; + } + + if (status & ADC5_GEN3_STATUS1_CONV_FAULT) { + dev_err_ratelimited(adc_tm5->dev, + "Unexpected conversion fault, status:%#x\n", + status); + val =3D ADC5_GEN3_CONV_ERR_CLR_REQ; + adc5_gen3_status_clear(adc_tm5->dev_data, sdam_num, + ADC5_GEN3_CONV_ERR_CLR, &val, 1); + return IRQ_HANDLED; + } + + ret =3D adc5_gen3_read(adc_tm5->dev_data, sdam_num, ADC5_GEN3_TM_HIGH_STS, + tm_status, sizeof(tm_status)); + if (ret) { + dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret); + return IRQ_HANDLED; + } + + if (tm_status[0] || tm_status[1]) + schedule_work(&adc_tm5->tm_handler_work); + + dev_dbg(adc_tm5->dev, "Interrupt status:%#x, high:%#x, low:%#x\n", + status, tm_status[0], tm_status[1]); + + return IRQ_HANDLED; +} + +static int adc5_gen3_tm_status_check(struct adc_tm5_gen3_chip *adc_tm5, + int sdam_index, u8 *tm_status, u8 *buf) +{ + int ret; + + ret =3D adc5_gen3_read(adc_tm5->dev_data, sdam_index, ADC5_GEN3_TM_HIGH_S= TS, + tm_status, 2); + if (ret) { + dev_err(adc_tm5->dev, "adc read TM status failed with %d\n", ret); + return ret; + } + + ret =3D adc5_gen3_status_clear(adc_tm5->dev_data, sdam_index, ADC5_GEN3_T= M_HIGH_STS_CLR, + tm_status, 2); + if (ret) { + dev_err(adc_tm5->dev, "adc status clear conv_req failed with %d\n", + ret); + return ret; + } + + ret =3D adc5_gen3_read(adc_tm5->dev_data, sdam_index, ADC5_GEN3_CH_DATA0(= 0), + buf, 16); + if (ret) + dev_err(adc_tm5->dev, "adc read data failed with %d\n", ret); + + return ret; +} + +static void tm_handler_work(struct work_struct *work) +{ + struct adc_tm5_gen3_chip *adc_tm5 =3D container_of(work, struct adc_tm5_g= en3_chip, + tm_handler_work); + int sdam_index =3D -1; + u8 tm_status[2] =3D { }; + u8 buf[16] =3D { }; + + for (int i =3D 0; i < adc_tm5->nchannels; i++) { + struct adc_tm5_gen3_channel_props *chan_prop =3D &adc_tm5->chan_props[i]; + int offset =3D chan_prop->tm_chan_index; + bool upper_set, lower_set; + int ret, temp; + u16 code; + + scoped_guard(adc5_gen3, adc_tm5) { + if (chan_prop->sdam_index !=3D sdam_index) { + sdam_index =3D chan_prop->sdam_index; + ret =3D adc5_gen3_tm_status_check(adc_tm5, sdam_index, + tm_status, buf); + if (ret) + break; + } + + upper_set =3D ((tm_status[0] & BIT(offset)) && chan_prop->high_thr_en); + lower_set =3D ((tm_status[1] & BIT(offset)) && chan_prop->low_thr_en); + } + + if (!(upper_set || lower_set)) + continue; + + code =3D get_unaligned_le16(&buf[2 * offset]); + dev_dbg(adc_tm5->dev, "ADC_TM threshold code:%#x\n", code); + + ret =3D adc5_gen3_therm_code_to_temp(adc_tm5->dev, + &chan_prop->common_props, + code, &temp); + if (ret) { + dev_err(adc_tm5->dev, + "Invalid temperature reading, ret =3D %d, code=3D%#x\n", + ret, code); + continue; + } + + chan_prop->last_temp =3D temp; + chan_prop->last_temp_set =3D true; + thermal_zone_device_update(chan_prop->tzd, THERMAL_TRIP_VIOLATED); + } +} + +static int adc_tm5_gen3_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct adc_tm5_gen3_channel_props *prop =3D thermal_zone_device_priv(tz); + struct adc_tm5_gen3_chip *adc_tm5; + + if (!prop || !prop->chip) + return -EINVAL; + + adc_tm5 =3D prop->chip; + + if (prop->last_temp_set) { + pr_debug("last_temp: %d\n", prop->last_temp); + prop->last_temp_set =3D false; + *temp =3D prop->last_temp; + return 0; + } + + return adc5_gen3_get_scaled_reading(adc_tm5->dev, &prop->common_props, + temp); +} + +static int adc_tm5_gen3_disable_channel(struct adc_tm5_gen3_channel_props = *prop) +{ + struct adc_tm5_gen3_chip *adc_tm5 =3D prop->chip; + int ret; + u8 val; + + prop->high_thr_en =3D false; + prop->low_thr_en =3D false; + + ret =3D adc5_gen3_poll_wait_hs(adc_tm5->dev_data, prop->sdam_index); + if (ret) + return ret; + + val =3D BIT(prop->tm_chan_index); + ret =3D adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_TM_HIGH_STS_CLR, &val, sizeof(val)); + if (ret) + return ret; + + val =3D MEAS_INT_DISABLE; + ret =3D adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_TIMER_SEL, &val, sizeof(val)); + if (ret) + return ret; + + /* To indicate there is an actual conversion request */ + val =3D ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index; + ret =3D adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_PERPH_CH, &val, sizeof(val)); + if (ret) + return ret; + + val =3D ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_CONV_REQ, &val, sizeof(val)); +} + +#define ADC_TM5_GEN3_CONFIG_REGS 12 + +static int adc_tm5_gen3_configure(struct adc_tm5_gen3_channel_props *prop, + int low_temp, int high_temp) +{ + struct adc_tm5_gen3_chip *adc_tm5 =3D prop->chip; + u8 buf[ADC_TM5_GEN3_CONFIG_REGS]; + u8 conv_req; + u16 adc_code; + int ret; + + ret =3D adc5_gen3_poll_wait_hs(adc_tm5->dev_data, prop->sdam_index); + if (ret < 0) + return ret; + + ret =3D adc5_gen3_read(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_SID, buf, sizeof(buf)); + if (ret < 0) + return ret; + + /* Write SID */ + buf[0] =3D FIELD_PREP(ADC5_GEN3_SID_MASK, prop->common_props.sid); + + /* Select TM channel and indicate there is an actual conversion request */ + buf[1] =3D ADC5_GEN3_CHAN_CONV_REQ | prop->tm_chan_index; + + buf[2] =3D prop->timer; + + /* Digital param selection */ + adc5_gen3_update_dig_param(&prop->common_props, &buf[3]); + + /* Update fast average sample value */ + buf[4] &=3D ~ADC5_GEN3_FAST_AVG_CTL_SAMPLES_MASK; + buf[4] |=3D prop->common_props.avg_samples | ADC5_GEN3_FAST_AVG_CTL_EN; + + /* Select ADC channel */ + buf[5] =3D prop->common_props.channel; + + /* Select HW settle delay for channel */ + buf[6] =3D FIELD_PREP(ADC5_GEN3_HW_SETTLE_DELAY_MASK, + prop->common_props.hw_settle_time_us); + + /* High temperature corresponds to low voltage threshold */ + prop->low_thr_en =3D (high_temp !=3D INT_MAX); + if (prop->low_thr_en) { + adc_code =3D qcom_adc_tm5_gen2_temp_res_scale(high_temp); + put_unaligned_le16(adc_code, &buf[8]); + } + + /* Low temperature corresponds to high voltage threshold */ + prop->high_thr_en =3D (low_temp !=3D -INT_MAX); + if (prop->high_thr_en) { + adc_code =3D qcom_adc_tm5_gen2_temp_res_scale(low_temp); + put_unaligned_le16(adc_code, &buf[10]); + } + + buf[7] =3D 0; + if (prop->high_thr_en) + buf[7] |=3D ADC5_GEN3_HIGH_THR_INT_EN; + if (prop->low_thr_en) + buf[7] |=3D ADC5_GEN3_LOW_THR_INT_EN; + + ret =3D adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, ADC5_GEN3_SI= D, + buf, sizeof(buf)); + if (ret < 0) + return ret; + + conv_req =3D ADC5_GEN3_CONV_REQ_REQ; + return adc5_gen3_write(adc_tm5->dev_data, prop->sdam_index, + ADC5_GEN3_CONV_REQ, &conv_req, sizeof(conv_req)); +} + +static int adc_tm5_gen3_set_trip_temp(struct thermal_zone_device *tz, + int low_temp, int high_temp) +{ + struct adc_tm5_gen3_channel_props *prop =3D thermal_zone_device_priv(tz); + struct adc_tm5_gen3_chip *adc_tm5; + + if (!prop || !prop->chip) + return -EINVAL; + + adc_tm5 =3D prop->chip; + + dev_dbg(adc_tm5->dev, "channel:%s, low_temp(mdegC):%d, high_temp(mdegC):%= d\n", + prop->common_props.label, low_temp, high_temp); + + guard(adc5_gen3)(adc_tm5); + if (high_temp =3D=3D INT_MAX && low_temp =3D=3D -INT_MAX) + return adc_tm5_gen3_disable_channel(prop); + + return adc_tm5_gen3_configure(prop, low_temp, high_temp); +} + +static const struct thermal_zone_device_ops adc_tm_ops =3D { + .get_temp =3D adc_tm5_gen3_get_temp, + .set_trips =3D adc_tm5_gen3_set_trip_temp, +}; + +static int adc_tm5_register_tzd(struct adc_tm5_gen3_chip *adc_tm5) +{ + unsigned int i, channel; + struct thermal_zone_device *tzd; + int ret; + + for (i =3D 0; i < adc_tm5->nchannels; i++) { + channel =3D ADC5_GEN3_V_CHAN(adc_tm5->chan_props[i].common_props); + tzd =3D devm_thermal_of_zone_register(adc_tm5->dev, channel, + &adc_tm5->chan_props[i], + &adc_tm_ops); + + if (IS_ERR(tzd)) { + if (PTR_ERR(tzd) =3D=3D -ENODEV) { + dev_warn(adc_tm5->dev, + "thermal sensor on channel %d is not used\n", + channel); + continue; + } + return dev_err_probe(adc_tm5->dev, PTR_ERR(tzd), + "Error registering TZ zone:%ld for channel:%d\n", + PTR_ERR(tzd), channel); + } + adc_tm5->chan_props[i].tzd =3D tzd; + ret =3D devm_thermal_add_hwmon_sysfs(adc_tm5->dev, tzd); + if (ret) + return ret; + } + return 0; +} + +static void adc5_gen3_clear_work(void *data) +{ + struct adc_tm5_gen3_chip *adc_tm5 =3D data; + + cancel_work_sync(&adc_tm5->tm_handler_work); +} + +static void adc5_gen3_disable(void *data) +{ + struct adc_tm5_gen3_chip *adc_tm5 =3D data; + int i; + + guard(adc5_gen3)(adc_tm5); + /* Disable all available TM channels */ + for (i =3D 0; i < adc_tm5->nchannels; i++) + adc_tm5_gen3_disable_channel(&adc_tm5->chan_props[i]); +} + +static void adctm_event_handler(struct auxiliary_device *adev) +{ + struct adc_tm5_gen3_chip *adc_tm5 =3D auxiliary_get_drvdata(adev); + + schedule_work(&adc_tm5->tm_handler_work); +} + +static int adc_tm5_probe(struct auxiliary_device *aux_dev, + const struct auxiliary_device_id *id) +{ + struct adc_tm5_gen3_chip *adc_tm5; + struct tm5_aux_dev_wrapper *aux_dev_wrapper; + struct device *dev =3D &aux_dev->dev; + int i, ret; + + adc_tm5 =3D devm_kzalloc(dev, sizeof(*adc_tm5), GFP_KERNEL); + if (!adc_tm5) + return -ENOMEM; + + aux_dev_wrapper =3D container_of(aux_dev, struct tm5_aux_dev_wrapper, + aux_dev); + + adc_tm5->dev =3D dev; + adc_tm5->dev_data =3D aux_dev_wrapper->dev_data; + adc_tm5->nchannels =3D aux_dev_wrapper->n_tm_channels; + adc_tm5->chan_props =3D devm_kcalloc(dev, aux_dev_wrapper->n_tm_channels, + sizeof(*adc_tm5->chan_props), GFP_KERNEL); + if (!adc_tm5->chan_props) + return -ENOMEM; + + for (i =3D 0; i < adc_tm5->nchannels; i++) { + adc_tm5->chan_props[i].common_props =3D aux_dev_wrapper->tm_props[i]; + adc_tm5->chan_props[i].timer =3D MEAS_INT_1S; + adc_tm5->chan_props[i].sdam_index =3D (i + 1) / 8; + adc_tm5->chan_props[i].tm_chan_index =3D (i + 1) % 8; + adc_tm5->chan_props[i].chip =3D adc_tm5; + } + + INIT_WORK(&adc_tm5->tm_handler_work, tm_handler_work); + + /* + * Skipping first SDAM IRQ as it is requested in parent driver. + * If there is a TM violation on that IRQ, the parent driver calls + * the notifier (adctm_event_handler) exposed from this driver to handle = it. + */ + for (i =3D 1; i < adc_tm5->dev_data->num_sdams; i++) { + ret =3D devm_request_threaded_irq(dev, + adc_tm5->dev_data->base[i].irq, + NULL, adctm5_gen3_isr, IRQF_ONESHOT, + adc_tm5->dev_data->base[i].irq_name, + adc_tm5); + if (ret < 0) + return ret; + } + + /* + * This drvdata is only used in the function (adctm_event_handler) + * called by parent ADC driver in case of TM violation on the first SDAM. + */ + auxiliary_set_drvdata(aux_dev, adc_tm5); + + adc5_gen3_register_tm_event_notifier(dev, adctm_event_handler); + + /* + * This is to cancel any instances of tm_handler_work scheduled by + * TM interrupt, at the time of module removal. + */ + + ret =3D devm_add_action(dev, adc5_gen3_clear_work, adc_tm5); + if (ret) + return ret; + + ret =3D adc_tm5_register_tzd(adc_tm5); + if (ret) + return ret; + + /* This is to disable all ADC_TM channels in case of probe failure. */ + + return devm_add_action(dev, adc5_gen3_disable, adc_tm5); +} + +static const struct auxiliary_device_id adctm5_auxiliary_id_table[] =3D { + { .name =3D "qcom_spmi_adc5_gen3.adc5_tm_gen3", }, + { } +}; + +MODULE_DEVICE_TABLE(auxiliary, adctm5_auxiliary_id_table); + +static struct auxiliary_driver adctm5gen3_auxiliary_driver =3D { + .id_table =3D adctm5_auxiliary_id_table, + .probe =3D adc_tm5_probe, +}; + +module_auxiliary_driver(adctm5gen3_auxiliary_driver); + +MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("QCOM_SPMI_ADC5_GEN3"); --=20 2.25.1