From nobody Sun Feb 8 22:05:31 2026 Received: from TYPPR03CU001.outbound.protection.outlook.com (mail-japaneastazon11022119.outbound.protection.outlook.com [52.101.126.119]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B499434847E; Wed, 28 Jan 2026 09:36:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.126.119 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769592987; cv=fail; b=GPkX+ynyKCjMSLSSj5Kcfp6sVWnF10sl/BXsQrYbmtmsTT0jsCaSOjUqKIhzsQMhLnM40lzs6Z0qadGultZCKGST3hTggwStK3BFrxaAl73PWYbGqUBJiCxAs/rlGjjHt67vJcmpGeOiq/QHvfnElaKNyfleCeqFaPJKt7lb5Rs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769592987; c=relaxed/simple; bh=odUc3X+VVoPfw7bsoj4g3t6PQrO9S0fzz4ThameH7HU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ORlvzVlTvp7b4Wu8DUJqnlfTlgwNzFROkPZrJFeDkL/+FOAuhAv5i1rQUrKPgRw8lm4UPfxz7g3l1OQ2FiObWSkg2tKP6ryDRuZdf1usQmOoSgXvNO+hvgYQZw0qJOcfTVktWSG/rRRhbm5K9+PfcGFkDokT8xyKZLYEIDmaylM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=52.101.126.119 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=xWurJi74G79GP4BWN5FsXm4UJqw5OQtThxw0AOstvZBKApZsbEXTgwi6zz54yO2fR14d9PuBB9IV0bRGOn2LmCX1bnWsP3LqdJe9Ss06odjwD5UTtECn7R4CnB53jJy8V1e1h3O/YPPULFMMl4z/DwKNRIDSAaUxLYE0K3fg8qKikgprfdaYcZfa26HLJDf+S9ld9XdgJO7FEjyzS87o6FYoqSvLNv/2CMih9RGnPU95L9qxH5CKcKYZ8fHZPDkiO2CjHq8FMiliLQ6AL1GEOCtUKfO7dzlMcd6OB2fekHnCQCCRIzGr+OaCfH55lu1+bF+CqHRPfvbflhieRIVVBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uRkfg6lzT0php/2O7PjWai6nsN//ZW66M8ji8oiMULU=; b=zG8urlrhxEiFCt1Ktl8mX64SZilUuGnYF4US7OkkpH6uaKtCbn36ls21qaBgk9kCqOp6xv9KFsgG8RXSm6ao/ksmCdMGViO2Mx/IhOEe3I6my+Wpw/NKgi31a1/wHWGhZOovW8GwtF/YcAT/SDR+Bg5fknKxHu4PmhK5LG7NVu25IxIJYqWbiHSmWfX2aJcMw9FS0jNLcvIlYiuTb33XaxMzcmHXK++gfGh9sLNECw/Mp83YYh2BwGp42vYC9hZ+KmwVqVVVGP8UzyIB+ikXDxkq/vBoY6LR/n1tjBspm2pciNKcIphhPECdaUbPRonqlU88AIwOju9PIaxG1ujNVw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cixtech.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from PS2PR02CA0092.apcprd02.prod.outlook.com (2603:1096:300:5c::32) by TYSPR06MB7245.apcprd06.prod.outlook.com (2603:1096:405:81::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.16; Wed, 28 Jan 2026 09:36:13 +0000 Received: from OSA0EPF000000CC.apcprd02.prod.outlook.com (2603:1096:300:5c:cafe::bd) by PS2PR02CA0092.outlook.office365.com (2603:1096:300:5c::32) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9542.16 via Frontend Transport; Wed, 28 Jan 2026 09:36:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by OSA0EPF000000CC.mail.protection.outlook.com (10.167.240.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Wed, 28 Jan 2026 09:36:12 +0000 Received: from localhost.localdomain (unknown [172.16.64.196]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 057F24350706; Wed, 28 Jan 2026 17:36:12 +0800 (CST) From: Gary Yang To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, peter.chen@cixtech.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, cix-kernel-upstream@cixtech.com, Gary Yang Subject: [PATCH v4 1/3] dt-bindings: reset: add sky1 reset controller Date: Wed, 28 Jan 2026 17:36:09 +0800 Message-ID: <20260128093611.1932770-2-gary.yang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20260128093611.1932770-1-gary.yang@cixtech.com> References: <20260128093611.1932770-1-gary.yang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CC:EE_|TYSPR06MB7245:EE_ X-MS-Office365-Filtering-Correlation-Id: d4d2b36a-7c4c-44be-681a-08de5e50ad4f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?TzRZGFHsFbpbxqlKn/m39FJmFMgB0c2THpjGCL7TB6FY2Cmf5bwr0VGDVrkd?= =?us-ascii?Q?aDHB5/I2o1cQFJLKwNzwMpfOeHvz6hdFcogYDQuYJIp4yI+PPinUMBgGyXN4?= =?us-ascii?Q?WdGs/FO949gKFm/TnoHdbpiGE1sEguF9JuDvoErAyyV9EE5LhnoESDgtqFKW?= =?us-ascii?Q?Up1APhB3xO56azJ9uUKY/96CZuXc9++alTyCua5IXg+uqFPuzKKwIuF3w7m0?= =?us-ascii?Q?PRyfSdUXvCadWsqrjZnW+C2tMIx71Iy8SrzKGa/RE/Ri+wz/J6QgZCpaeFzi?= =?us-ascii?Q?mY6AgqG+C/kvNtmMygN9TePQrBpBE3Y9owwo9X8ifO9Ptt+KxqZUnqY04rMW?= =?us-ascii?Q?HRRLclBv7qk51CN3bm4MGewkgAA8vaNJUtHe07LIWmtXBvL4rEYuCS3aTK2K?= =?us-ascii?Q?LGqEPcX6lXD8evhoqI8KJJaKE3e50FaTGRBun3caSnPnP9QlmhO//47F+0uM?= =?us-ascii?Q?eqGIx9vOb026y3F9I4AkPcZRI2Btxcelmkxp1NEpotbvaUxbPlfSNUrwoysB?= =?us-ascii?Q?n0nAHqtxpNAxrGg70kPtCV16GXjmSUuI5y0uSINm45rf5hEPdC3ty9gNuQau?= =?us-ascii?Q?Pyj4b70nBic1bEjiCUrhsdCKCWWkng/7J1AFe2e8+LE6xay6xUc+HxI3j00j?= =?us-ascii?Q?cR2n3/FpW1akR7wnh/YMNS2DlW3R1bXzP9m3YKYBAVusorqjhr4rjX7zGstD?= =?us-ascii?Q?GskZwx8f1+eIWvRbipHcGMyzQjiudGmyUNqiQv0KZUes68WdYZLJAqhCnU7Z?= =?us-ascii?Q?94AWAWDWS5LTqIrvhG/Y6GaV5MQERU3CA40hthVyV17VcbeOvR9owP0Hnlzj?= =?us-ascii?Q?rLu2GZ/262x9i8ZwtKnEofo7QF4bblBthPnyzNESpT4PxjXE1RcFR7+fXuK3?= =?us-ascii?Q?EwlxRtYMXvl9R2ZC6qNucYK69lp00vRyBEFs+SHf8ekmAl6l/24wdTzzTmUW?= =?us-ascii?Q?WUZWsaWDv2fhGxeZ/yksAjskLmzJYI5eHpq2KqZWdtr/6QqPRbj/GUL+C/ts?= =?us-ascii?Q?+bQk+UeDq23QzBC1ETaiA2uxTYJxmeykcGaJIFTk3+alMJmuK2BxUFWsONzv?= =?us-ascii?Q?T06fAmKAwQ/sJ2/qjvr7nb3IDwnRa/JYDbftAJIGe7nLzphezl7hQvFlxB/A?= =?us-ascii?Q?fdU1pPU+lgqjh9n09D6/445azXN5adBCtH/pKo36GZgXMKBnzDwSb2VMI5ar?= =?us-ascii?Q?h7k6oFBAzpaG0NbPbirI2RKXTDazhX9bEVU7RZmHsD0y4Pq9n4Uw4pWtbUJm?= =?us-ascii?Q?yepStD4tiDhzBKLSXTf1VeThl1khJMCEp3I4mmrUDY/sl2wgVwrPpy/HI+Ue?= =?us-ascii?Q?IqyaBT8xvFTXYHbn1/awPi2jy0+gdVaHoHAMmnfvgDbD9iyK1VOo2urrEJmk?= =?us-ascii?Q?ZV8g2dcvruWBrW0EbiI/b/5auB9ZvqqfdoOTFe41onOn7RfPZz2T0BtOBAxS?= =?us-ascii?Q?gh9KcNEUCH0hYSty4PjkHu1NK4rQ4AbyIvy4MOiDbQGiIhw0sK4peNB/C0rX?= =?us-ascii?Q?a5fDQSvKOHQ8CQyEY0fm6Go8RGjeSaqBvm3vEU8jKmNtsqDYFCh2DspJqF07?= =?us-ascii?Q?bB36ynM0dayyZzBOXGEpA8689t4whP0uC16vX1hTKhGiGgLKZ/3YDrkfKbRb?= =?us-ascii?Q?/g=3D=3D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(13003099007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jan 2026 09:36:12.8838 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4d2b36a-7c4c-44be-681a-08de5e50ad4f X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CC.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYSPR06MB7245 Content-Type: text/plain; charset="utf-8" There are two reset controllers on Cix sky1 Soc. One is located in S0 domain, and the other is located in S0 and S5 domain. Signed-off-by: Gary Yang Link: https://lore.kernel.org/r/20251124063235.952136-2-gary.yang@cixtech.c= om Signed-off-by: Peter Chen --- .../devicetree/bindings/mfd/syscon.yaml | 7 + .../bindings/reset/cix,sky1-rst.yaml | 46 +++++ .../soc/cix/cix,sky1-system-controller.yaml | 48 +++++ include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 +++++ include/dt-bindings/reset/cix,sky1-rst.h | 164 ++++++++++++++++++ 5 files changed, 307 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/cix,sky1-rst.ya= ml create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-syst= em-controller.yaml create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 55efb83b1495..be864a6b8efb 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -170,6 +170,8 @@ properties: - cirrus,ep7209-syscon1 - cirrus,ep7209-syscon2 - cirrus,ep7209-syscon3 + - cix,sky1-system-controller + - cix,sky1-s5-system-controller - cnxt,cx92755-uc - freecom,fsg-cs2-system-controller - fsl,imx93-aonmix-ns-syscfg @@ -254,6 +256,11 @@ properties: - const: microchip,pic64gx-sysreg-scb - const: microchip,mpfs-sysreg-scb - const: syscon + - items: + - enum: + - cix,sky1-system-controller + - cix,sky1-s5-system-controller + - const: syscon =20 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml b/Do= cumentation/devicetree/bindings/reset/cix,sky1-rst.yaml new file mode 100644 index 000000000000..4323acdc2c45 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/cix,sky1-rst.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/cix,sky1-rst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 Reset Controller + +maintainers: + - Gary Yang + +description: | + CIX Sky1 reset controller can be used to reset various set of peripheral= s. + There are two reset controllers, one is located in S0 domain, the other + is located in S0 and S5 domain. + + See also: + - include/dt-bindings/reset/cix,sky1-rst.h + +properties: + compatible: + items: + - enum: + - cix,sky1-rst + - cix,sky1-rst-fch + + '#reset-cells': + const: 1 + +required: + - compatible + - '#reset-cells' + +additionalProperties: false + +examples: + - | + syscon@16000000 { + compatible =3D "cix,sky1-s5-system-controller", "syscon", + "simple-mfd"; + reg =3D <0x0 0x16000000 0x0 0x1000>; + src: reset-controller { + compatible =3D "cix,sky1-rst"; + #reset-cells =3D <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-cont= roller.yaml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-con= troller.yaml new file mode 100644 index 000000000000..f6e2776e3f53 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-controller.= yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/cix/cix,sky1-system-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 SoC system controller register region + +maintainers: + - Gary Yang + +description: + An wide assortment of registers of the system controller on Sky1 SoC, + including resets and usb. + +allOf: + - $ref: /schemas/mfd/syscon.yaml# + +properties: + compatible: + oneOf: + - contains: + - enum: + - cix,sky1-system-controller + - cix,sky1-s5-system-controller + - const: syscon + - const: simple-mfd + + reg: + maxItems: 2 + +patternProperties: + "^reset(-controller)?$": + $ref: /schemas/reset/cix,sky1-rst.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@16000000 { + compatible =3D "cix,sky1-s5-system-controller", "syscon", "simple-mf= d"; + reg =3D <0x0 0x16000000 0x0 0x1000>; + }; + diff --git a/include/dt-bindings/reset/cix,sky1-rst-fch.h b/include/dt-bind= ings/reset/cix,sky1-rst-fch.h new file mode 100644 index 000000000000..8e67d7eb92aa --- /dev/null +++ b/include/dt-bindings/reset/cix,sky1-rst-fch.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* Author: Jerry Zhu */ +#ifndef DT_BINDING_RESET_FCH_SKY1_H +#define DT_BINDING_RESET_FCH_SKY1_H + +/* func reset for sky1 fch */ + +#define SW_I3C0_RST_FUNC_G_N 0 +#define SW_I3C0_RST_FUNC_I_N 1 +#define SW_I3C1_RST_FUNC_G_N 2 +#define SW_I3C1_RST_FUNC_I_N 3 +#define SW_UART0_RST_FUNC_N 4 +#define SW_UART1_RST_FUNC_N 5 +#define SW_UART2_RST_FUNC_N 6 +#define SW_UART3_RST_FUNC_N 7 +#define SW_TIMER_RST_FUNC_N 8 + +/* apb reset for sky1 fch */ +#define SW_I3C0_RST_APB_N 9 +#define SW_I3C1_RST_APB_N 10 +#define SW_DMA_RST_AXI_N 11 +#define SW_UART0_RST_APB_N 12 +#define SW_UART1_RST_APB_N 13 +#define SW_UART2_RST_APB_N 14 +#define SW_UART3_RST_APB_N 15 +#define SW_SPI0_RST_APB_N 16 +#define SW_SPI1_RST_APB_N 17 +#define SW_I2C0_RST_APB_N 18 +#define SW_I2C1_RST_APB_N 19 +#define SW_I2C2_RST_APB_N 20 +#define SW_I2C3_RST_APB_N 21 +#define SW_I2C4_RST_APB_N 22 +#define SW_I2C5_RST_APB_N 23 +#define SW_I2C6_RST_APB_N 24 +#define SW_I2C7_RST_APB_N 25 +#define SW_GPIO_RST_APB_N 26 + +/* fch rst for xspi */ +#define SW_XSPI_REG_RST_N 27 +#define SW_XSPI_SYS_RST_N 28 + +#endif diff --git a/include/dt-bindings/reset/cix,sky1-rst.h b/include/dt-bindings= /reset/cix,sky1-rst.h new file mode 100644 index 000000000000..2f0990922aad --- /dev/null +++ b/include/dt-bindings/reset/cix,sky1-rst.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* Author: Jerry Zhu */ +#ifndef DT_BINDING_RESET_SKY1_H +#define DT_BINDING_RESET_SKY1_H + +/* reset for csu_pm */ + +#define SKY1_CSU_PM_RESET_N 0 +#define SKY1_SENSORFUSION_RESET_N 1 +#define SKY1_SENSORFUSION_NOC_RESET_N 2 + +/* reset group0 for s0 domain modules */ +#define SKY1_DDRC_RESET_N 3 +#define SKY1_GIC_RESET_N 4 +#define SKY1_CI700_RESET_N 5 +#define SKY1_SYS_NI700_RESET_N 6 +#define SKY1_MM_NI700_RESET_N 7 +#define SKY1_PCIE_NI700_RESET_N 8 +#define SKY1_GPU_RESET_N 9 +#define SKY1_NPUTOP_RESET_N 10 +#define SKY1_NPUCORE0_RESET_N 11 +#define SKY1_NPUCORE1_RESET_N 12 +#define SKY1_NPUCORE2_RESET_N 13 +#define SKY1_VPU_RESET_N 14 +#define SKY1_ISP_SRESET_N 15 +#define SKY1_ISP_ARESET_N 16 +#define SKY1_ISP_HRESET_N 17 +#define SKY1_ISP_GDCRESET_N 18 +#define SKY1_DPU_RESET0_N 19 +#define SKY1_DPU_RESET1_N 20 +#define SKY1_DPU_RESET2_N 21 +#define SKY1_DPU_RESET3_N 22 +#define SKY1_DPU_RESET4_N 23 +#define SKY1_DP_RESET0_N 24 +#define SKY1_DP_RESET1_N 25 +#define SKY1_DP_RESET2_N 26 +#define SKY1_DP_RESET3_N 27 +#define SKY1_DP_RESET4_N 28 +#define SKY1_DP_PHY_RST_N 29 + +/* reset group1 for s0 domain modules */ +#define SKY1_AUDIO_HIFI5_RESET_N 30 +#define SKY1_AUDIO_HIFI5_NOC_RESET_N 31 +#define SKY1_CSIDPHY_PRST0_N 32 +#define SKY1_CSIDPHY_CMNRST0_N 33 +#define SKY1_CSI0_RST_N 34 +#define SKY1_CSIDPHY_PRST1_N 35 +#define SKY1_CSIDPHY_CMNRST1_N 36 +#define SKY1_CSI1_RST_N 37 +#define SKY1_CSI2_RST_N 38 +#define SKY1_CSI3_RST_N 39 +#define SKY1_CSIBRDGE0_RST_N 40 +#define SKY1_CSIBRDGE1_RST_N 41 +#define SKY1_CSIBRDGE2_RST_N 42 +#define SKY1_CSIBRDGE3_RST_N 43 +#define SKY1_GMAC0_RST_N 44 +#define SKY1_GMAC1_RST_N 45 +#define SKY1_PCIE0_RESET_N 46 +#define SKY1_PCIE1_RESET_N 47 +#define SKY1_PCIE2_RESET_N 48 +#define SKY1_PCIE3_RESET_N 49 +#define SKY1_PCIE4_RESET_N 50 + +/* reset group1 for usb phys */ +#define SKY1_USB_DP_PHY0_PRST_N 51 +#define SKY1_USB_DP_PHY1_PRST_N 52 +#define SKY1_USB_DP_PHY2_PRST_N 53 +#define SKY1_USB_DP_PHY3_PRST_N 54 +#define SKY1_USB_DP_PHY0_RST_N 55 +#define SKY1_USB_DP_PHY1_RST_N 56 +#define SKY1_USB_DP_PHY2_RST_N 57 +#define SKY1_USB_DP_PHY3_RST_N 58 +#define SKY1_USBPHY_SS_PST_N 59 +#define SKY1_USBPHY_SS_RST_N 60 +#define SKY1_USBPHY_HS0_PRST_N 61 +#define SKY1_USBPHY_HS1_PRST_N 62 +#define SKY1_USBPHY_HS2_PRST_N 63 +#define SKY1_USBPHY_HS3_PRST_N 64 +#define SKY1_USBPHY_HS4_PRST_N 65 +#define SKY1_USBPHY_HS5_PRST_N 66 +#define SKY1_USBPHY_HS6_PRST_N 67 +#define SKY1_USBPHY_HS7_PRST_N 68 +#define SKY1_USBPHY_HS8_PRST_N 69 +#define SKY1_USBPHY_HS9_PRST_N 70 + +/* reset group1 for usb controllers */ +#define SKY1_USBC_SS0_PRST_N 71 +#define SKY1_USBC_SS1_PRST_N 72 +#define SKY1_USBC_SS2_PRST_N 73 +#define SKY1_USBC_SS3_PRST_N 74 +#define SKY1_USBC_SS4_PRST_N 75 +#define SKY1_USBC_SS5_PRST_N 76 +#define SKY1_USBC_SS0_RST_N 77 +#define SKY1_USBC_SS1_RST_N 78 +#define SKY1_USBC_SS2_RST_N 79 +#define SKY1_USBC_SS3_RST_N 80 +#define SKY1_USBC_SS4_RST_N 81 +#define SKY1_USBC_SS5_RST_N 82 +#define SKY1_USBC_HS0_PRST_N 83 +#define SKY1_USBC_HS1_PRST_N 84 +#define SKY1_USBC_HS2_PRST_N 85 +#define SKY1_USBC_HS3_PRST_N 86 +#define SKY1_USBC_HS0_RST_N 87 +#define SKY1_USBC_HS1_RST_N 88 +#define SKY1_USBC_HS2_RST_N 89 +#define SKY1_USBC_HS3_RST_N 90 + +/* reset group0 for rcsu */ +#define SKY1_AUDIO_RCSU_RESET_N 91 +#define SKY1_CI700_RCSU_RESET_N 92 +#define SKY1_CSI_RCSU0_RESET_N 93 +#define SKY1_CSI_RCSU1_RESET_N 94 +#define SKY1_CSU_PM_RCSU_RESET_N 95 +#define SKY1_DDR_BROADCAST_RCSU_RESET_N 96 +#define SKY1_DDR_CTRL_RCSU_0_RESET_N 97 +#define SKY1_DDR_CTRL_RCSU_1_RESET_N 98 +#define SKY1_DDR_CTRL_RCSU_2_RESET_N 99 +#define SKY1_DDR_CTRL_RCSU_3_RESET_N 100 +#define SKY1_DDR_TZC400_RCSU_0_RESET_N 101 +#define SKY1_DDR_TZC400_RCSU_1_RESET_N 102 +#define SKY1_DDR_TZC400_RCSU_2_RESET_N 103 +#define SKY1_DDR_TZC400_RCSU_3_RESET_N 104 +#define SKY1_DP0_RCSU_RESET_N 105 +#define SKY1_DP1_RCSU_RESET_N 106 +#define SKY1_DP2_RCSU_RESET_N 107 +#define SKY1_DP3_RCSU_RESET_N 108 +#define SKY1_DP4_RCSU_RESET_N 109 +#define SKY1_DPU0_RCSU_RESET_N 110 +#define SKY1_DPU1_RCSU_RESET_N 111 +#define SKY1_DPU2_RCSU_RESET_N 112 +#define SKY1_DPU3_RCSU_RESET_N 113 +#define SKY1_DPU4_RCSU_RESET_N 114 +#define SKY1_DSU_RCSU_RESET_N 115 +#define SKY1_FCH_RCSU_RESET_N 116 +#define SKY1_GICD_RCSU_RESET_N 117 +#define SKY1_GMAC_RCSU_RESET_N 118 +#define SKY1_GPU_RCSU_RESET_N 119 +#define SKY1_ISP_RCSU0_RESET_N 120 +#define SKY1_ISP_RCSU1_RESET_N 121 +#define SKY1_NI700_MMHUB_RCSU_RESET_N 122 + +/* reset group1 for rcsu */ +#define SKY1_NPU_RCSU_RESET_N 123 +#define SKY1_NI700_PCIE_RCSU_RESET_N 124 +#define SKY1_PCIE_X421_RCSU_RESET_N 125 +#define SKY1_PCIE_X8_RCSU_RESET_N 126 +#define SKY1_SF_RCSU_RESET_N 127 +#define SKY1_RCSU_SMMU_MMHUB_RESET_N 128 +#define SKY1_RCSU_SMMU_PCIEHUB_RESET_N 129 +#define SKY1_RCSU_SYSHUB_RESET_N 130 +#define SKY1_NI700_SMN_RCSU_RESET_N 131 +#define SKY1_NI700_SYSHUB_RCSU_RESET_N 132 +#define SKY1_RCSU_USB2_HOST0_RESET_N 133 +#define SKY1_RCSU_USB2_HOST1_RESET_N 134 +#define SKY1_RCSU_USB2_HOST2_RESET_N 135 +#define SKY1_RCSU_USB2_HOST3_RESET_N 136 +#define SKY1_RCSU_USB3_TYPEA_DRD_RESET_N 137 +#define SKY1_RCSU_USB3_TYPEC_DRD_RESET_N 138 +#define SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N 139 +#define SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N 140 +#define SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N 141 +#define SKY1_VPU_RCSU_RESET_N 142 + +#endif --=20 2.49.0 From nobody Sun Feb 8 22:05:31 2026 Received: from TYDPR03CU002.outbound.protection.outlook.com (mail-japaneastazon11023074.outbound.protection.outlook.com [52.101.127.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0B5E298CC0; Wed, 28 Jan 2026 09:36:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.127.74 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769592978; cv=fail; b=tRoWyO4qyq1Cq974d1gvPTz5QBNWGP4bJwfUJm4u+Skpg5xwUK3K0vUTIPqgp2Ko2U6DrTbhMRfgGYRdjktSSVBZ+oUVUIHn1Ozw5Dn4FTYao+em28KdgzGU6cadyv3R1Fbl9t2FHVatUvALOo/pRJz+k4UH/YC2rP23R3eAfRA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769592978; c=relaxed/simple; bh=WNADvlaAbeLu3AZh3oDWWOfqlusQBiSJXjMC7dIuf7o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FWND6893P3UnSdLCJachKJZgPuNyhvp+4FPOSWntP3cCUQyt4II9AG9daYDLfoSXWj9eFa0nA0Dur3u0Em53HQiMe8Zqy9pV2swdZmUaRgfhGoen9aNYzkLHTwYPgx3ectAONpTFB8Fwz2y/Bltwwi36xgno3lHXHKwWz87DhUc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=52.101.127.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=VvBGK/G/VRKl7ms47fXjUQt6EyedEBu1FsiST7eOqD36LvZCLb2BmeJMUnezYAUXeagToChE9x2MNAI21PzA5vx/El2M1PnbCxKJsmUxz2lZL9dEYEvbRweeRL+PWRQpWsqVCjQHv7THBSwENYUTziAtOAs/vEUgvCBcPUMI1RUq0kM/qBVWNyHHnuXIyMLEElTDIVfjfkHCR/ANZvaF/TZDc/XYOCOvLFRYSNJYD5sKk2/4VAF1tIjyXptuxODuAfgtPQ4gmSQUNIDYkr1Xe+LDNXbSww59yLNcZnds/eAFZOpSlWKcwDNMsVcUMpV8URUWn3KhjDKCV6/4Sn5Nwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QJA+wPUH3yFQDLWjSjn21+lnOvYt1E7BiGZVhM9H9+E=; b=hltqeVRmoY3THrw5ORJvR/bjyYq3kwO8DwVaPymBerjn2jRtH17sACnIeIVKXTonUvy1y3JQ3+ht4toJhOGtjie65AIWB6YpuMm7Z8W9kEplFStQ8kN5At1k2bxvb+CuUjgiJ96aPva+g+oqSNyu0HtQpEwlUf2cbweRx+Lw28GP8dKPMxZ8VhWi0jhLuHC8ueDh9ZZB+TcU40HMlsDS8hzIBMlM0uoF6xSBSOW5rPRZf55iTs7CNY5t6TyMmQFv4DT1bWXqIUd6IDo5p0AGu/U9SU+6H1sDQ3rawVbzMJMZDPMuGWn8K/panHddTR0Qo8wXos54D5LQrICfjpWd/w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cixtech.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from TY4PR01CA0116.jpnprd01.prod.outlook.com (2603:1096:405:379::16) by TYZPR06MB6355.apcprd06.prod.outlook.com (2603:1096:400:41d::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.16; Wed, 28 Jan 2026 09:36:13 +0000 Received: from TY2PEPF0000AB8A.apcprd03.prod.outlook.com (2603:1096:405:379:cafe::2) by TY4PR01CA0116.outlook.office365.com (2603:1096:405:379::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9564.7 via Frontend Transport; Wed, 28 Jan 2026 09:36:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by TY2PEPF0000AB8A.mail.protection.outlook.com (10.167.253.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Wed, 28 Jan 2026 09:36:12 +0000 Received: from localhost.localdomain (unknown [172.16.64.196]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 164954350714; Wed, 28 Jan 2026 17:36:12 +0800 (CST) From: Gary Yang To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, peter.chen@cixtech.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, cix-kernel-upstream@cixtech.com, Gary Yang Subject: [PATCH v4 2/3] reset: cix: add support for cix sky1 resets Date: Wed, 28 Jan 2026 17:36:10 +0800 Message-ID: <20260128093611.1932770-3-gary.yang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20260128093611.1932770-1-gary.yang@cixtech.com> References: <20260128093611.1932770-1-gary.yang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB8A:EE_|TYZPR06MB6355:EE_ X-MS-Office365-Filtering-Correlation-Id: 879d8a9a-011b-4b46-9728-08de5e50ad67 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Tn/0Y58g09jWxr/6r+1dn/RXVS5250dmlF459ok/Ryn/3uXq7a1OCEQLofc4?= =?us-ascii?Q?afcVNzHh0CBDKqs0PpGNw5lMisQXtKPyVwYgUxiZh6TcBiauQV7FBpFJ4CNc?= =?us-ascii?Q?O1T75itp7APNNvzOZCTL+T/RVpvuZ7/xOqHLrm/F8TAWvrrT4hRhg7Jm4uah?= =?us-ascii?Q?uzZh4VTicEY2qGJ1p4Vb7KP4QjHYBvqvPIHzogEhvkueFQbmDnpE3miQiKim?= =?us-ascii?Q?xYskvnFvw46u8gi9GM+aKlYu+fDezd3v55D79ZgWij1u1tKnhw/JnLkdXacL?= =?us-ascii?Q?u0MuHPhbBYTKBAw2kVag7c9jfMwCFdQpopZQ6FzCmEF9r9xlQUYLaxQcILfK?= =?us-ascii?Q?76lBl7OnjMjfoOP4SIjm/wLTd6D3SfZjJgmP9GQifQBLnQ0QTkTIo0WOBB3G?= =?us-ascii?Q?9bREZuqQaTHlasTPlefhwn1HOaqIdG9NB4JSZGVXVTOq1l1Gc34SVmDBIf8n?= =?us-ascii?Q?w6MfLJZWTS4rnmrtm/nfG2Y2b+A3w4TQfvWzfZGHxLQNF4UDtYAzhP6B3q8d?= =?us-ascii?Q?RS1xLQOF78nKna/CbbjxIKKAgmxVackrCvZHR8MMCiIUtv0G+pJ52kTlLYjF?= =?us-ascii?Q?ZnDTrwd2Y1CdgVT511sLs+jG+ojUmV967K3+llsbATEIv+dQxj6qOarkwUEx?= =?us-ascii?Q?hPhTVApZ7umYGxRFYmf89FIRk6fi9T9Mv7joJs2K9wYNK65hxD/s5ZjiJuq3?= =?us-ascii?Q?p+MYdwVQEEhYdY0jpmiumb6ocm9WuLP4qd5dQq8+ZUiNLeHbjRr/UZNLoEaz?= =?us-ascii?Q?eFK/VbSNQhlnmMtfr+8YjwgwnvfWaz9oWPVxRUlg7UdJXoc1dlOoq6ZUkt1R?= =?us-ascii?Q?tLvsUmbQH2F7jeFLWDo5ifNWo7gQ9pRlyIHJe15uHO/vcCR7VlLG1PnqIqA4?= =?us-ascii?Q?0AALkWljB/vEdYTgTxlER7SaDGpS8a8W81r0k9ALYeqBqwxqMDC3CYc63lQB?= =?us-ascii?Q?O9S0OMEQU/SP+DUqVqcW8zIA3nFtx0Cb2Z6AW62Xeeu9FwaI19nF8Wz3IsJf?= =?us-ascii?Q?llFfdIbZxHubRm5i/9zNLLwfo2LqIbbZjlNnggRuM4mPFhZa4DSQiUDLx6EG?= =?us-ascii?Q?whzfDmirM+D7WELpcgMjrm7u68IMEiSzoVX60/ZqY9oPLhzxQrl1VBJs15ve?= =?us-ascii?Q?rDUU8S97nWu3Nrv0byVM5xRK85URXBObhMPmmslne+BzsZy+0c4Qq+Ns7+5/?= =?us-ascii?Q?KWcxBV8X690TT+3nFjqyuWfSEKAtE6JxqfkEUYbfu1+nu21k43vUMvMTnfLR?= =?us-ascii?Q?0VigGeNEhIBD5XKfHvcdwgxUO9ZkU9pvHo2HiPuBZw+v4JiB2nEUhHiSmgKl?= =?us-ascii?Q?jvJaNhbNuc0/FiRMJSyi5zGalgW347xK5xiQrQIcEP33GNroGMwv5PCVIfQm?= =?us-ascii?Q?kJy/a4tG0/gEIV0G78XK31nxFyrizvNJNewDDklueK0dBnL4rK4XBi2VrYof?= =?us-ascii?Q?HJenp0lyrDSCNUgf6ZSvoeaV9hdkNrqcyVSBmE5FYZP5pFy7OEWWZG+2OLJu?= =?us-ascii?Q?7oPjTt3f072d7vjetWMyX7uPSIxgQ+P0evFE7fdMoQDt0hW3lM27MOzgAvhU?= =?us-ascii?Q?LnWif78Xx9d1kgelDuYequrEuUjmxQ2C//Lkj5GpnhQJJ2sddUDzI7zbpHUp?= =?us-ascii?Q?wI2OcY98K1HfzbeFZdHnEXdMg8ZR7BPFHyBGKim9cjJyFPVscTYAIM98rd6o?= =?us-ascii?Q?+S4GEA=3D=3D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jan 2026 09:36:12.9455 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 879d8a9a-011b-4b46-9728-08de5e50ad67 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB8A.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB6355 Content-Type: text/plain; charset="utf-8" There are two reset controllers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S0 and S5 domain. Signed-off-by: Gary Yang Link: https://lore.kernel.org/r/20251124063235.952136-3-gary.yang@cixtech.c= om Signed-off-by: Peter Chen --- drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-sky1.c | 376 +++++++++++++++++++++++++++++++++++++ 3 files changed, 384 insertions(+) create mode 100644 drivers/reset/reset-sky1.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 6e5d6deffa7d..24bf60c4e640 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -291,6 +291,13 @@ config RESET_SIMPLE - SiFive FU740 SoCs - Sophgo SoCs =20 +config RESET_SKY1 + bool "Cix Sky1 reset controller" + depends on HAS_IOMEM + depends on ARCH_CIX || COMPILE_TEST + help + This enables the reset controller for Cix Sky1. + config RESET_SOCFPGA bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFP= GA) default ARM && ARCH_INTEL_SOCFPGA diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 9c3e484dfd81..0d2e1329561d 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) +=3D reset-rzg2l-us= bphy-ctrl.o obj-$(CONFIG_RESET_RZV2H_USB2PHY) +=3D reset-rzv2h-usb2phy.o obj-$(CONFIG_RESET_SCMI) +=3D reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) +=3D reset-simple.o +obj-$(CONFIG_RESET_SKY1) +=3D reset-sky1.o obj-$(CONFIG_RESET_SOCFPGA) +=3D reset-socfpga.o obj-$(CONFIG_RESET_SPACEMIT) +=3D reset-spacemit.o obj-$(CONFIG_RESET_SUNPLUS) +=3D reset-sunplus.o diff --git a/drivers/reset/reset-sky1.c b/drivers/reset/reset-sky1.c new file mode 100644 index 000000000000..92e34b48f041 --- /dev/null +++ b/drivers/reset/reset-sky1.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * + * CIX System Reset Controller (SRC) driver + * + * Author: Jerry Zhu + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define SKY1_RESET_SLEEP_MIN_US 50 +#define SKY1_RESET_SLEEP_MAX_US 100 + +struct sky1_src_signal { + unsigned int offset; + unsigned int bit; +}; + +struct sky1_src_variant { + const struct sky1_src_signal *signals; + unsigned int signals_num; +}; + +struct sky1_src { + struct reset_controller_dev rcdev; + const struct sky1_src_signal *signals; + struct regmap *regmap; +}; + +enum { + CSU_PM_RESET =3D 0x304, + SENSORFUSION_RESET =3D 0x308, + SENSORFUSION_NOC_RESET =3D 0x30c, + RESET_GROUP0_S0_DOMAIN_0 =3D 0x400, + RESET_GROUP0_S0_DOMAIN_1 =3D 0x404, + RESET_GROUP1_USB_PHYS =3D 0x408, + RESET_GROUP1_USB_CONTROLLERS =3D 0x40c, + RESET_GROUP0_RCSU =3D 0x800, + RESET_GROUP1_RCSU =3D 0x804, +}; + +static const struct sky1_src_signal sky1_src_signals[] =3D { + /* reset group1 for s0 domain modules */ + [SKY1_CSU_PM_RESET_N] =3D { CSU_PM_RESET, BIT(0) }, + [SKY1_SENSORFUSION_RESET_N] =3D { SENSORFUSION_RESET, BIT(0) }, + [SKY1_SENSORFUSION_NOC_RESET_N] =3D { SENSORFUSION_NOC_RESET, BIT(0) }, + [SKY1_DDRC_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(0) }, + [SKY1_GIC_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(1) }, + [SKY1_CI700_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(2) }, + [SKY1_SYS_NI700_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(3) }, + [SKY1_MM_NI700_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(4) }, + [SKY1_PCIE_NI700_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(5) }, + [SKY1_GPU_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(6) }, + [SKY1_NPUTOP_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(7) }, + [SKY1_NPUCORE0_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(8) }, + [SKY1_NPUCORE1_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(9) }, + [SKY1_NPUCORE2_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(10) }, + [SKY1_VPU_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(11) }, + [SKY1_ISP_SRESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(12) }, + [SKY1_ISP_ARESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(13) }, + [SKY1_ISP_HRESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(14) }, + [SKY1_ISP_GDCRESET_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(15) }, + [SKY1_DPU_RESET0_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(16) }, + [SKY1_DPU_RESET1_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(17) }, + [SKY1_DPU_RESET2_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(18) }, + [SKY1_DPU_RESET3_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(19) }, + [SKY1_DPU_RESET4_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(20) }, + [SKY1_DP_RESET0_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(21) }, + [SKY1_DP_RESET1_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(22) }, + [SKY1_DP_RESET2_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(23) }, + [SKY1_DP_RESET3_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(24) }, + [SKY1_DP_RESET4_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(25) }, + [SKY1_DP_PHY_RST_N] =3D { RESET_GROUP0_S0_DOMAIN_0, BIT(26) }, + + /* reset group1 for s0 domain modules */ + [SKY1_AUDIO_HIFI5_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(0) }, + [SKY1_AUDIO_HIFI5_NOC_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(1) }, + [SKY1_CSIDPHY_PRST0_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(2) }, + [SKY1_CSIDPHY_CMNRST0_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(3) }, + [SKY1_CSI0_RST_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(4) }, + [SKY1_CSIDPHY_PRST1_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(5) }, + [SKY1_CSIDPHY_CMNRST1_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(6) }, + [SKY1_CSI1_RST_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(7) }, + [SKY1_CSI2_RST_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(8) }, + [SKY1_CSI3_RST_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(9) }, + [SKY1_CSIBRDGE0_RST_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(10) }, + [SKY1_CSIBRDGE1_RST_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(11) }, + [SKY1_CSIBRDGE2_RST_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(12) }, + [SKY1_CSIBRDGE3_RST_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(13) }, + [SKY1_GMAC0_RST_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(14) }, + [SKY1_GMAC1_RST_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(15) }, + [SKY1_PCIE0_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(16) }, + [SKY1_PCIE1_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(17) }, + [SKY1_PCIE2_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(18) }, + [SKY1_PCIE3_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(19) }, + [SKY1_PCIE4_RESET_N] =3D { RESET_GROUP0_S0_DOMAIN_1, BIT(20) }, + + /* reset group1 for usb phys */ + [SKY1_USB_DP_PHY0_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(0) }, + [SKY1_USB_DP_PHY1_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(1) }, + [SKY1_USB_DP_PHY2_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(2) }, + [SKY1_USB_DP_PHY3_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(3) }, + [SKY1_USB_DP_PHY0_RST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(4) }, + [SKY1_USB_DP_PHY1_RST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(5) }, + [SKY1_USB_DP_PHY2_RST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(6) }, + [SKY1_USB_DP_PHY3_RST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(7) }, + [SKY1_USBPHY_SS_PST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(8) }, + [SKY1_USBPHY_SS_RST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(9) }, + [SKY1_USBPHY_HS0_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(10) }, + [SKY1_USBPHY_HS1_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(11) }, + [SKY1_USBPHY_HS2_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(12) }, + [SKY1_USBPHY_HS3_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(13) }, + [SKY1_USBPHY_HS4_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(14) }, + [SKY1_USBPHY_HS5_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(15) }, + [SKY1_USBPHY_HS6_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(16) }, + [SKY1_USBPHY_HS7_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(17) }, + [SKY1_USBPHY_HS8_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(18) }, + [SKY1_USBPHY_HS9_PRST_N] =3D { RESET_GROUP1_USB_PHYS, BIT(19) }, + + /* reset group1 for usb controllers */ + [SKY1_USBC_SS0_PRST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(0) }, + [SKY1_USBC_SS1_PRST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(1) }, + [SKY1_USBC_SS2_PRST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(2) }, + [SKY1_USBC_SS3_PRST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(3) }, + [SKY1_USBC_SS4_PRST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(4) }, + [SKY1_USBC_SS5_PRST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(5) }, + [SKY1_USBC_SS0_RST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(6) }, + [SKY1_USBC_SS1_RST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(7) }, + [SKY1_USBC_SS2_RST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(8) }, + [SKY1_USBC_SS3_RST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(9) }, + [SKY1_USBC_SS4_RST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(10) }, + [SKY1_USBC_SS5_RST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(11) }, + [SKY1_USBC_HS0_PRST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(12) }, + [SKY1_USBC_HS1_PRST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(13) }, + [SKY1_USBC_HS2_PRST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(14) }, + [SKY1_USBC_HS3_PRST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(15) }, + [SKY1_USBC_HS0_RST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(16) }, + [SKY1_USBC_HS1_RST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(17) }, + [SKY1_USBC_HS2_RST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(18) }, + [SKY1_USBC_HS3_RST_N] =3D { RESET_GROUP1_USB_CONTROLLERS, BIT(19) }, + + /* reset group0 for rcsu */ + [SKY1_AUDIO_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(0) }, + [SKY1_CI700_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(1) }, + [SKY1_CSI_RCSU0_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(2) }, + [SKY1_CSI_RCSU1_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(3) }, + [SKY1_CSU_PM_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(4) }, + [SKY1_DDR_BROADCAST_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(5) }, + [SKY1_DDR_CTRL_RCSU_0_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(6) }, + [SKY1_DDR_CTRL_RCSU_1_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(7) }, + [SKY1_DDR_CTRL_RCSU_2_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(8) }, + [SKY1_DDR_CTRL_RCSU_3_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(9) }, + [SKY1_DDR_TZC400_RCSU_0_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(10) }, + [SKY1_DDR_TZC400_RCSU_1_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(11) }, + [SKY1_DDR_TZC400_RCSU_2_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(12) }, + [SKY1_DDR_TZC400_RCSU_3_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(13) }, + [SKY1_DP0_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(14) }, + [SKY1_DP1_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(15) }, + [SKY1_DP2_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(16) }, + [SKY1_DP3_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(17) }, + [SKY1_DP4_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(18) }, + [SKY1_DPU0_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(19) }, + [SKY1_DPU1_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(20) }, + [SKY1_DPU2_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(21) }, + [SKY1_DPU3_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(22) }, + [SKY1_DPU4_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(23) }, + [SKY1_DSU_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(24) }, + [SKY1_FCH_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(25) }, + [SKY1_GICD_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(26) }, + [SKY1_GMAC_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(27) }, + [SKY1_GPU_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(28) }, + [SKY1_ISP_RCSU0_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(29) }, + [SKY1_ISP_RCSU1_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(30) }, + [SKY1_NI700_MMHUB_RCSU_RESET_N] =3D { RESET_GROUP0_RCSU, BIT(31) }, + + /* reset group1 for rcsu */ + [SKY1_NPU_RCSU_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(0) }, + [SKY1_NI700_PCIE_RCSU_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(1) }, + [SKY1_PCIE_X421_RCSU_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(2) }, + [SKY1_PCIE_X8_RCSU_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(3) }, + [SKY1_SF_RCSU_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(4) }, + [SKY1_RCSU_SMMU_MMHUB_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(5) }, + [SKY1_RCSU_SMMU_PCIEHUB_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(6) }, + [SKY1_RCSU_SYSHUB_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(7) }, + [SKY1_NI700_SMN_RCSU_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(8) }, + [SKY1_NI700_SYSHUB_RCSU_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(9) }, + [SKY1_RCSU_USB2_HOST0_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(10) }, + [SKY1_RCSU_USB2_HOST1_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(11) }, + [SKY1_RCSU_USB2_HOST2_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(12) }, + [SKY1_RCSU_USB2_HOST3_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(13) }, + [SKY1_RCSU_USB3_TYPEA_DRD_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(14) }, + [SKY1_RCSU_USB3_TYPEC_DRD_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(15) }, + [SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(16) }, + [SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(17) }, + [SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(18) }, + [SKY1_VPU_RCSU_RESET_N] =3D { RESET_GROUP1_RCSU, BIT(19) }, +}; + +enum { + FCH_SW_RST_FUNC =3D 0x8, + FCH_SW_RST_BUS =3D 0xc, + FCH_SW_XSPI =3D 0x10, +}; + +static const struct sky1_src_signal sky1_src_fch_signals[] =3D { + /* resets for fch_sw_rst_func */ + [SW_I3C0_RST_FUNC_G_N] =3D { FCH_SW_RST_FUNC, BIT(0) }, + [SW_I3C0_RST_FUNC_I_N] =3D { FCH_SW_RST_FUNC, BIT(1) }, + [SW_I3C1_RST_FUNC_G_N] =3D { FCH_SW_RST_FUNC, BIT(2) }, + [SW_I3C1_RST_FUNC_I_N] =3D { FCH_SW_RST_FUNC, BIT(3) }, + [SW_UART0_RST_FUNC_N] =3D { FCH_SW_RST_FUNC, BIT(4) }, + [SW_UART1_RST_FUNC_N] =3D { FCH_SW_RST_FUNC, BIT(5) }, + [SW_UART2_RST_FUNC_N] =3D { FCH_SW_RST_FUNC, BIT(6) }, + [SW_UART3_RST_FUNC_N] =3D { FCH_SW_RST_FUNC, BIT(7) }, + [SW_TIMER_RST_FUNC_N] =3D { FCH_SW_RST_FUNC, BIT(20) }, + + /* resets for fch_sw_rst_bus */ + [SW_I3C0_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(0) }, + [SW_I3C1_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(1) }, + [SW_DMA_RST_AXI_N] =3D { FCH_SW_RST_BUS, BIT(2) }, + [SW_UART0_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(4) }, + [SW_UART1_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(5) }, + [SW_UART2_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(6) }, + [SW_UART3_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(7) }, + [SW_SPI0_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(8) }, + [SW_SPI1_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(9) }, + [SW_I2C0_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(12) }, + [SW_I2C1_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(13) }, + [SW_I2C2_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(14) }, + [SW_I2C3_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(15) }, + [SW_I2C4_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(16) }, + [SW_I2C5_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(17) }, + [SW_I2C6_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(18) }, + [SW_I2C7_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(19) }, + [SW_GPIO_RST_APB_N] =3D { FCH_SW_RST_BUS, BIT(21) }, + + /* resets for fch_sw_xspi */ + [SW_XSPI_REG_RST_N] =3D { FCH_SW_XSPI, BIT(0) }, + [SW_XSPI_SYS_RST_N] =3D { FCH_SW_XSPI, BIT(1) }, +}; + +static struct sky1_src *to_sky1_src(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct sky1_src, rcdev); +} + +static int sky1_reset_set(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct sky1_src *sky1src =3D to_sky1_src(rcdev); + const struct sky1_src_signal *signal =3D &sky1src->signals[id]; + unsigned int value =3D assert ? 0 : sky1src->signals[id].bit; + + return regmap_update_bits(sky1src->regmap, + signal->offset, signal->bit, value); +} + +static int sky1_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + sky1_reset_set(rcdev, id, true); + usleep_range(SKY1_RESET_SLEEP_MIN_US, + SKY1_RESET_SLEEP_MAX_US); + return 0; +} + +static int sky1_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + sky1_reset_set(rcdev, id, false); + usleep_range(SKY1_RESET_SLEEP_MIN_US, + SKY1_RESET_SLEEP_MAX_US); + return 0; +} + +static int sky1_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + sky1_reset_assert(rcdev, id); + sky1_reset_deassert(rcdev, id); + return 0; +} + +static int sky1_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + unsigned int value =3D 0; + struct sky1_src *sky1src =3D to_sky1_src(rcdev); + const struct sky1_src_signal *signal =3D &sky1src->signals[id]; + + regmap_read(sky1src->regmap, signal->offset, &value); + return !(value & signal->bit); +} + +static const struct sky1_src_variant variant_sky1 =3D { + .signals =3D sky1_src_signals, + .signals_num =3D ARRAY_SIZE(sky1_src_signals), +}; + +static const struct sky1_src_variant variant_sky1_fch =3D { + .signals =3D sky1_src_fch_signals, + .signals_num =3D ARRAY_SIZE(sky1_src_fch_signals), +}; + +static const struct reset_control_ops sky1_src_ops =3D { + .reset =3D sky1_reset, + .assert =3D sky1_reset_assert, + .deassert =3D sky1_reset_deassert, + .status =3D sky1_reset_status +}; + +static const struct regmap_config sky1_src_config[] =3D { + { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .name =3D "src", + }, +}; + +static int sky1_reset_probe(struct platform_device *pdev) +{ + struct sky1_src *sky1src; + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + const struct sky1_src_variant *variant =3D of_device_get_match_data(dev); + + sky1src =3D devm_kzalloc(dev, sizeof(*sky1src), GFP_KERNEL); + if (!sky1src) + return -ENOMEM; + + sky1src->regmap =3D device_node_to_regmap(np->parent); + if (IS_ERR(sky1src->regmap)) { + dev_err(dev, "Unable to get sky1-src regmap"); + return PTR_ERR(sky1src->regmap); + } + + sky1src->signals =3D variant->signals; + sky1src->rcdev.owner =3D THIS_MODULE; + sky1src->rcdev.nr_resets =3D variant->signals_num; + sky1src->rcdev.ops =3D &sky1_src_ops; + sky1src->rcdev.of_node =3D dev->of_node; + sky1src->rcdev.dev =3D dev; + + return devm_reset_controller_register(dev, &sky1src->rcdev); +} + +static const struct of_device_id sky1_reset_dt_ids[] =3D { + { .compatible =3D "cix,sky1-rst", .data =3D &variant_sky1 }, + { .compatible =3D "cix,sky1-rst-fch", .data =3D &variant_sky1_fch }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, sky1_reset_dt_ids); + +static struct platform_driver sky1_reset_driver =3D { + .probe =3D sky1_reset_probe, + .driver =3D { + .name =3D KBUILD_MODNAME, + .of_match_table =3D sky1_reset_dt_ids, + }, +}; +module_platform_driver(sky1_reset_driver) + +MODULE_AUTHOR("Jerry Zhu "); +MODULE_DESCRIPTION("Cix Sky1 reset driver"); +MODULE_LICENSE("GPL"); --=20 2.49.0 From nobody Sun Feb 8 22:05:31 2026 Received: from TYDPR03CU002.outbound.protection.outlook.com (mail-japaneastazon11023119.outbound.protection.outlook.com [52.101.127.119]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8FDCDF76; Wed, 28 Jan 2026 09:36:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.127.119 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769592979; cv=fail; b=ZZUKKeWfyrIxeWf6nyvvaNqhhiTLxO0LMP8zSJgF38w1TtpaEmNlfLZC0AzmGVSdgY6PkO4il62vE2sRqRo74mMoq8pcLkCG5mLV7WJpNvFV0Q0tj+o5xPUKzE63xR60tUaCWqHEuuetIMoT7bSiFJYrkCBDbmMXsLSKcEserbs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769592979; c=relaxed/simple; bh=joVc26Zp2PAyFoEeyvfmsXXOalVXpZwsGDVD/FYhU3I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Mz4WyV1GRLCUxhqBuX3I/4jF8IexpbxZbKen366XRkwJ0FWZuu9RBxPw/lXvgZvM8vo+lIgzaUjAFckC2Lw968FV0Z4guEAh8e01AmKV2zJxp14OqvUeHJzQh5FLWZ7Nvw5/NMGSWoZM9E1C/BIt0qlpDs5IqOTzZoQc9jSZZKQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=52.101.127.119 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=j1IpCa30cKnAgBnOB5Q93WFLso/JXLPxUs30hBDnjxcM6g2F+soCoGEoLXFfmjfV5nYNf26OtCX4hvqUImEqQZ9Qp2F5a/I1W9Cva2D4ZIm+gof5sKKyVPa+77Vm8PNif9jwyMRmjXnxhjY2keVZIfu7bDyb52hagZv3eqcERqk0jUEeMwKWBYYNwWjJjRzvAts5RbA7KmB0hudkUCrTgJEJO9EKciN+g0Mf6dee/+W10UVvjKsvFIqKHZaRJV8xnR8WwW5MID4a0Y/SfTktn1KmAN8Fv3aeOmZxTan8+jyxQzSKRpztVvc/vQRRnfH3n8ZfNv+/GHQWtdInPLCuAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qgx/OZovnYaqJbXU8yLMLwe/etamtsRy8FltMyp7ndQ=; b=ne5xJLpWu/jrbYIx4eGLbYOlTSr/wjya9UlhpKuUA6gwb0fyHvv7PH62PDgvJ4L7N+m+BHfV5LLPqRk0l0Xl5q6XzzL4YC6w0sSTFfIJy1q21OQiLRQjIBod3yIGnKKvzc8+8Z1AZzALPqskkzzydGtStA+7W05sRLhc8dRn69BQbSQnxDtrqBddIIR0JwLWpz1ru/zOuYMh27Bw9BJt0jAJdDZmLp5zJjKU3ioILy6RLSC+cUvkhZYo9oNkx+YKt2xHsk+YvRXzkVAJt0ZWvVBcAnmn4TcozNcsNXiuaa6Y9d++iHLfqDMXoZPdVuwFMjlH/dUgICHatoBBLeNrDg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cixtech.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from SI2PR02CA0020.apcprd02.prod.outlook.com (2603:1096:4:195::7) by KL1PR06MB6428.apcprd06.prod.outlook.com (2603:1096:820:f6::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.15; Wed, 28 Jan 2026 09:36:14 +0000 Received: from SG2PEPF000B66CA.apcprd03.prod.outlook.com (2603:1096:4:195:cafe::cd) by SI2PR02CA0020.outlook.office365.com (2603:1096:4:195::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9564.7 via Frontend Transport; Wed, 28 Jan 2026 09:36:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CA.mail.protection.outlook.com (10.167.240.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.3 via Frontend Transport; Wed, 28 Jan 2026 09:36:12 +0000 Received: from localhost.localdomain (unknown [172.16.64.196]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 269BB4350715; Wed, 28 Jan 2026 17:36:12 +0800 (CST) From: Gary Yang To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, peter.chen@cixtech.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, cix-kernel-upstream@cixtech.com, Gary Yang Subject: [PATCH v4 3/3] arm64: dts: cix: add support for cix sky1 resets Date: Wed, 28 Jan 2026 17:36:11 +0800 Message-ID: <20260128093611.1932770-4-gary.yang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20260128093611.1932770-1-gary.yang@cixtech.com> References: <20260128093611.1932770-1-gary.yang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CA:EE_|KL1PR06MB6428:EE_ X-MS-Office365-Filtering-Correlation-Id: e622345c-7274-49cb-eb3c-08de5e50ad28 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?bBe0tCbngmeuB59O2SmhzhuJ/coTqjU9eT+2yZo9u7BdaL3YBvsNX4sWSIKg?= =?us-ascii?Q?EE8v0kOXtmXkU7zavnduksCuSq/o6NibCP+bBwU2AdaswTWJshg0ViGAOVt8?= =?us-ascii?Q?9uni38GFvta+QU3D1BVju1XEcINnBbnU2eSik0PnAvfC5pEezQ13jI+LHiuQ?= =?us-ascii?Q?PvdSvc73X4RW2OsvX3axY9auUT/A++eVyzyzNfL8kNT9Gu3jz9yVJIrQpUEC?= =?us-ascii?Q?JOejPGzypjXRW/EJFMKb3Vz2QSJCk4MOScEXN9X2gSuTj9BDMwixFWUN1rdE?= =?us-ascii?Q?WvF2tNCjls4cz1r6Dh5mcm8IKGhHRLoJtYfh5+EMgKTomEJR7+jDJ0j0sUcg?= =?us-ascii?Q?neLxxSOIl5Q/txMzZpyS3EMxSX0YDikDk9c8tyxschFP9L95CFg8azm0E+dG?= =?us-ascii?Q?e8f/McduXxQBwppWvllvtW9hMtUBFiwISUiw4kSvlii/nhSmUBiTlKk6CaB/?= =?us-ascii?Q?e5dV5rwz5VYLSbWf735JA1Cm5VvMvrnaVW/fG08eSjjzuuiGzAS5PfqHP5Oh?= =?us-ascii?Q?WiH65OK+VTJBqtNYeM0kJhXUHlQa6jg0oQVVrHG/7fY8vG1HXTwNCqeTN0bU?= =?us-ascii?Q?zFjRUzAlp5Ej4VKe1HFW3LM9EjABDg7Q6fnfTbp3ckwak30vJ68R58J9m2BT?= =?us-ascii?Q?V3TvFvUEwpTCxLxCMjWAWxpoHuTSYzIe9AD5xbKaSnd0y5ggt7ZgZvIhnERe?= =?us-ascii?Q?3bXyQsHdIWkAns0/2CtDU2cbxph3HyuKyqvX/yadWp+oNnUAJLDWPTcnEJ7v?= =?us-ascii?Q?WZGUB/8QBxTaCcGFDr+xvtzJ/SwWlhzv+YfooCRsX/4xKrvBuwpxOUxG+J5e?= =?us-ascii?Q?6+rRBO8rkUIw9141yGMKNy2x+9to5vDqM9DNL0OOj2EvxRetWDvsavKfuqKY?= =?us-ascii?Q?SQkvNhGbvDtFoKgqH8024mmX357g6LWDK4EqU8v0+itFNW0dpH0inLdkoRvU?= =?us-ascii?Q?hi8uRd2zu9pZ7qliUse6ZtypI39d5ho+8/Nrnm+gGyEHnVe10LC1MuJQpBaS?= =?us-ascii?Q?6kFXk6GpRwf9lYjgcbwpEQDBvsNoTkwN2qvmGDADy0d6eW9T3QtGrnwgzuxd?= =?us-ascii?Q?w5KrTp8UgY4chfQYMMXgwTi3aE//ZdlgaRxkmpQ9CKoHnOOMZXbW/9sCkljC?= =?us-ascii?Q?1HAhvNwKDMVg6l+SGBerKEzJPWJt/FgqQwb/tQq2Ln2tW0J//s8b/DctQ/7D?= =?us-ascii?Q?WinEWAGhYAWAsrk4aQFJ7h1axaNhcW+wBE353UnI/XNA3vMhUSvNO2FcQLzN?= =?us-ascii?Q?lt7fbUc/KCFhetxheafYDuosjMThyMKIMJwIk6LwafPPMvXm/XONANfPFafl?= =?us-ascii?Q?d69PfI9rJaqzw7U/07RSzwQiQ+7SK4tjEuCNiIK/vd4lSZBLZhMNBFYJot/f?= =?us-ascii?Q?qYBJg7QbDwKS89iXTASQkImfx2J2CTBXVzDTGYX9WMlpDAOAxB5tLv6Dbftt?= =?us-ascii?Q?CJfWmz0n4lNJDS8MVVAarL4OKvwGuDKOlb/J1yAt83DK1cC0PiayjG0ex6yt?= =?us-ascii?Q?jXqHrCpaPMSwBGAjZWNhcunzdSvkUwdci9eIIIpj4AIB6zNQ9jVVZU9HYg7U?= =?us-ascii?Q?oayuGyguHcsYYE1J+5TNUAVOr4/ZXsPGe3R9KC/HYsLXyyhrxTKgz9Pn4bNe?= =?us-ascii?Q?BQAWjnXXWAgP3C5RHAMel8PY0Ld4mKq9sO/rcyyKiF9L3efhQucIwMFMUbUP?= =?us-ascii?Q?VvnWNQ=3D=3D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jan 2026 09:36:12.6861 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e622345c-7274-49cb-eb3c-08de5e50ad28 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CA.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KL1PR06MB6428 Content-Type: text/plain; charset="utf-8" There are two reset conctrollers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S0 and S5 domain. Signed-off-by: Gary Yang Link: https://lore.kernel.org/r/20251124063235.952136-4-gary.yang@cixtech.c= om Signed-off-by: Peter Chen --- arch/arm64/boot/dts/cix/sky1.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi index 64b76905cbff..45c008bf580a 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -348,6 +348,17 @@ i3c1: i3c@4100000 { status =3D "disabled"; }; =20 + syscon: syscon@4160000 { + compatible =3D "cix,sky1-system-controller", "syscon", + "simple-mfd"; + reg =3D <0x0 0x4160000 0x0 0x100>; + + src_fch: reset-controller { + compatible =3D "cix,sky1-rst-fch"; + #reset-cells =3D <1>; + }; + }; + iomuxc: pinctrl@4170000 { compatible =3D "cix,sky1-pinctrl"; reg =3D <0x0 0x04170000 0x0 0x1000>; @@ -568,6 +579,17 @@ ppi_partition1: interrupt-partition-1 { }; }; =20 + s5_syscon: s5-syscon@16000000 { + compatible =3D "cix,sky1-s5-system-controller", "syscon", + "simple-mfd"; + reg =3D <0x0 0x16000000 0x0 0x1000>; + + src: reset-controller { + compatible =3D "cix,sky1-rst"; + #reset-cells =3D <1>; + }; + }; + iomuxc_s5: pinctrl@16007000 { compatible =3D "cix,sky1-pinctrl-s5"; reg =3D <0x0 0x16007000 0x0 0x1000>; --=20 2.49.0