From nobody Sat Feb 7 15:15:23 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5EC154652; Wed, 28 Jan 2026 01:55:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769565334; cv=none; b=X3GqPB8vu65j+PL4zhEU68eUO4I+/tYSojLr2TTiOmTb8k01DahCHb3tscqlcR1260FZ84NqSq+rheikj2ioa8bl5WzN7QK8fguh33RawQzrJr9aAabPgkaKP2mEusRs5ygQXnoafl5TD8UpQDxxFTuoqwmd6dhUewPVmkkp44s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769565334; c=relaxed/simple; bh=CP/qnvB6fXOxVLAIQC9mjygAeI/xPgo7d+fUUVeDfKo=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=JTVsuyuYx2WWEfg6dUxv83Imbdyp35GMIx5zO9TFohj7h3PPM6Rc8Z36rxpsBdrOqbXp70+FdTWA3kQpVkr7nMwDxEya7DWAkyFtjEIEPZKuG2Mdu9qPWguij2Qdf2rFm08B74C6ouyqb2MHfdjHvnoroCF6JNBsIbTquxbZsJ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FVyxCgwP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FVyxCgwP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31507C116C6; Wed, 28 Jan 2026 01:55:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769565334; bh=CP/qnvB6fXOxVLAIQC9mjygAeI/xPgo7d+fUUVeDfKo=; h=From:To:Cc:Subject:Date:From; b=FVyxCgwPXJrlaMWB4T5cTDCSpuj4TlfoPEmeYd0jetk9q6NjTz2UhPfMxzo0WRoeo SCrtXVLFyEPzKl4ffv6QPcTd5QNetW3iMCbtv0/QTl8VYFzXzGHp/6ycgNfKlj2CjU RUfBOKDt/sItxsq05wvH4OSNkZFyi0oTQR6eh/7a8S+cj/qljlPKbzQd18KUMxlukg JPllKMscdntViFRqlQ/TmUT5JSVAavP34GKnwymsDRKlST2cYyKEIC0UdT7zKFhPyu JslZO5gi971aqdKHeAXOzhk8AHE888EqxZE7LPK/PQWToJrjp4gj2S9t4OPflrQ+5g qw4Bvya7VAwNQ== From: "Rob Herring (Arm)" To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Krzysztof Kozlowski , Conor Dooley Cc: Elad Nachman , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] arm/arm64: dts: marvell: Drop unused .dtsi Date: Tue, 27 Jan 2026 19:55:20 -0600 Message-ID: <20260128015521.3694910-1-robh@kernel.org> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These .dtsi files are not included anywhere in the tree and can't be tested. Signed-off-by: Rob Herring (Arm) --- v2: - Keep armada-7020.dtsi and armada-ap806-dual.dtsi which now have a user. --- arch/arm/boot/dts/marvell/armada-380.dtsi | 148 ------------------ arch/arm64/boot/dts/marvell/armada-8020.dtsi | 20 --- .../dts/marvell/cn9130-db-comexpress.dtsi | 96 ------------ 3 files changed, 264 deletions(-) delete mode 100644 arch/arm/boot/dts/marvell/armada-380.dtsi delete mode 100644 arch/arm64/boot/dts/marvell/armada-8020.dtsi delete mode 100644 arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi diff --git a/arch/arm/boot/dts/marvell/armada-380.dtsi b/arch/arm/boot/dts/= marvell/armada-380.dtsi deleted file mode 100644 index e94f22b0e9b5..000000000000 --- a/arch/arm/boot/dts/marvell/armada-380.dtsi +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 380 SoC. - * - * Copyright (C) 2014 Marvell - * - * Lior Amsalem - * Gregory CLEMENT - * Thomas Petazzoni - */ - -#include "armada-38x.dtsi" - -/ { - model =3D "Marvell Armada 380 family SoC"; - compatible =3D "marvell,armada380"; - - cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - enable-method =3D "marvell,armada-380-smp"; - - cpu@0 { - device_type =3D "cpu"; - compatible =3D "arm,cortex-a9"; - reg =3D <0>; - }; - }; - - soc { - internal-regs { - pinctrl@18000 { - compatible =3D "marvell,mv88f6810-pinctrl"; - }; - }; - - pcie { - compatible =3D "marvell,armada-370-pcie"; - status =3D "disabled"; - device_type =3D "pci"; - - #address-cells =3D <3>; - #size-cells =3D <2>; - - msi-parent =3D <&mpic>; - bus-range =3D <0x00 0xff>; - - ranges =3D - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; - - /* x1 port */ - pcie@1,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82000800 0 0x80000 0 0x2000>; - reg =3D <0x0800 0 0 0 0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupt-names =3D "intx"; - interrupts-extended =3D <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells =3D <1>; - ranges =3D <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port =3D <0>; - marvell,pcie-lane =3D <0>; - clocks =3D <&gateclk 8>; - status =3D "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells =3D <1>; - }; - }; - - /* x1 port */ - pcie@2,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82001000 0 0x40000 0 0x2000>; - reg =3D <0x1000 0 0 0 0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupt-names =3D "intx"; - interrupts-extended =3D <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells =3D <1>; - ranges =3D <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie2_intc 0>, - <0 0 0 2 &pcie2_intc 1>, - <0 0 0 3 &pcie2_intc 2>, - <0 0 0 4 &pcie2_intc 3>; - marvell,pcie-port =3D <1>; - marvell,pcie-lane =3D <0>; - clocks =3D <&gateclk 5>; - status =3D "disabled"; - - pcie2_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells =3D <1>; - }; - }; - - /* x1 port */ - pcie@3,0 { - device_type =3D "pci"; - assigned-addresses =3D <0x82001800 0 0x44000 0 0x2000>; - reg =3D <0x1800 0 0 0 0>; - #address-cells =3D <3>; - #size-cells =3D <2>; - interrupt-names =3D "intx"; - interrupts-extended =3D <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells =3D <1>; - ranges =3D <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range =3D <0x00 0xff>; - interrupt-map-mask =3D <0 0 0 7>; - interrupt-map =3D <0 0 0 1 &pcie3_intc 0>, - <0 0 0 2 &pcie3_intc 1>, - <0 0 0 3 &pcie3_intc 2>, - <0 0 0 4 &pcie3_intc 3>; - marvell,pcie-port =3D <2>; - marvell,pcie-lane =3D <0>; - clocks =3D <&gateclk 6>; - status =3D "disabled"; - - pcie3_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells =3D <1>; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot= /dts/marvell/armada-8020.dtsi deleted file mode 100644 index b6fc18876093..000000000000 --- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and - * two CP110. - */ - -#include "armada-ap806-dual.dtsi" -#include "armada-80x0.dtsi" - -/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock - * in CP master is not connected (by package) to the oscillator. So - * disable it. However, the RTC clock in CP slave is connected to the - * oscillator so this one is let enabled. - */ - -&cp0_rtc { - status =3D "disabled"; -}; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi b/arch/a= rm64/boot/dts/marvell/cn9130-db-comexpress.dtsi deleted file mode 100644 index 028496ebc473..000000000000 --- a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Marvell International Ltd. - * - * Device tree for the CN9130-DB Com Express CPU module board. - */ - -#include "cn9130-db.dtsi" - -/ { - model =3D "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board"; - compatible =3D "marvell,cn9130-cpu-module", "marvell,cn9130", - "marvell,armada-ap807-quad", "marvell,armada-ap807"; - -}; - -&ap0_reg_sd_vccq { - regulator-max-microvolt =3D <1800000>; - states =3D <1800000 0x1 1800000 0x0>; - /delete-property/ gpios; -}; - -&cp0_reg_usb3_vbus0 { - /delete-property/ gpio; -}; - -&cp0_reg_usb3_vbus1 { - /delete-property/ gpio; -}; - -&cp0_reg_sd_vcc { - status =3D "disabled"; -}; - -&cp0_reg_sd_vccq { - status =3D "disabled"; -}; - -&cp0_sdhci0 { - status =3D "disabled"; -}; - -&cp0_eth0 { - status =3D "disabled"; -}; - -&cp0_eth1 { - status =3D "okay"; - phy =3D <&phy0>; - phy-mode =3D "rgmii-id"; -}; - -&cp0_eth2 { - status =3D "disabled"; -}; - -&cp0_mdio { - status =3D "okay"; - pinctrl-0 =3D <&cp0_ge_mdio_pins>; - phy0: ethernet-phy@0 { - status =3D "okay"; - }; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible =3D "marvell,cp115-standalone-pinctrl"; - - cp0_ge_mdio_pins: ge-mdio-pins { - marvell,pins =3D "mpp40", "mpp41"; - marvell,function =3D "ge"; - }; - }; -}; - -&cp0_sdhci0 { - status =3D "disabled"; -}; - -&cp0_spi1 { - status =3D "okay"; -}; - -&cp0_usb3_0 { - status =3D "okay"; - usb-phy =3D <&cp0_usb3_0_phy0>; - phy-names =3D "usb"; - /delete-property/ phys; -}; - -&cp0_usb3_1 { - status =3D "okay"; - usb-phy =3D <&cp0_usb3_0_phy1>; - phy-names =3D "usb"; - /delete-property/ phys; -}; --=20 2.51.0