From nobody Sat Feb 7 08:55:05 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FD672F7AAC for ; Wed, 28 Jan 2026 10:33:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769596405; cv=none; b=X7fahSE8TSOYjZvey1E6CLVKs7mbIA0YCZLf/cxI44ZATxTzVT1R2dKyCeLsqMgUC4DE1qQlFj50ehPJe0gk5ZDfucX8+Dyf/Wrmct8lT3OXntnQb/c+0N8VN0kAN8djPQpSSdRJm55ttwXkc+wLAW3OeatULeGpHm7Q/nAFZ6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769596405; c=relaxed/simple; bh=NTt92laGBXWa0dXkz821jS+e4ktZkVNCs2eds0MYEEw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VFJMzcphrrhkuvaG6pjqEWQlTyXdynhpdlgbuuo0WxlVpDTj69c8lHGd6PgmZE2J05JDlN9iAy9Pm8LKe2FznL0ksBt7qXtCloUPzciPU5G/CYCuhpkDu3b+SSFL6ZaNWk28iGZSq7588+OYmcEM+wX6Cs67fQa60M0jOYroumM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=KMX7uLwt; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="KMX7uLwt" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-47ee07570deso51276175e9.1 for ; Wed, 28 Jan 2026 02:33:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769596402; x=1770201202; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AZKhZYCrGgSV5qxzyJJ87NXFvhprZ3awbdJBkiwYbV0=; b=KMX7uLwtZsWYI2pLrnEJJgcDIeyw5blcDDBu20xQIEEKilresGm8u6520VPntGodk0 VY+YnyRbBJmNUJ4V8I2EXLcxrhe69boFToTuRc+jL7a5dbSWVhr9ewe2QRgfGgxslqZf Npnvp0Xs9dbkIyn8HkILuzQG6pUdKUEU0q4z4/LDuIneJ+Do+sRQOLpqv5AlSF+YEBKt QNFnXM5y20abrYP2y6XPoHCpxKE3g0FN75GlIOqxsTD3rYVqyslLHEY/F0bnHUd+MPX7 1AMZVk5JPt7pOil8yhHJf02Ujfmf79EZQ4eVXICS44P6j52l/avf5nwAUgGy1QGSV8wp V3Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769596402; x=1770201202; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=AZKhZYCrGgSV5qxzyJJ87NXFvhprZ3awbdJBkiwYbV0=; b=UDk88jIruiiVCJCFQ4xdSVGhkKSPTSE6e75qV4OpWmvnCYf0MDPqIjEFDHSVsRcwtz yRUzFz6fMvhhIsVhovlnM6rbC67L62RI50r8fXQC4YMM7TN8SnNUR97i9RxZZhc2dRAl tJzvFRcVziz+R0aqScwgp/I/+7zI0mYVnranU3+YB3ysDKGpYrX7ZNSGRnsBjntY0gkg OvSEG63gIwslE8AQVJdaPapS93yMCUut6wsB37Mb4vQkXnwajS6VYgSjCD0d06FweN2k OUyL4nmDk7zEalQgaUixiRZuGALsv+LhfZc6bJELS73VZM+8lZQai1hhvhcmNxUGgkSJ BQ1Q== X-Forwarded-Encrypted: i=1; AJvYcCWOMfDvfcudNcBujujvCXu+Yfa0VT76HtG9i2PYjJba9gtZx16FsrrT50iShWuCxS9QvcFYd+xLM2kLECM=@vger.kernel.org X-Gm-Message-State: AOJu0YyYYCQ2y+FZdwoI7Y2Ha/hHiKuhVdbWmiNLAiLmKKMQFIuP5LBb yTCGP0eO7SGT7pSxx1R/rdFDN9ppwCMaKH2CdFg2TG3GKx38INM1NKkyiOIiTfpu+mRtN+ZkfP6 +KzXf X-Gm-Gg: AZuq6aJq00XqwsL1mUK3pSjP2GcN14w9Xq6wMovSQabaq/5oSXIegh9qOh4FehBWRra wxrgLarHigVF/Ky/Bd/n4CRx9BED2O5tJR/EenrR/N7QzNEb96NIhFOROPXmk2AqMQlJ94/5YuG gb7hWmPIQ68GNSPnyaDwagT2/RIF5anpBqlgURIn+SvHZMgS7t7ElaS1JMfdasgJbRH3hIA3OmS RyaCr7IAzFWzBPnm3UUtKAZxcdB22qsAuIawcAAanVNNmoBoACHhkhzlUp+vBB+DTLCssxRXCe+ rUdz+TJxQv+BNa8e8kbSxt6FmW4xAAt3fm7MU5fmMPVi3F7EN/6G8ICuoal0379hvyzyfcjyezF /tygJp6AsLCWPYrbyCj7lgd2fk3HH5go1c8LTfP0jCSa43hwBQbV0eyfqggWjMAj4KPbCADQ+QX 8YzOhLLM5NAeQFnqTB1I4EWylhhllKsvA= X-Received: by 2002:a05:600c:1d16:b0:47a:8088:439c with SMTP id 5b1f17b1804b1-48069c9ec08mr66603525e9.35.1769596402191; Wed, 28 Jan 2026 02:33:22 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e132356dsm6241692f8f.33.2026.01.28.02.33.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 02:33:21 -0800 (PST) From: Neil Armstrong Date: Wed, 28 Jan 2026 11:33:17 +0100 Subject: [PATCH 2/3] arm64: dts: qcom: sm8650: add CPU cache size properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-topic-sm8650-upstream-cpu-props-v1-2-9fbb5efe7f07@linaro.org> References: <20260128-topic-sm8650-upstream-cpu-props-v1-0-9fbb5efe7f07@linaro.org> In-Reply-To: <20260128-topic-sm8650-upstream-cpu-props-v1-0-9fbb5efe7f07@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4680; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=NTt92laGBXWa0dXkz821jS+e4ktZkVNCs2eds0MYEEw=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBpeeXund8wUunw3MVwyirTyS3bly+wNI7jZ3rG3N/z oz2zRz6JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCaXnl7gAKCRB33NvayMhJ0bJfD/ wL96X2/VTV/Cx7MTWUbHACD6rX4oqVHql99OTq6Fxh8oU/aiPBfWx1GwpQ48hH/RCEdJcdJw4f8k7i d9GESHE6MXgZXaQw3KkYC8rvfYmV/jl19Npag6YSpI9/WS1oE5QktpaSIhA6qlPwPYm5TT0Ext3TOn 3P2waGtgJ+5F5QwmUlutunVtMW59vWp+hnUL57U9atQFLe6pRbVSoZFWFOBwJVZ3h1UZs7w9isIERn 6hbo04+VSmXAU0p6mkTloSZZP/SFCx+XJHYsCw9KFlfJDwfrJLOVQU1mRUFBFu1TgClaJBNuffYsCI fMb4Iq2tHFNBVz7FhtTBOAGectzWEr7B5b0JacB55o9BSuZIIKxaF6kgDQJy/1pZTvrb3dd+kYz4ws 6z9KCZww43b9tO2lpEOl5Hcd8wJ8v/tlTyATzLLI4UUd3dCRiOLtPwnLPXm3nx0cBwieWKpa9344LP PgqhmkZggFT/DSXcdXVRZIE1Kaoyek74Neak9ubD7jXQY/9LH8OyFM/WhGjbMsxaXQ6//x0s1TNmh3 KrJygiwy6FRhO/xRUzB6v+KHE1ibEvFOp1oDIHiTyPTNxsCKWWOoqMj5SmLC5bSTWNtkW8FapDzN5a o0ZOZn2tqxmPOfX/oCgV/B6Uzv1fzH5lDHWZus2N3tOOBAKwtFNJzp5BTLtw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add the L1 cache size and its line size (cache-size and cache-line-size) with the corresponding L1-I cache and L1-D cache. L1 cache is unified, but clidr_el1 register (get_cache_type) tells that L1 cache is separated (CACHE_TYPE_SEPARATE), add i-cache-line-size and d-cache-line-size and cache-line-size of L3 cache is specified. All cache line sizes were confirmed by checking ccsidr_el1. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 56 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 8671c25dd68f..f8563ec79dc6 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -75,6 +75,11 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a520"; reg =3D <0 0>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 0>; =20 power-domains =3D <&cpu_pd0>; @@ -103,11 +108,15 @@ l2_0: l2-cache { cache-level =3D <2>; cache-unified; next-level-cache =3D <&l3_0>; + cache-size =3D <262144>; + cache-line-size =3D <64>; =20 l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; + cache-size =3D <12582912>; + cache-line-size =3D <64>; }; }; }; @@ -117,6 +126,11 @@ cpu1: cpu@100 { compatible =3D "arm,cortex-a520"; reg =3D <0 0x100>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 0>; =20 power-domains =3D <&cpu_pd1>; @@ -146,6 +160,11 @@ cpu2: cpu@200 { compatible =3D "arm,cortex-a720"; reg =3D <0 0x200>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 3>; =20 power-domains =3D <&cpu_pd2>; @@ -174,6 +193,8 @@ l2_200: l2-cache { cache-level =3D <2>; cache-unified; next-level-cache =3D <&l3_0>; + cache-size =3D <524288>; + cache-line-size =3D <64>; }; }; =20 @@ -182,6 +203,11 @@ cpu3: cpu@300 { compatible =3D "arm,cortex-a720"; reg =3D <0 0x300>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 3>; =20 power-domains =3D <&cpu_pd3>; @@ -210,6 +236,8 @@ l2_300: l2-cache { cache-level =3D <2>; cache-unified; next-level-cache =3D <&l3_0>; + cache-size =3D <524288>; + cache-line-size =3D <64>; }; }; =20 @@ -218,6 +246,11 @@ cpu4: cpu@400 { compatible =3D "arm,cortex-a720"; reg =3D <0 0x400>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 3>; =20 power-domains =3D <&cpu_pd4>; @@ -246,6 +279,8 @@ l2_400: l2-cache { cache-level =3D <2>; cache-unified; next-level-cache =3D <&l3_0>; + cache-size =3D <524288>; + cache-line-size =3D <64>; }; }; =20 @@ -254,6 +289,11 @@ cpu5: cpu@500 { compatible =3D "arm,cortex-a720"; reg =3D <0 0x500>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 1>; =20 power-domains =3D <&cpu_pd5>; @@ -282,6 +322,8 @@ l2_500: l2-cache { cache-level =3D <2>; cache-unified; next-level-cache =3D <&l3_0>; + cache-size =3D <524288>; + cache-line-size =3D <64>; }; }; =20 @@ -290,6 +332,11 @@ cpu6: cpu@600 { compatible =3D "arm,cortex-a720"; reg =3D <0 0x600>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 1>; =20 power-domains =3D <&cpu_pd6>; @@ -318,6 +365,8 @@ l2_600: l2-cache { cache-level =3D <2>; cache-unified; next-level-cache =3D <&l3_0>; + cache-size =3D <524288>; + cache-line-size =3D <64>; }; }; =20 @@ -326,6 +375,11 @@ cpu7: cpu@700 { compatible =3D "arm,cortex-x4"; reg =3D <0 0x700>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 2>; =20 power-domains =3D <&cpu_pd7>; @@ -354,6 +408,8 @@ l2_700: l2-cache { cache-level =3D <2>; cache-unified; next-level-cache =3D <&l3_0>; + cache-size =3D <2097152>; + cache-line-size =3D <64>; }; }; =20 --=20 2.34.1