From nobody Sat Feb 7 07:11:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EF803793BE; Wed, 28 Jan 2026 20:28:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632092; cv=none; b=aKjlj3AKOIt2BFsfDtSfNVQzuOCOMlNwBHCyEulBzGVPuHeOtS/tLDopg2yTAHCbmiLk8AwFFdjl6Qzam3c4rjGFwzQskXL67MFmQlt1c5rrRFOvkbdRR4DX+n4rMD9kZCqSTA5C/dKZKacFR8tHE7deLLGqyYi1DCfrg3DsePw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632092; c=relaxed/simple; bh=/31EreH53ZbfLgFROUgaazBzJSVsVuqJTT5oOs7SCjM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e1ga4kkXUtpwyIRI5LhctQFtbRUyBt/SuGGhm6TQ7KVFdZEooMwpe3yoHEv5reoYmUl0nrWObDau2KTbwlpD2r2LYxOZHk4uu1Oo7fDfZzPZlf6hTWdQJpt3QWWIKsIjvMOZz2q64JVR9FBD0DNsMLPsalhvoPT+UibFUOZXJtk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ucbNnild; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ucbNnild" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CB782C16AAE; Wed, 28 Jan 2026 20:28:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632092; bh=/31EreH53ZbfLgFROUgaazBzJSVsVuqJTT5oOs7SCjM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ucbNnildD1YQ95dVxpJ2kkQXeMWx+bA6Mc2FsARgFcVczjwggyqCOcgGWKsjXfec0 51D6f5QPatAMeAu9Vw6HX+6MRLWkyyK6yzpjQQlivsYVrTrYieeOmAAYjkYpC6njYK K7NE0shSt3timYgnt9sBnvphGh2hQP16PqKuqTDkVV3H2wkYDF5c/dL9sHxeiHygKF 6QL+fgFZpGiBtC1RH0UUPAzxFv/9qe2Nje7LN9WU+3iv6g+cZCTL5ZvPakAArH+9Lp 9GlN8ysBJm1zNmO5ChhjFmzSnxiSs0gdkJhnT9j7aw0P+nGRKD/uKtDX9+BI2hS/q1 dAoFoM2VcjExQ== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:37 -0800 Subject: [PATCH RFC v2 16/17] acpi: riscv: Parse RISC-V Quality of Service Controller (RQSC) table Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-16-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5705; i=fustini@kernel.org; h=from:subject:message-id; bh=/31EreH53ZbfLgFROUgaazBzJSVsVuqJTT5oOs7SCjM=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQZGmc3dXWH840Dfap/on9x8wdaVnnOLfHdbrlfoZ HF8f8W3o5SFQYyLQVZMkWXTh7wLS7xCvy6Y/2IbzBxWJpAhDFycAjCRfdsZGf7cnRk68dAd/agJ ifslzvismBv8apVhxuS3PauDbFtSvs9mZOgQt1u7wGulryvHyoVrpmtsZF2jVzO1cZL8hI91bI+ mqnABAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add driver to parse the ACPI RISC-V Quality of Service Controller (RQSC) table which describes the capacity and bandwidth QoS controllers in a system. The QoS controllers implement the RISC-V Capacity and Bandwidth Controller QoS Register Interface (CBQRI) specification. Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 Link: https://github.com/riscv-non-isa/riscv-rqsc/blob/main/src/ Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + arch/riscv/include/asm/acpi.h | 10 ++++ drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/rqsc.c | 112 ++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 124 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 96ead357a634..e96a83dc9a02 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22512,6 +22512,7 @@ S: Supported F: arch/riscv/include/asm/qos.h F: arch/riscv/include/asm/resctrl.h F: arch/riscv/kernel/qos/ +F: drivers/acpi/riscv/rqsc.c F: include/linux/riscv_qos.h =20 RISC-V RPMI AND MPXY DRIVERS diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 6e13695120bc..16c6e25eed1e 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -71,6 +71,16 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, =20 void acpi_get_cbo_block_size(struct acpi_table_header *table, u32 *cbom_si= ze, u32 *cboz_size, u32 *cbop_size); + +#ifdef CONFIG_RISCV_ISA_SSQOSID +int acpi_parse_rqsc(struct acpi_table_header *table); +#else +static inline int acpi_parse_rqsc(struct acpi_table_header *table) +{ + return -EINVAL; +} +#endif /* CONFIG_RISCV_ISA_SSQOSID */ + #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 1284a076fa88..cf0f38c93a9f 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y +=3D rhct.o init.o irq.o +obj-y +=3D rhct.o rqsc.o init.o irq.o obj-$(CONFIG_ACPI_PROCESSOR_IDLE) +=3D cpuidle.o obj-$(CONFIG_ACPI_CPPC_LIB) +=3D cppc.o obj-$(CONFIG_ACPI_RIMT) +=3D rimt.o diff --git a/drivers/acpi/riscv/rqsc.c b/drivers/acpi/riscv/rqsc.c new file mode 100644 index 000000000000..a86ddb39fae4 --- /dev/null +++ b/drivers/acpi/riscv/rqsc.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Tenstorrent + * Author: Drew Fustini + * + */ + +#define pr_fmt(fmt) "ACPI: RQSC: " fmt + +#include +#include +#include + +#ifdef CONFIG_RISCV_ISA_SSQOSID + +#define CBQRI_CTRL_SIZE 0x1000 + +static struct acpi_table_rqsc *acpi_get_rqsc(void) +{ + static struct acpi_table_header *rqsc; + acpi_status status; + + /* + * RQSC will be used at runtime on every CPU, so we + * don't need to call acpi_put_table() to release the table mapping. + */ + if (!rqsc) { + status =3D acpi_get_table(ACPI_SIG_RQSC, 0, &rqsc); + if (ACPI_FAILURE(status)) { + pr_warn_once("No RQSC table found\n"); + return NULL; + } + } + + return (struct acpi_table_rqsc *)rqsc; +} + +int acpi_parse_rqsc(struct acpi_table_header *table) +{ + struct acpi_table_rqsc *rqsc; + int err; + + BUG_ON(acpi_disabled); + if (!table) { + rqsc =3D acpi_get_rqsc(); + if (!rqsc) + return -ENOENT; + } else { + rqsc =3D (struct acpi_table_rqsc *)table; + } + + for (int i =3D 0; i < rqsc->num; i++) { + struct cbqri_controller_info *ctrl_info; + + ctrl_info =3D kzalloc(sizeof(*ctrl_info), GFP_KERNEL); + if (!ctrl_info) + return -ENOMEM; + + ctrl_info->type =3D rqsc->f[i].type; + ctrl_info->addr =3D rqsc->f[i].reg[1]; + ctrl_info->size =3D CBQRI_CTRL_SIZE; + ctrl_info->rcid_count =3D rqsc->f[i].rcid; + ctrl_info->mcid_count =3D rqsc->f[i].mcid; + + pr_info("Found controller with type %u addr 0x%lx size %lu rcid %u mci= d %u", + ctrl_info->type, ctrl_info->addr, ctrl_info->size, + ctrl_info->rcid_count, ctrl_info->mcid_count); + + if (ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY) { + ctrl_info->cache.cache_id =3D rqsc->f[i].res.id1; + ctrl_info->cache.cache_level =3D + find_acpi_cache_level_from_id(ctrl_info->cache.cache_id); + + struct acpi_pptt_cache *cache; + + cache =3D find_acpi_cache_from_id(ctrl_info->cache.cache_id); + if (cache) { + ctrl_info->cache.cache_size =3D cache->size; + } else { + pr_warn("%s(): failed to determine size for cache id 0x%x", + __func__, ctrl_info->cache.cache_id); + ctrl_info->cache.cache_size =3D 0; + } + + pr_info("Cache controller has ID 0x%x level %u size %u ", + ctrl_info->cache.cache_id, ctrl_info->cache.cache_level, + ctrl_info->cache.cache_size); + + /* + * For CBQRI, any cpu (technically a hart in RISC-V terms) + * can access the memory-mapped registers of any CBQRI + * controller in the system. + */ + err =3D cpumask_parse("FF", &ctrl_info->cache.cpu_mask); + if (err) + pr_err("Failed to convert cores mask string to cpumask (%d)", err); + + } else if (ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_BANDWIDTH) { + ctrl_info->mem.prox_dom =3D rqsc->f[i].res.id1; + pr_info("Memory controller with proximity domain %u", + ctrl_info->mem.prox_dom); + } + + /* Fill the list shared with RISC-V QoS resctrl */ + INIT_LIST_HEAD(&ctrl_info->list); + list_add_tail(&ctrl_info->list, &cbqri_controllers); + } + + return 0; +} + +#endif /* CONFIG_RISCV_ISA_SSQOSID */ --=20 2.43.0