From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D607337688; Wed, 28 Jan 2026 20:28:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632083; cv=none; b=hRCfFsbB66LQ6lR0QtX5WlKKfQFJ+vCKqWA517Cm6Zn2NOIIxaa+R4B+PlUsv97No1AFzrjl/XHokr4gOPOdZgr01LkOYzwSOMSaBZjuVcBD1pXLl+jvnb4rdJ93VL3Ar7H+0nyAxZMAXbzyLVPe7iUJ/hp68eL/xzcNRpJ1yLA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632083; c=relaxed/simple; bh=iU4P/QyFDo51iNRXh33LwyQncDIl37ClLj6x8G/smfI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RVoxPlWlB0uXhltjA+D47odu4JPwi3KyL/bea0TxedetTHlCmP8ISLN9jiFv+YOsXeaohd6WbpvdFApSFo8wr7fj3/gBNOZYgZJNwsxzKKii56nsfj/pfetx2rZw23aHeyieUxyAue/t+NzT9byCv/j8vYG7Hhwh3iNzFqeJ/gY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lmTmP1J+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lmTmP1J+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0472EC2BC9E; Wed, 28 Jan 2026 20:28:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632083; bh=iU4P/QyFDo51iNRXh33LwyQncDIl37ClLj6x8G/smfI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lmTmP1J+Qghc05Nqc5cuJVnSgKJfS/c5eJF7LeB5R271apI5myUekh302dfbDgCgN wx+sDKAT57yvi1HnUvqWhNOCDbj2SCV5EUegmE/sDE++rEAZyXqy/BCBUbvX7vse7q cJ4abyQlrOnkTmmRSdyYptIopsnsZpq+POLi2X4YmB08d4JB9wHhDqAc2jAvl6+GYY TNgv1oPjxFgfwp0vm7PLyrh71UTJXNSXfKC9lJyLpk0M+dfhUIyeM4f2+bVEvYyhh2 bbv4tz9DF5egQtGnkPc5S6BFFvq4aMGKdl87/9yZEr+6JjKuqn7Gl3K8VRyALJpb7y 2miCt+A7iqigA== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:22 -0800 Subject: [PATCH RFC v2 01/17] dt-bindings: riscv: Add Ssqosid extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-1-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org, Conor Dooley X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1214; i=fustini@kernel.org; h=from:subject:message-id; bh=iU4P/QyFDo51iNRXh33LwyQncDIl37ClLj6x8G/smfI=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFfpPVLT64/lPNeKa8oEgmen1mrtmnF3btkdEM+bZT 5cEdc3lHaUsDGJcDLJiiiybPuRdWOIV+nXB/BfbYOawMoEMYeDiFICJTGpj+MV0pWRf986zx0Nu VR9/VLFUSuTSrUS/NeX6ryTPbYy7On0hI0Pj4tWnbWpmT5SIMqmyux6dJueim/9hsViYYOaG5Z0 6FmwA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Document the ratified Supervisor-mode Quality of Service ID (Ssqosid) extension v1.0. Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0 Acked-by: Conor Dooley Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 5bab356addc8..27a7b4e63eb1 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -165,6 +165,12 @@ properties: ratified at commit d70011dde6c2 ("Update to ratified state") of riscv-j-extension. =20 + - const: ssqosid + description: | + The Ssqosid extension for Quality of Service ID is ratified + as v1.0 in commit 5059e0ca641c ("Merge pull request #7 from + ved-rivos/Ratified") of riscv-ssqosid. + - const: sstc description: | The standard Sstc supervisor-level extension for time compare = as --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C82B336ECA; Wed, 28 Jan 2026 20:28:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632084; cv=none; b=fWjYunNCJjlDzqWR4PZalwJU2HnpVCpQqLE2iNasqgxM2uC5Wi9qIsD16SuS8f7ROmCoN05BQBKewkulIkftCOX1AWFbut8IWCF1WySwsNK+tmXzPs1874Zlh+7Y0TweX3tD/N56WbkxmvcNAaETkQRyjifrbwIYZbcw3hrRVUo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632084; c=relaxed/simple; bh=fj8k7O5ZHAbvxYPSXABfgdwCx96nHjY6bA9gTqNje0o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GkgShrBr5j0eS5ylCkLICGCQi9mQiWoZbeYXM4LrHujKKCOEzReewyR1Y7e7CjIpao2Btk6Uo7ktcUlmRgRSqQc94ByziNU4lOTbke5fPy9tzzAtSafhD/Ct1bmetGfVu0+Nz3dz3D3rDwDBATOe/boFC/DmQqTxEgLHg+CcCt8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lnEr3FIf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lnEr3FIf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9AE4BC4CEF7; Wed, 28 Jan 2026 20:28:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632084; bh=fj8k7O5ZHAbvxYPSXABfgdwCx96nHjY6bA9gTqNje0o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lnEr3FIfCsXlF/AQZanvEtVWCn/JltE3MGIvF9w4D4ayIgdylOAJhvTtuvl1r1IOB CdyhNLl88Girdfnj8BXm+NdMj0JPjYlXE6ocKtxhT0Hx+L7zfz0zRGyWi80zX6gbz4 OgmsOZIyMFTBYWi8TBTV18am6n2i77N7/fvZnMmoPzhIf7Z6o8hR2wvYORIFj6je/I myCicl/CY+6IKLZOWpOQ2HlBJ9WJQS8l1NRyVqqcsEQpi6qCXQx4+5ogUY8gGbrzsb L0Rozibjfll3jBe4vQq+vImqDRbzfkYQOQHe6+sAc6wcTdyyO7fuW+TnwSOTm2Ixub hSEzvjmQ9jBTA== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:23 -0800 Subject: [PATCH RFC v2 02/17] RISC-V: Detect the Ssqosid extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-2-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1618; i=fustini@kernel.org; h=from:subject:message-id; bh=fj8k7O5ZHAbvxYPSXABfgdwCx96nHjY6bA9gTqNje0o=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFfobF4qs9Wp5vWb6ury3XytXTFYXU1Wo2C3hnDqzY am63YaVHaUsDGJcDLJiiiybPuRdWOIV+nXB/BfbYOawMoEMYeDiFICJxK9g+B/N/WVx2Je9++5/ WsS0Vmez1XzV4xMTbjRtSGSqkmVr2/uZkeFxsmrwLb+j0f+PTpqiwF/yd31fX6vOQYXj3Hrv2zM FlzEAAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Ssqosid is the RISC-V Quality-of-Service (QoS) Identifiers specification which defines the Supervisor Resource Management Configuration (srmcfg) register. Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0 Signed-off-by: Kornel Dul=C4=99ba [fustini: rebase on current upstream] Signed-off-by: Drew Fustini --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 4369a2338541..28dff8233b34 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -110,6 +110,7 @@ #define RISCV_ISA_EXT_ZALASR 101 #define RISCV_ISA_EXT_ZILSD 102 #define RISCV_ISA_EXT_ZCLSD 103 +#define RISCV_ISA_EXT_SSQOSID 104 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c05b11596c19..bf704b48679c 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -558,6 +558,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_e= xts), + __RISCV_ISA_EXT_DATA(ssqosid, RISCV_ISA_EXT_SSQOSID), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), __RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu= _validate), --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA894374734; Wed, 28 Jan 2026 20:28:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632084; cv=none; b=CNAkxsnqzBiRnPO4GT+52XgFXM/kwGUJ4CNS6dv/iK09zsdkdQi4CrFrKJfkE9BOfpz4K6s0JLpsu2fDkVHPGWzph1gOlvjAB7jZCQS9T7/gEC98zUnlr8mi/6BKStRiE9Owh7SJsEHp2oGZFNkDuSU2YLLdVACMQ/9ceiah3CI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632084; c=relaxed/simple; bh=brCvnWFV/0XpvuigvCVeTSEbQ9WZIuSfsqfRCiA/hck=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BDYgYzTQlnsnoo2W5FmpaZhvCGBJi0KjZ5pTvEIsJKsWJJBVBnWHf7CXOZZU/IBNiUCrFV7d+MubC+2wbj6J8FfsTCjobYhAM9tp2TLfwy2D/9ovclQDeQXHHu6Tqtws6lh/BTw8ZGSUY/c25gzeeLz8FPrnVXLRTOqlzi6pVQ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ib3iqgLT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ib3iqgLT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 409D6C19421; Wed, 28 Jan 2026 20:28:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632084; bh=brCvnWFV/0XpvuigvCVeTSEbQ9WZIuSfsqfRCiA/hck=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ib3iqgLT3bxP9DgDkA7X2XUKCP08yrLWsUW3voJLaaV/d8nP5IzUZsPTiapq4pOgX 7CgUmgu2ncbA1zP/zM9suKAv9bp1+m5ZuV06kyZpVIKN2ItLKXqZOUbsThCpt0+kLx /0W11UykoVELte/kD/g0zGhPYfli6s4A9EuvaFjSmVd/nr5wbF0aR6SbIRxGo2IqVB UNYirsgMehgTlvH4zECAR1P2A7hYVxKHjJCENFBCYGAeL5M8/TVewtGyQUvAbzoErn NqnYyVJVykdsf2iINkyv5QY5H2LrQEsXhENZt0XXHE+BMY6ixRlz1jfED0uGeMmXy7 uO4+RbDKuDZmA== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:24 -0800 Subject: [PATCH RFC v2 03/17] RISC-V: Add support for srmcfg CSR from Ssqosid ext Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-3-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7818; i=fustini@kernel.org; h=from:subject:message-id; bh=brCvnWFV/0XpvuigvCVeTSEbQ9WZIuSfsqfRCiA/hck=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFfpf4o9ulhNeO0n0A7f+dt7rHWcqU2zOCWo3vT8oM ntB49GFHaUsDGJcDLJiiiybPuRdWOIV+nXB/BfbYOawMoEMYeDiFICJdK5i+B/NXMU3uWbR678q +2T3OUfkdYTwB76IPHL+2RIXURvbBd8ZGd58jWsIESn65vPY6u30wirBreLBjTO7uWf3fmuM/Xh rBTsA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add support for the srmcfg CSR defined in the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). The CSR contains two fields: - Resource Control ID (RCID) used determine resource allocation - Monitoring Counter ID (MCID) used to track resource usage Requests from a hart to shared resources like cache will be tagged with these IDs. This allows the usage of shared resources to be associated with the task currently running on the hart. A srmcfg field is added to thread_struct and has the same format as the srmcfg CSR. This allows the scheduler to set the hart's srmcfg CSR to contain the RCID and MCID for the task that is being scheduled in. The srmcfg CSR is only written to if the thread_struct.srmcfg is different than the current value of the CSR. A per-cpu variable cpu_srmcfg is used to mirror that state of the CSR. This is because access to L1D hot memory should be several times faster than a CSR read. Also, in the case of virtualization, accesses to this CSR are trapped in the hypervisor. Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0 Co-developed-by: Kornel Dul=C4=99ba Signed-off-by: Kornel Dul=C4=99ba [fustini: rename csr, refactor switch_to, rebase on upstream] Signed-off-by: Drew Fustini --- MAINTAINERS | 7 +++++++ arch/riscv/Kconfig | 17 ++++++++++++++++ arch/riscv/include/asm/csr.h | 8 ++++++++ arch/riscv/include/asm/processor.h | 3 +++ arch/riscv/include/asm/qos.h | 41 ++++++++++++++++++++++++++++++++++= ++++ arch/riscv/include/asm/switch_to.h | 3 +++ arch/riscv/kernel/Makefile | 2 ++ arch/riscv/kernel/qos/Makefile | 2 ++ arch/riscv/kernel/qos/qos.c | 5 +++++ 9 files changed, 88 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 765ad2daa218..e98d553bd0ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22505,6 +22505,13 @@ F: drivers/perf/riscv_pmu.c F: drivers/perf/riscv_pmu_legacy.c F: drivers/perf/riscv_pmu_sbi.c =20 +RISC-V QOS RESCTRL SUPPORT +M: Drew Fustini +L: linux-riscv@lists.infradead.org +S: Supported +F: arch/riscv/include/asm/qos.h +F: arch/riscv/kernel/qos/ + RISC-V RPMI AND MPXY DRIVERS M: Rahul Pathak M: Anup Patel diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6b39f37f769a..35a6238b02c5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -595,6 +595,23 @@ config RISCV_ISA_SVNAPOT =20 If you don't know what to do here, say Y. =20 +config RISCV_ISA_SSQOSID + bool "Ssqosid extension support for supervisor mode Quality of Service ID" + default y + help + Adds support for the Ssqosid ISA extension (Supervisor-mode + Quality of Service ID). + + Ssqosid defines the srmcfg CSR which allows the system to tag the + running process with an RCID (Resource Control ID) and MCID + (Monitoring Counter ID). The RCID is used to determine resource + allocation. The MCID is used to track resource usage in event + counters. + + For example, a cache controller may use the RCID to apply a + cache partitioning scheme and use the MCID to track how much + cache a process, or a group of processes, is using. + config RISCV_ISA_SVPBMT bool "Svpbmt extension support for supervisor mode page-based memory type= s" depends on 64BIT && MMU diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 4a37a98398ad..2590b89b8f72 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -75,6 +75,13 @@ #define SATP_ASID_MASK _AC(0xFFFF, UL) #endif =20 +/* SRMCFG fields */ +#define SRMCFG_RCID_MASK _AC(0x00000FFF, UL) +#define SRMCFG_MCID_MASK SRMCFG_RCID_MASK +#define SRMCFG_MCID_SHIFT 16 +#define SRMCFG_MASK ((SRMCFG_MCID_MASK << SRMCFG_MCID_SHIFT) | \ + SRMCFG_RCID_MASK) + /* Exception cause high bit - is an interrupt if set */ #define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) =20 @@ -317,6 +324,7 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 #define CSR_SATP 0x180 +#define CSR_SRMCFG 0x181 =20 #define CSR_STIMECMP 0x14D #define CSR_STIMECMPH 0x15D diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index da5426122d28..183c55e32b96 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -122,6 +122,9 @@ struct thread_struct { /* A forced icache flush is not needed if migrating to the previous cpu. = */ unsigned int prev_cpu; #endif +#ifdef CONFIG_RISCV_ISA_SSQOSID + u32 srmcfg; +#endif }; =20 /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/asm/qos.h b/arch/riscv/include/asm/qos.h new file mode 100644 index 000000000000..84830d7c6dc4 --- /dev/null +++ b/arch/riscv/include/asm/qos.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_RISCV_QOS_H +#define _ASM_RISCV_QOS_H + +#ifdef CONFIG_RISCV_ISA_SSQOSID + +#include +#include + +#include +#include +#include + +/* cached value of srmcfg csr for each cpu */ +DECLARE_PER_CPU(u32, cpu_srmcfg); + +static inline void __switch_to_srmcfg(struct task_struct *next) +{ + u32 *cpu_srmcfg_ptr =3D this_cpu_ptr(&cpu_srmcfg); + u32 thread_srmcfg; + + thread_srmcfg =3D READ_ONCE(next->thread.srmcfg); + + if (thread_srmcfg !=3D *cpu_srmcfg_ptr) { + *cpu_srmcfg_ptr =3D thread_srmcfg; + csr_write(CSR_SRMCFG, thread_srmcfg); + } +} + +static __always_inline bool has_srmcfg(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SSQOSID); +} + +#else /* ! CONFIG_RISCV_ISA_SSQOSID */ + +static __always_inline bool has_srmcfg(void) { return false; } +#define __switch_to_srmcfg(__next) do { } while (0) + +#endif /* CONFIG_RISCV_ISA_SSQOSID */ +#endif /* _ASM_RISCV_QOS_H */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 0e71eb82f920..a684a3795d3d 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -14,6 +14,7 @@ #include #include #include +#include =20 #ifdef CONFIG_FPU extern void __fstate_save(struct task_struct *save_to); @@ -119,6 +120,8 @@ do { \ __switch_to_fpu(__prev, __next); \ if (has_vector() || has_xtheadvector()) \ __switch_to_vector(__prev, __next); \ + if (has_srmcfg()) \ + __switch_to_srmcfg(__next); \ if (switch_to_should_flush_icache(__next)) \ local_flush_icache_all(); \ __switch_to_envcfg(__next); \ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index f60fce69b725..a3c36d18145c 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -125,3 +125,5 @@ obj-$(CONFIG_ACPI) +=3D acpi.o obj-$(CONFIG_ACPI_NUMA) +=3D acpi_numa.o =20 obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) +=3D bugs.o + +obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos/ diff --git a/arch/riscv/kernel/qos/Makefile b/arch/riscv/kernel/qos/Makefile new file mode 100644 index 000000000000..9f996263a86d --- /dev/null +++ b/arch/riscv/kernel/qos/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos.o diff --git a/arch/riscv/kernel/qos/qos.c b/arch/riscv/kernel/qos/qos.c new file mode 100644 index 000000000000..7b06f7ae9056 --- /dev/null +++ b/arch/riscv/kernel/qos/qos.c @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include + +/* cached value of sqoscfg csr for each cpu */ +DEFINE_PER_CPU(u32, cpu_srmcfg); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-4-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1881; i=fustini@kernel.org; h=from:subject:message-id; bh=e1gD37k8W4Pzp7U55pR9/mebQe/hwn2pjhUSiquHa+s=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFfo/PsmQs8/5uN0n4RmuNZbNnaqKh08JWp8PniEvI bZA5vf0jlIWBjEuBlkxRZZNH/IuLPEK/bpg/ottMHNYmUCGMHBxCsBEplxlZLhUc3PVNvcCloD3 kWI1zKbTl3BYzC5zeF0/S6nPd/bORDOGv7KKuyXYZZdlXPyvsccx8XE9U12Qqvt2Y92ekIhmPZU nHAA= X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Define data structure to represent the CBQRI properties that a driver for an CBQRI-capable controller would discover during probe. Each instance of a CBQRI-capable controller is added to a list that the RISC-V CBQRI resctrl implementation will consume. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + include/linux/riscv_qos.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e98d553bd0ca..31e536304972 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22511,6 +22511,7 @@ L: linux-riscv@lists.infradead.org S: Supported F: arch/riscv/include/asm/qos.h F: arch/riscv/kernel/qos/ +F: include/linux/riscv_qos.h =20 RISC-V RPMI AND MPXY DRIVERS M: Rahul Pathak diff --git a/include/linux/riscv_qos.h b/include/linux/riscv_qos.h new file mode 100644 index 000000000000..51c3a96bbcd0 --- /dev/null +++ b/include/linux/riscv_qos.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __LINUX_RISCV_QOS_H +#define __LINUX_RISCV_QOS_H + +#include +#include + +#include + +enum cbqri_controller_type { + CBQRI_CONTROLLER_TYPE_CAPACITY, + CBQRI_CONTROLLER_TYPE_BANDWIDTH, + CBQRI_CONTROLLER_TYPE_UNKNOWN +}; + +struct cbqri_controller_info { + unsigned long addr; + unsigned long size; + enum cbqri_controller_type type; + u32 rcid_count; + u32 mcid_count; + struct list_head list; + + struct cache_controller { + u32 cache_level; + u32 cache_size; /* in bytes */ + struct cpumask cpu_mask; + } cache; +}; + +extern struct list_head cbqri_controllers; + +#endif /* __LINUX_RISCV_QOS_H */ --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1570937647B; Wed, 28 Jan 2026 20:28:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632086; cv=none; b=WRi8ovSR/d6yuae07n7l/2/gzpo489LiKwYyfVK7QKMHb4OCqYeojstfFLLSQAbZYpLZxOXU9ntPV7EIjU9DXdWYSA3rDn79xsGqjSBTQ1wZsKM+DaRipKlfR/bz70/7hVQhnxS1+aWnOnLus6s0vKdHoikPWvk9pXCHPvm3DRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632086; c=relaxed/simple; bh=uuacy5TWBWCqGEovDfg1uYj/N0C7aRhzBOjqrPUPGZE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fqAMv1t/paPAEbPAzwV+16QBzYGwaa/tNiPGZ9LanoT+p5srNozK79mRS5up/Pi3AbEF80ZoEOYZHOtxNsQV7IEe4Ix+PhSzOit39BV5ZNsnIpVtdYWC7XxSj1MDavJt3dydyKgy5+Q9JlfkhsmTm3pa78txxRo2v8cGJnNxT2Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cuu7ZLVJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cuu7ZLVJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 68251C4CEF7; Wed, 28 Jan 2026 20:28:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632085; bh=uuacy5TWBWCqGEovDfg1uYj/N0C7aRhzBOjqrPUPGZE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=cuu7ZLVJx0gAzesWP4IDGrHlRXyqQrUU3YixYnv3MC5zLnNPDIxy56Z3WUd+GYJGZ 37bW/dN8Hg8BLsvrPtvuV+qeA8VYNQtI23k3Nb8AB1VA4DTDuptQU8GKXi+laiKnoE rY07evMIMWYNs0oEL+s+DB7p+FHW7Jwl9k6evZvlAajvMFiiN6wWQgzs2H+ePBIhVU ck2JSWcWrcw89q+4jI9q0QC8sdCZ7VPHtAb2prmwASOoTQXPQ8DyyQnVQP6WIBFVwM g3RhVeKqNfC5aAi8d6/2r/iTMc8SvtCsj37uO2m8T8zZl/oMEfladXnfg5/ecKC2C2 KqVHJqVoum1DQ== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:26 -0800 Subject: [PATCH RFC v2 05/17] RISC-V: QoS: define CBQRI capacity and bandwidth capabilities Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-5-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4712; i=fustini@kernel.org; h=from:subject:message-id; bh=uuacy5TWBWCqGEovDfg1uYj/N0C7aRhzBOjqrPUPGZE=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQYobQy54nbak+F10tT+lae+cUrN6c4t9FE60iv55 9jzZVvnd5SyMIhxMciKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAmEvCfkeGV0Z0j3a9ZmpQP na3VkK95pWS9f2Z6lm3MmZSS8mnWmQsY/nvsX7vaQzvSYWMWXw3nwwc94hMmfomZyzK3ctPkvYf PyrIAAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Define data structures to store the capacity and bandwidth capabilities that are discovered for a CBQRI-capable controller. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/internal.h | 128 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 128 insertions(+) diff --git a/arch/riscv/kernel/qos/internal.h b/arch/riscv/kernel/qos/inter= nal.h new file mode 100644 index 000000000000..ff2c7eff50be --- /dev/null +++ b/arch/riscv/kernel/qos/internal.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_RISCV_QOS_INTERNAL_H +#define _ASM_RISCV_QOS_INTERNAL_H + +#include + +#define CBQRI_CC_CAPABILITIES_OFF 0 +#define CBQRI_CC_MON_CTL_OFF 8 +#define CBQRI_CC_MON_CTL_VAL_OFF 16 +#define CBQRI_CC_ALLOC_CTL_OFF 24 +#define CBQRI_CC_BLOCK_MASK_OFF 32 + +#define CBQRI_BC_CAPABILITIES_OFF 0 +#define CBQRI_BC_MON_CTL_OFF 8 +#define CBQRI_BC_MON_CTR_VAL_OFF 16 +#define CBQRI_BC_ALLOC_CTL_OFF 24 +#define CBQRI_BC_BW_ALLOC_OFF 32 + +#define CBQRI_CC_CAPABILITIES_VER_MINOR_MASK GENMASK(3, 0) +#define CBQRI_CC_CAPABILITIES_VER_MAJOR_MASK GENMASK(7, 4) + +#define CBQRI_CC_CAPABILITIES_FRCID_MASK 0x1 +#define CBQRI_CC_CAPABILITIES_FRCID_SHIFT 24 + +#define CBQRI_CC_CAPABILITIES_NCBLKS_SHIFT 8 +#define CBQRI_CC_CAPABILITIES_NCBLKS_MASK 0xFFFF + +#define CBQRI_BC_CAPABILITIES_VER_MINOR_MASK GENMASK(3, 0) +#define CBQRI_BC_CAPABILITIES_VER_MAJOR_MASK GENMASK(7, 4) + +#define CBQRI_BC_CAPABILITIES_NBWBLKS_SHIFT 8 +#define CBQRI_BC_CAPABILITIES_NBWBLKS_MASK 0xFFFF +#define CBQRI_BC_CAPABILITIES_MRBWB_SHIFT 32 +#define CBQRI_BC_CAPABILITIES_MRBWB_MASK 0xFFFF + +#define CBQRI_CONTROL_REGISTERS_BUSY_SHIFT 39 +#define CBQRI_CONTROL_REGISTERS_BUSY_MASK 0x01 +#define CBQRI_CONTROL_REGISTERS_STATUS_SHIFT 32 +#define CBQRI_CONTROL_REGISTERS_STATUS_MASK 0x7F +#define CBQRI_CONTROL_REGISTERS_OP_SHIFT 0 +#define CBQRI_CONTROL_REGISTERS_OP_MASK 0x1F +#define CBQRI_CONTROL_REGISTERS_AT_SHIFT 5 +#define CBQRI_CONTROL_REGISTERS_AT_MASK 0x07 +#define CBQRI_CONTROL_REGISTERS_AT_DATA 0 +#define CBQRI_CONTROL_REGISTERS_AT_CODE 1 +#define CBQRI_CONTROL_REGISTERS_RCID_SHIFT 8 +#define CBQRI_CONTROL_REGISTERS_RCID_MASK 0xFFF +#define CBQRI_CONTROL_REGISTERS_RBWB_SHIFT 0 +#define CBQRI_CONTROL_REGISTERS_RBWB_MASK 0xFFFF + +#define CBQRI_CC_MON_CTL_OP_CONFIG_EVENT 1 +#define CBQRI_CC_MON_CTL_OP_READ_COUNTER 2 +#define CBQRI_CC_MON_CTL_STATUS_SUCCESS 1 + +#define CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT 1 +#define CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT 2 +#define CBQRI_CC_ALLOC_CTL_OP_FLUSH_RCID 3 +#define CBQRI_CC_ALLOC_CTL_STATUS_SUCCESS 1 + +#define CBQRI_BC_MON_CTL_OP_CONFIG_EVENT 1 +#define CBQRI_BC_MON_CTL_OP_READ_COUNTER 2 +#define CBQRI_BC_MON_CTL_STATUS_SUCCESS 1 + +#define CBQRI_BC_ALLOC_CTL_OP_CONFIG_LIMIT 1 +#define CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT 2 +#define CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS 1 + +/* Capacity Controller hardware capabilities */ +struct riscv_cbqri_capacity_caps { + u16 ncblks; /* number of capacity blocks */ + u16 cache_level; + u32 blk_size; + + bool supports_alloc_at_data; + bool supports_alloc_at_code; + + bool supports_alloc_op_config_limit; + bool supports_alloc_op_read_limit; + bool supports_alloc_op_flush_rcid; + + bool supports_mon_at_data; + bool supports_mon_at_code; + + bool supports_mon_op_config_event; + bool supports_mon_op_read_counter; + + bool supports_mon_evt_id_none; + bool supports_mon_evt_id_occupancy; +}; + +/* Bandwidth Controller hardware capabilities */ +struct riscv_cbqri_bandwidth_caps { + u16 nbwblks; /* number of bandwidth blocks */ + u16 mrbwb; /* max reserved bw blocks */ + + bool supports_alloc_at_data; + bool supports_alloc_at_code; + + bool supports_alloc_op_config_limit; + bool supports_alloc_op_read_limit; + + bool supports_mon_at_data; + bool supports_mon_at_code; + + bool supports_mon_op_config_event; + bool supports_mon_op_read_counter; + + bool supports_mon_evt_id_none; + bool supports_mon_evt_id_rdwr_count; + bool supports_mon_evt_id_rdonly_count; + bool supports_mon_evt_id_wronly_count; +}; + +struct cbqri_controller { + struct cbqri_controller_info *ctrl_info; + void __iomem *base; + + int ver_major; + int ver_minor; + + struct riscv_cbqri_bandwidth_caps bc; + struct riscv_cbqri_capacity_caps cc; + + bool alloc_capable; + bool mon_capable; +}; + +#endif /* _ASM_RISCV_QOS_INTERNAL_H */ --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8B6E374187; Wed, 28 Jan 2026 20:28:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632086; cv=none; b=MR+Nh60g5xb8OF/6ebpq7yDidT+PwZYRJ/w4RbnKHyHNbLBykA3hql3CYZCvyXB/0LlglqWUaMg7XCHsNP2ohje8HGGz4IE00g0NlAHT2bPaJz8YpAZm5ayMoDYcE5N1nn9n+fz1vax8XLwpOtHzXGJhOhEOcVMDRvMrwDujK3U= ARC-Message-Signature: i=1; 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b=QyoMgQ1PlpsL25i4MmYfj4pTfftDnw7v3FsxFrm0jEker86I3vX4LLM3Vfp5/3oX2 0CNeldeXnjcgDuhembANRxNc0zAi7xPH2f7N0zKk9Ql/qiff+RbvLIyJspncWrBJO6 gSg1zmnP5UtM7ZF2EVg5Bw3fmIeQZZSpqWOcst/dkdR32o/2GF72e7Z3VR6xOjowhI X4SNGkZm/4G4g0pf9+V7X0VNFnul2tCcpiK7MwzdyfGDpNYwnSNAle1sxZ3UL/qCGJ MPtURsWZmNvZY7R0JKskU0HYVIUF+LxDzIU+i3GXfI39kDlCd0Ue6jqQ5jtJxFC9YJ gFTNMoLDM+uyA== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:27 -0800 Subject: [PATCH RFC v2 06/17] RISC-V: QoS: define CBQRI resctrl resources and domains Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-6-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1671; i=fustini@kernel.org; h=from:subject:message-id; bh=nRtrIHSuWEDHEeDXLCrpmYAAH9Hp3uZpgjylkcnSlpU=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQZcWOafc1mIUyQrfPft57MCLq6xf8c35WlDxxZ/h trtfz886ShlYRDjYpAVU2TZ9CHvwhKv0K8L5r/YBjOHlQlkCAMXpwBMZFsMw2+2eX9Mbvuknzs9 +9bmf3fmG1k9iFq368zirCNn7MIYrle0MTIszUg6Kj236ZH6fPNX17YwnmDmXZb4seOg0E0T+23 drwOZAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Define data structures to encapsulate the resctrl resource and domain structures. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi [fustini: rebased current upstream] Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/internal.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/riscv/kernel/qos/internal.h b/arch/riscv/kernel/qos/inter= nal.h index ff2c7eff50be..c0402dd06cfa 100644 --- a/arch/riscv/kernel/qos/internal.h +++ b/arch/riscv/kernel/qos/internal.h @@ -65,6 +65,11 @@ #define CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT 2 #define CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS 1 =20 +int qos_resctrl_setup(void); +void qos_resctrl_exit(void); +int qos_resctrl_online_cpu(unsigned int cpu); +int qos_resctrl_offline_cpu(unsigned int cpu); + /* Capacity Controller hardware capabilities */ struct riscv_cbqri_capacity_caps { u16 ncblks; /* number of capacity blocks */ @@ -125,4 +130,26 @@ struct cbqri_controller { bool mon_capable; }; =20 +struct cbqri_resctrl_res { + struct rdt_resource resctrl_res; + struct cbqri_controller controller; + u32 max_rcid; + u32 max_mcid; +}; + +struct cbqri_resctrl_dom { + struct rdt_domain_hdr resctrl_dom_hdr; + struct rdt_ctrl_domain resctrl_ctrl_dom; + struct rdt_mon_domain resctrl_mon_dom; + u64 cbm; + u64 rbwb; + u64 *ctrl_val; + struct cbqri_controller *hw_ctrl; +}; + +struct cbqri_config { + u64 cbm; /* capacity block mask */ + u64 rbwb; /* reserved bandwidth blocks */ +}; + #endif /* _ASM_RISCV_QOS_INTERNAL_H */ --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42C9C376BC8; Wed, 28 Jan 2026 20:28:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632087; cv=none; b=jXDAhzbBD24TAWGq+pMDzUNq0/JKggNZE5/m+iVFEw32Dr48BMpoUDOwvTr4PQ7OveJ8ECTLlaE2OTQtcG/kT41sQ0x3o73vUkvkZe49W7PAokeTKnVIZZjNXDpSzQ4HUyfj8whGnk0xeagWKm1IbWyWWVzuHV1M6ok00c44GPk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632087; c=relaxed/simple; bh=CVgk8+0DOVtFgoErfuPTKgd5FmJ8SBgjgEb/2k9FVe0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uDJ9dd81DIvdD1bQlzNH0uurUq77w0vmznPAR8nfFrXUE1UrhnSNek7IcpBsZe4aouuOd+wG92ENdJ7FELzWLx/hlS43EdMx9nUWy1ZEnwarH22W16DPrwNrMXSd2GF5yUS6zR8Tk9nhs8EyrR0IjXGNQcmxOTH3ZSvHDm/PAIs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kDZothHs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kDZothHs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A58BBC16AAE; Wed, 28 Jan 2026 20:28:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632087; bh=CVgk8+0DOVtFgoErfuPTKgd5FmJ8SBgjgEb/2k9FVe0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kDZothHsC0SE8ArM14vzOmB2tLd6uqZJD2C7GffaxHZCpyXZzeTwICgFm+oOrsdi9 X34I9y9dnybmX7RDdxZhH37D2zJ2OV5sv4fucC+OQ8cReAtMCLRYgifhnsBcUu+HGb AI0sYUs1pD041F6ocDMXoVPuKq7DPzQnTAxnZcYkd2MM1lE1d0SBfsgRpFIyYZcPca qCZzHlrndkQA1isP7juA53jOdMhnmbDg3kaFJ+ln+YpPx1f0B0SbqXemecZfrn2F+l GcByaXMx/6g6n72pauP2macgso9Xwh6tza7xI4TWqIRgK85kg0PZbJlgg9rJH+hHnN VlE/2e25nT6oA== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:28 -0800 Subject: [PATCH RFC v2 07/17] RISC-V: QoS: define prototypes for resctrl interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-7-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2767; i=fustini@kernel.org; h=from:subject:message-id; bh=CVgk8+0DOVtFgoErfuPTKgd5FmJ8SBgjgEb/2k9FVe0=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQaISj0rOd11wV6vnWOx8sInCgdUZy9k6P2y3P/8+ osX9jQ/7ChlYRDjYpAVU2TZ9CHvwhKv0K8L5r/YBjOHlQlkCAMXpwBM5KccI8PXgsPcf53ecDCc b+N+X7AozrJql6dE/4d3L3qcPd6vOXuN4a+s+8eYNw4n9+eZ5s/7vOnUuukl/E8eWqZe7cy+d/T 9iSvsAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Define the prototypes for the resctrl interface functions that are implemented on RISC-V. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi [fustini: rebased on current upstream] Signed-off-by: Drew Fustini --- include/linux/riscv_qos.h | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/include/linux/riscv_qos.h b/include/linux/riscv_qos.h index 51c3a96bbcd0..0c551ed85fe1 100644 --- a/include/linux/riscv_qos.h +++ b/include/linux/riscv_qos.h @@ -3,6 +3,7 @@ #ifndef __LINUX_RISCV_QOS_H #define __LINUX_RISCV_QOS_H =20 +#include #include #include =20 @@ -31,4 +32,47 @@ struct cbqri_controller_info { =20 extern struct list_head cbqri_controllers; =20 +bool resctrl_arch_alloc_capable(void); +bool resctrl_arch_mon_capable(void); +bool resctrl_arch_is_llc_occupancy_enabled(void); +bool resctrl_arch_is_mbm_local_enabled(void); +bool resctrl_arch_is_mbm_total_enabled(void); + +struct rdt_resource; +/* + * Note about terminology between x86 (Intel RDT/AMD QoS) and RISC-V: + * CLOSID on x86 is RCID on RISC-V + * RMID on x86 is MCID on RISC-V + * CDP on x86 is AT (access type) on RISC-V + */ +u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid); +void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid); +void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 pmg= ); +void resctrl_arch_sched_in(struct task_struct *tsk); +void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32= rmid); +bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid); +bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid= ); +void resctrl_arch_reset_resources(void); +void *resctrl_arch_mon_ctx_alloc(struct rdt_resource *r, enum resctrl_even= t_id evtid); +void resctrl_arch_mon_ctx_free(struct rdt_resource *r, enum resctrl_event_= id evtid, + void *arch_mon_ctx); +struct rdt_domain_hdr *resctrl_arch_find_domain(struct list_head *domain_l= ist, int id); + +static inline bool resctrl_arch_event_is_free_running(enum resctrl_event_i= d evt) +{ + /* must be true for resctrl L3 monitoring files to be created */ + return true; +} + +static inline unsigned int resctrl_arch_round_mon_val(unsigned int val) +{ + return val; +} + +/* Not needed for RISC-V */ +static inline void resctrl_arch_enable_mon(void) { } +static inline void resctrl_arch_disable_mon(void) { } +static inline void resctrl_arch_enable_alloc(void) { } +static inline void resctrl_arch_disable_alloc(void) { } + #endif /* __LINUX_RISCV_QOS_H */ --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09ACE32AADA; Wed, 28 Jan 2026 20:28:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632088; cv=none; b=j5+vjWwxEYgwAQWEKjHL/52UNW148qxZMHyhsLVDE9PGoL0Jgoo9rDAxuUVoBQYKbNBtDL1ZS3cC9Kstoi1Tw3ZkFT5oavf4xxdCSumt0r2X1u0mtL0Hfuy2uzun+FHOPaz33/2Zen7AOY6j7nHNCss8HYOGLREnd52iW50BcHg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632088; c=relaxed/simple; bh=XzraD+jv8gAhejLYPXzwrc/jCF5MPR0Cpl7OBhstQgE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZjvBbH5rQuOOn1IbrgJN5iz6V+P/6fPKPCu8D+XN7Mv6wNdSavFj46y4medgi1ea1Sgl5R5tfxxT9e9jIkUgiMZwt7kr5r8R5lHo2KJLtamq4udzhkxbDO/+oV5YMcazCAVh/4rRtPqZw9m0qUKqlT55LuGffpGLkcH39nKdOZk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qzVeMux8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qzVeMux8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3A166C2BCB0; Wed, 28 Jan 2026 20:28:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632087; bh=XzraD+jv8gAhejLYPXzwrc/jCF5MPR0Cpl7OBhstQgE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qzVeMux8KRfbvd1J7ykWveNJCKSYuin5wJ59z7UnXXAGRTGF0SPlCHtHiAXz940U5 aJ0CFnX6HnxWFjIP8ql/oNOM3korkzpFdHPVQUmo/vKDiNkz5iT+xSQdo3pJUTcXDk 3KWpHjN1x5CDKUiaN/D1zkdpooC5It/BJ/0wGPxbOU3Y95+08hzANP1VClc6Fpt8dS C5APu+3gyr+s1OYzP+rA/HHKw85jKNYJWTJg7QAstwkAEs7YupmyCaEYV5yWdAmV9z 1MpAxbIq1gXBCw0AOTVlJp/QsqYOvp2kmpowtVYC5Diw0cdroufvsNx5Fr+nisyjls 7ntlgDvGIx7aw== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:29 -0800 Subject: [PATCH RFC v2 08/17] RISC-V: QoS: add resctrl interface for CBQRI controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-8-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=36897; i=fustini@kernel.org; h=from:subject:message-id; bh=XzraD+jv8gAhejLYPXzwrc/jCF5MPR0Cpl7OBhstQgE=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQas9pgaIxKUOW9xm8Oyr9XqjUxZNy6GTo9+yJ+ov PBQ1L27HaUsDGJcDLJiiiybPuRdWOIV+nXB/BfbYOawMoEMYeDiFICJPGpg+B+/MMldfr7ETZnU m87qMmZs69fMtvssqv28fIvpzuOHaw0YGc6Lme7+eHTBJSGvjGMv3/1mim+0L5rKqKzn+0DOxVZ NhBsA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add interface for CBQRI controller drivers to make use of the resctrl filesystem. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/qos_resctrl.c | 1192 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 1192 insertions(+) diff --git a/arch/riscv/kernel/qos/qos_resctrl.c b/arch/riscv/kernel/qos/qo= s_resctrl.c new file mode 100644 index 000000000000..d500098599d2 --- /dev/null +++ b/arch/riscv/kernel/qos/qos_resctrl.c @@ -0,0 +1,1192 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#define pr_fmt(fmt) "qos: resctrl: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include "internal.h" + +#define MAX_CONTROLLERS 6 +static struct cbqri_controller controllers[MAX_CONTROLLERS]; +static struct cbqri_resctrl_res cbqri_resctrl_resources[RDT_NUM_RESOURCES]; + +static bool exposed_alloc_capable; +static bool exposed_mon_capable; +/* CDP (code data prioritization) on x86 is AT (access type) on RISC-V */ +static bool exposed_cdp_l2_capable; +static bool exposed_cdp_l3_capable; +static bool is_cdp_l2_enabled; +static bool is_cdp_l3_enabled; + +/* used by resctrl_arch_system_num_rmid_idx() */ +static u32 max_rmid; + +LIST_HEAD(cbqri_controllers); + +static int cbqri_wait_busy_flag(struct cbqri_controller *ctrl, int reg_off= set); + +bool resctrl_arch_alloc_capable(void) +{ + return exposed_alloc_capable; +} + +bool resctrl_arch_mon_capable(void) +{ + return exposed_mon_capable; +} + +bool resctrl_arch_is_llc_occupancy_enabled(void) +{ + return true; +} + +bool resctrl_arch_is_mbm_local_enabled(void) +{ + return false; +} + +bool resctrl_arch_is_mbm_total_enabled(void) +{ + return false; +} + +bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level rid) +{ + switch (rid) { + case RDT_RESOURCE_L2: + return is_cdp_l2_enabled; + + case RDT_RESOURCE_L3: + return is_cdp_l3_enabled; + + default: + return false; + } +} + +int resctrl_arch_set_cdp_enabled(enum resctrl_res_level rid, bool enable) +{ + switch (rid) { + case RDT_RESOURCE_L2: + if (!exposed_cdp_l2_capable) + return -ENODEV; + is_cdp_l2_enabled =3D enable; + break; + + case RDT_RESOURCE_L3: + if (!exposed_cdp_l3_capable) + return -ENODEV; + is_cdp_l3_enabled =3D enable; + break; + + default: + return -ENODEV; + } + + return 0; +} + +struct rdt_resource *resctrl_arch_get_resource(enum resctrl_res_level l) +{ + if (l >=3D RDT_NUM_RESOURCES) + return NULL; + + return &cbqri_resctrl_resources[l].resctrl_res; +} + +struct rdt_domain_hdr *resctrl_arch_find_domain(struct list_head *domain_l= ist, int id) +{ + struct rdt_domain_hdr *hdr; + + lockdep_assert_cpus_held(); + + list_for_each_entry(hdr, domain_list, list) { + if (hdr->id =3D=3D id) + return hdr; + } + + return NULL; +} + +bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt) +{ + return false; +} + +void *resctrl_arch_mon_ctx_alloc(struct rdt_resource *r, + enum resctrl_event_id evtid) +{ + /* RISC-V can always read an rmid, nothing needs allocating */ + return NULL; +} + +void resctrl_arch_mon_ctx_free(struct rdt_resource *r, + enum resctrl_event_id evtid, void *arch_mon_ctx) +{ + /* not implemented for the RISC-V resctrl interface */ +} + +void resctrl_arch_reset_resources(void) +{ + /* not implemented for the RISC-V resctrl implementation */ +} + +void resctrl_arch_config_cntr(struct rdt_resource *r, struct rdt_mon_domai= n *d, + enum resctrl_event_id evtid, u32 rmid, u32 closid, + u32 cntr_id, bool assign) +{ + /* not implemented for the RISC-V resctrl implementation */ +} + +int resctrl_arch_cntr_read(struct rdt_resource *r, struct rdt_mon_domain *= d, + u32 unused, u32 rmid, int cntr_id, + enum resctrl_event_id eventid, u64 *val) +{ + /* not implemented for the RISC-V resctrl implementation */ + return 0; +} + +bool resctrl_arch_mbm_cntr_assign_enabled(struct rdt_resource *r) +{ + /* not implemented for the RISC-V resctrl implementation */ + return false; +} + +int resctrl_arch_mbm_cntr_assign_set(struct rdt_resource *r, bool enable) +{ + /* not implemented for the RISC-V resctrl implementation */ + return 0; +} + +void resctrl_arch_reset_cntr(struct rdt_resource *r, struct rdt_mon_domain= *d, + u32 unused, u32 rmid, int cntr_id, + enum resctrl_event_id eventid) +{ + /* not implemented for the RISC-V resctrl implementation */ +} + +bool resctrl_arch_get_io_alloc_enabled(struct rdt_resource *r) +{ + /* not implemented for the RISC-V resctrl implementation */ + return false; +} + +int resctrl_arch_io_alloc_enable(struct rdt_resource *r, bool enable) +{ + /* not implemented for the RISC-V resctrl implementation */ + return 0; +} + +/* + * Note about terminology between x86 (Intel RDT/AMD QoS) and RISC-V: + * CLOSID on x86 is RCID on RISC-V + * RMID on x86 is MCID on RISC-V + */ +u32 resctrl_arch_get_num_closid(struct rdt_resource *res) +{ + struct cbqri_resctrl_res *hw_res; + + hw_res =3D container_of(res, struct cbqri_resctrl_res, resctrl_res); + + return hw_res->max_rcid; +} + +u32 resctrl_arch_system_num_rmid_idx(void) +{ + return max_rmid; +} + +u32 resctrl_arch_rmid_idx_encode(u32 closid, u32 rmid) +{ + return rmid; +} + +void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid) +{ + *closid =3D ((u32)~0); /* refer to X86_RESCTRL_BAD_CLOSID */ + *rmid =3D idx; +} + +/* RISC-V resctrl interface does not maintain a default srmcfg value for a= given CPU */ +void resctrl_arch_set_cpu_default_closid_rmid(int cpu, u32 closid, u32 rmi= d) { } + +void resctrl_arch_sched_in(struct task_struct *tsk) +{ + __switch_to_srmcfg(tsk); +} + +void resctrl_arch_set_closid_rmid(struct task_struct *tsk, u32 closid, u32= rmid) +{ + u32 srmcfg; + + WARN_ON_ONCE((closid & SRMCFG_RCID_MASK) !=3D closid); + WARN_ON_ONCE((rmid & SRMCFG_MCID_MASK) !=3D rmid); + + srmcfg =3D rmid << SRMCFG_MCID_SHIFT; + srmcfg |=3D closid; + WRITE_ONCE(tsk->thread.srmcfg, srmcfg); +} + +void resctrl_arch_sync_cpu_closid_rmid(void *info) +{ + struct resctrl_cpu_defaults *r =3D info; + + lockdep_assert_preemption_disabled(); + + if (r) { + resctrl_arch_set_cpu_default_closid_rmid(smp_processor_id(), + r->closid, r->rmid); + } + + resctrl_arch_sched_in(current); +} + +bool resctrl_arch_match_closid(struct task_struct *tsk, u32 closid) +{ + u32 srmcfg; + bool match; + + srmcfg =3D READ_ONCE(tsk->thread.srmcfg); + match =3D (srmcfg & SRMCFG_RCID_MASK) =3D=3D closid; + return match; +} + +bool resctrl_arch_match_rmid(struct task_struct *tsk, u32 closid, u32 rmid) +{ + u32 tsk_rmid; + + tsk_rmid =3D READ_ONCE(tsk->thread.srmcfg); + tsk_rmid >>=3D SRMCFG_MCID_SHIFT; + tsk_rmid &=3D SRMCFG_MCID_MASK; + + return tsk_rmid =3D=3D rmid; +} + +int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_mon_domain *= d, + u32 closid, u32 rmid, enum resctrl_event_id eventid, + u64 *val, void *arch_mon_ctx) +{ + /* + * The current Qemu implementation of CBQRI capacity and bandwidth + * controllers do not emulate the utilization of resources over + * time. Therefore, Qemu currently sets the invalid bit in + * cc_mon_ctr_val and bc_mon_ctr_val, and there is no meaningful + * value other than 0 to return for reading an RMID (e.g. MCID in + * CBQRI terminology) + */ + + return 0; +} + +void resctrl_arch_reset_rmid(struct rdt_resource *r, struct rdt_mon_domain= *d, + u32 closid, u32 rmid, enum resctrl_event_id eventid) +{ + /* not implemented for the RISC-V resctrl interface */ +} + +void resctrl_arch_mon_event_config_read(void *info) +{ + /* not implemented for the RISC-V resctrl interface */ +} + +void resctrl_arch_mon_event_config_write(void *info) +{ + /* not implemented for the RISC-V resctrl interface */ +} + +void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_do= main *d) +{ + /* not implemented for the RISC-V resctrl implementation */ +} + +void resctrl_arch_reset_all_ctrls(struct rdt_resource *r) +{ + /* not implemented for the RISC-V resctrl implementation */ +} + +/* Set capacity block mask (cc_block_mask) */ +static void cbqri_set_cbm(struct cbqri_controller *ctrl, u64 cbm) +{ + int reg_offset; + u64 reg; + + reg_offset =3D CBQRI_CC_BLOCK_MASK_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + + reg =3D cbm; + iowrite64(reg, ctrl->base + reg_offset); +} + +/* Set the Rbwb (reserved bandwidth blocks) field in bc_bw_alloc */ +static void cbqri_set_rbwb(struct cbqri_controller *ctrl, u64 rbwb) +{ + int reg_offset; + u64 reg; + + reg_offset =3D CBQRI_BC_BW_ALLOC_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + reg &=3D ~CBQRI_CONTROL_REGISTERS_RBWB_MASK; + rbwb &=3D CBQRI_CONTROL_REGISTERS_RBWB_MASK; + reg |=3D rbwb; + iowrite64(reg, ctrl->base + reg_offset); +} + +/* Get the Rbwb (reserved bandwidth blocks) field in bc_bw_alloc */ +static u64 cbqri_get_rbwb(struct cbqri_controller *ctrl) +{ + int reg_offset; + u64 reg; + + reg_offset =3D CBQRI_BC_BW_ALLOC_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + reg &=3D CBQRI_CONTROL_REGISTERS_RBWB_MASK; + return reg; +} + +static int cbqri_wait_busy_flag(struct cbqri_controller *ctrl, int reg_off= set) +{ + unsigned long timeout =3D jiffies + usecs_to_jiffies(1000); + int busy; + u64 reg; + + while (time_before(jiffies, timeout)) { + reg =3D ioread64(ctrl->base + reg_offset); + busy =3D (reg >> CBQRI_CONTROL_REGISTERS_BUSY_SHIFT) & + CBQRI_CONTROL_REGISTERS_BUSY_MASK; + if (!busy) + return 0; + } + + pr_warn("%s(): busy timeout", __func__); + return -EIO; +} + +/* Perform capacity allocation control operation on capacity controller */ +static int cbqri_cc_alloc_op(struct cbqri_controller *ctrl, int operation,= int rcid, + enum resctrl_conf_type type) +{ + int reg_offset =3D CBQRI_CC_ALLOC_CTL_OFF; + int status; + u64 reg; + + reg =3D ioread64(ctrl->base + reg_offset); + reg &=3D ~(CBQRI_CONTROL_REGISTERS_OP_MASK << CBQRI_CONTROL_REGISTERS_OP_= SHIFT); + reg |=3D (operation & CBQRI_CONTROL_REGISTERS_OP_MASK) << + CBQRI_CONTROL_REGISTERS_OP_SHIFT; + reg &=3D ~(CBQRI_CONTROL_REGISTERS_RCID_MASK << + CBQRI_CONTROL_REGISTERS_RCID_SHIFT); + reg |=3D (rcid & CBQRI_CONTROL_REGISTERS_RCID_MASK) << + CBQRI_CONTROL_REGISTERS_RCID_SHIFT; + + /* CBQRI capacity AT is only supported on L2 and L3 caches for now */ + if (ctrl->ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY && + ((ctrl->ctrl_info->cache.cache_level =3D=3D 2 && is_cdp_l2_enabled) || + (ctrl->ctrl_info->cache.cache_level =3D=3D 3 && is_cdp_l3_enabled))) { + reg &=3D ~(CBQRI_CONTROL_REGISTERS_AT_MASK << + CBQRI_CONTROL_REGISTERS_AT_SHIFT); + switch (type) { + case CDP_CODE: + reg |=3D (CBQRI_CONTROL_REGISTERS_AT_CODE & + CBQRI_CONTROL_REGISTERS_AT_MASK) << + CBQRI_CONTROL_REGISTERS_AT_SHIFT; + break; + case CDP_DATA: + default: + reg |=3D (CBQRI_CONTROL_REGISTERS_AT_DATA & + CBQRI_CONTROL_REGISTERS_AT_MASK) << + CBQRI_CONTROL_REGISTERS_AT_SHIFT; + break; + } + } + + iowrite64(reg, ctrl->base + reg_offset); + + if (cbqri_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when executing the operation", __func__); + return -EIO; + } + + reg =3D ioread64(ctrl->base + reg_offset); + status =3D (reg >> CBQRI_CONTROL_REGISTERS_STATUS_SHIFT) & + CBQRI_CONTROL_REGISTERS_STATUS_MASK; + if (status !=3D 1) { + pr_err("%s(): operation %d failed: status=3D%d", __func__, operation, st= atus); + return -EIO; + } + + return 0; +} + +static int cbqri_apply_cache_config(struct cbqri_resctrl_dom *hw_dom, u32 = closid, + enum resctrl_conf_type type, struct cbqri_config *cfg) +{ + struct cbqri_controller *ctrl =3D hw_dom->hw_ctrl; + int reg_offset; + int err =3D 0; + u64 reg; + + if (cfg->cbm !=3D hw_dom->ctrl_val[closid]) { + /* Store the new cbm in the ctrl_val array for this closid in this domai= n */ + hw_dom->ctrl_val[closid] =3D cfg->cbm; + + /* Set capacity block mask (cc_block_mask) */ + cbqri_set_cbm(ctrl, cfg->cbm); + + /* Capacity config limit operation */ + err =3D cbqri_cc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT, clos= id, type); + if (err < 0) { + pr_err("%s(): operation failed: err =3D %d", __func__, err); + return err; + } + + /* Clear cc_block_mask before read limit to verify op works*/ + cbqri_set_cbm(ctrl, 0); + + /* Performa capacity read limit operation to verify blockmask */ + err =3D cbqri_cc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, closid= , type); + if (err < 0) { + pr_err("%s(): operation failed: err =3D %d", __func__, err); + return err; + } + + /* Read capacity blockmask to verify it matches the requested config */ + reg_offset =3D CBQRI_CC_BLOCK_MASK_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + if (reg !=3D cfg->cbm) { + pr_warn("%s(): failed to verify allocation (reg:%llx !=3D cbm:%llx)", + __func__, reg, cfg->cbm); + return -EIO; + } + } + + return err; +} + +/* Perform bandwidth allocation control operation on bandwidth controller = */ +static int cbqri_bc_alloc_op(struct cbqri_controller *ctrl, int operation,= int rcid) +{ + int reg_offset =3D CBQRI_BC_ALLOC_CTL_OFF; + int status; + u64 reg; + + reg =3D ioread64(ctrl->base + reg_offset); + reg &=3D ~(CBQRI_CONTROL_REGISTERS_OP_MASK << CBQRI_CONTROL_REGISTERS_OP_= SHIFT); + reg |=3D (operation & CBQRI_CONTROL_REGISTERS_OP_MASK) << + CBQRI_CONTROL_REGISTERS_OP_SHIFT; + reg &=3D ~(CBQRI_CONTROL_REGISTERS_RCID_MASK << CBQRI_CONTROL_REGISTERS_R= CID_SHIFT); + reg |=3D (rcid & CBQRI_CONTROL_REGISTERS_RCID_MASK) << + CBQRI_CONTROL_REGISTERS_RCID_SHIFT; + iowrite64(reg, ctrl->base + reg_offset); + + if (cbqri_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when executing the operation", __func__); + return -EIO; + } + + reg =3D ioread64(ctrl->base + reg_offset); + status =3D (reg >> CBQRI_CONTROL_REGISTERS_STATUS_SHIFT) & + CBQRI_CONTROL_REGISTERS_STATUS_MASK; + if (status !=3D 1) { + pr_err("%s(): operation %d failed with status =3D %d", + __func__, operation, status); + return -EIO; + } + + return 0; +} + +static int cbqri_apply_bw_config(struct cbqri_resctrl_dom *hw_dom, u32 clo= sid, + enum resctrl_conf_type type, struct cbqri_config *cfg) +{ + struct cbqri_controller *ctrl =3D hw_dom->hw_ctrl; + int ret =3D 0; + u64 reg; + + if (cfg->rbwb !=3D hw_dom->ctrl_val[closid]) { + /* Store the new rbwb in the ctrl_val array for this closid in this doma= in */ + hw_dom->ctrl_val[closid] =3D cfg->rbwb; + + /* Set reserved bandwidth blocks */ + cbqri_set_rbwb(ctrl, cfg->rbwb); + + /* Bandwidth config limit operation */ + ret =3D cbqri_bc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_CONFIG_LIMIT, clos= id); + if (ret < 0) { + pr_err("%s(): operation failed: ret =3D %d", __func__, ret); + return ret; + } + + /* Clear rbwb before read limit to verify op works*/ + cbqri_set_rbwb(ctrl, 0); + + /* Bandwidth allocation read limit operation to verify */ + ret =3D cbqri_bc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, closid= ); + if (ret < 0) { + pr_err("%s(): operation failed: ret =3D %d", __func__, ret); + return ret; + } + + /* Read bandwidth allocation to verify it matches the requested config */ + reg =3D cbqri_get_rbwb(ctrl); + if (reg !=3D cfg->rbwb) { + pr_warn("%s(): failed to verify allocation (reg:%llx !=3D rbwb:%llu)", + __func__, reg, cfg->rbwb); + return -EIO; + } + } + + return ret; +} + +int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_ctrl_domain= *d, + u32 closid, enum resctrl_conf_type t, u32 cfg_val) +{ + struct cbqri_controller *ctrl; + struct cbqri_resctrl_dom *dom; + struct cbqri_config cfg; + int err =3D 0; + + dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_ctrl_dom); + ctrl =3D dom->hw_ctrl; + + if (!r->alloc_capable) + return -EINVAL; + + switch (r->rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + cfg.cbm =3D cfg_val; + err =3D cbqri_apply_cache_config(dom, closid, t, &cfg); + break; + case RDT_RESOURCE_MBA: + /* covert from percentage to bandwidth blocks */ + cfg.rbwb =3D cfg_val * ctrl->bc.nbwblks / 100; + err =3D cbqri_apply_bw_config(dom, closid, t, &cfg); + break; + default: + return -EINVAL; + } + + return err; +} + +int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid) +{ + struct resctrl_staged_config *cfg; + enum resctrl_conf_type t; + struct rdt_ctrl_domain *d; + int err =3D 0; + + list_for_each_entry(d, &r->ctrl_domains, hdr.list) { + for (t =3D 0; t < CDP_NUM_TYPES; t++) { + cfg =3D &d->staged_config[t]; + if (!cfg->have_new_ctrl) + continue; + err =3D resctrl_arch_update_one(r, d, closid, t, cfg->new_ctrl); + if (err) { + pr_warn("%s(): update failed (err=3D%d)", __func__, err); + return err; + } + } + } + return err; +} + +u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_ctrl_domain= *d, + u32 closid, enum resctrl_conf_type type) +{ + struct cbqri_resctrl_dom *hw_dom; + struct cbqri_controller *ctrl; + int reg_offset; + u32 percent; + u32 rbwb; + u64 reg; + int err; + + hw_dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_ctrl_dom); + + ctrl =3D hw_dom->hw_ctrl; + + if (!r->alloc_capable) + return resctrl_get_default_ctrl(r); + + switch (r->rid) { + case RDT_RESOURCE_L2: + case RDT_RESOURCE_L3: + /* Clear cc_block_mask before read limit operation */ + cbqri_set_cbm(ctrl, 0); + + /* Capacity read limit operation for RCID (closid) */ + err =3D cbqri_cc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, type, = closid); + if (err < 0) { + pr_err("%s(): operation failed: err =3D %d", __func__, err); + return resctrl_get_default_ctrl(r); + } + + /* Read capacity block mask for RCID (closid) */ + reg_offset =3D CBQRI_CC_BLOCK_MASK_OFF; + reg =3D ioread64(ctrl->base + reg_offset); + + /* Update the config value for the closid in this domain */ + hw_dom->ctrl_val[closid] =3D reg; + return hw_dom->ctrl_val[closid]; + + case RDT_RESOURCE_MBA: + /* Capacity read limit operation for RCID (closid) */ + err =3D cbqri_bc_alloc_op(ctrl, CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, closid= ); + if (err < 0) { + pr_err("%s(): operation failed: err =3D %d", __func__, err); + return resctrl_get_default_ctrl(r); + } + + hw_dom->ctrl_val[closid] =3D cbqri_get_rbwb(ctrl); + + /* Convert from bandwidth blocks to percent */ + rbwb =3D hw_dom->ctrl_val[closid]; + rbwb *=3D 100; + percent =3D rbwb / ctrl->bc.nbwblks; + if (rbwb % ctrl->bc.nbwblks) + percent++; + return percent; + + default: + return resctrl_get_default_ctrl(r); + } +} + +static int cbqri_probe_feature(struct cbqri_controller *ctrl, int reg_offs= et, + int operation, int *status, bool *access_type_supported) +{ + u64 reg, saved_reg; + int at; + + /* Keep the initial register value to preserve the WPRI fields */ + reg =3D ioread64(ctrl->base + reg_offset); + saved_reg =3D reg; + + /* Execute the requested operation to find if the register is implemented= */ + reg &=3D ~(CBQRI_CONTROL_REGISTERS_OP_MASK << CBQRI_CONTROL_REGISTERS_OP_= SHIFT); + reg |=3D (operation & CBQRI_CONTROL_REGISTERS_OP_MASK) << CBQRI_CONTROL_R= EGISTERS_OP_SHIFT; + iowrite64(reg, ctrl->base + reg_offset); + if (cbqri_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when executing the operation", __func__); + return -EIO; + } + + /* Get the operation status */ + reg =3D ioread64(ctrl->base + reg_offset); + *status =3D (reg >> CBQRI_CONTROL_REGISTERS_STATUS_SHIFT) & + CBQRI_CONTROL_REGISTERS_STATUS_MASK; + + /* + * Check for the AT support if the register is implemented + * (if not, the status value will remain 0) + */ + if (*status !=3D 0) { + /* Set the AT field to a valid value */ + reg =3D saved_reg; + reg &=3D ~(CBQRI_CONTROL_REGISTERS_AT_MASK << CBQRI_CONTROL_REGISTERS_AT= _SHIFT); + reg |=3D CBQRI_CONTROL_REGISTERS_AT_CODE << CBQRI_CONTROL_REGISTERS_AT_S= HIFT; + iowrite64(reg, ctrl->base + reg_offset); + if (cbqri_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when setting AT field", __func__); + return -EIO; + } + + /* + * If the AT field value has been reset to zero, + * then the AT support is not present + */ + reg =3D ioread64(ctrl->base + reg_offset); + at =3D (reg >> CBQRI_CONTROL_REGISTERS_AT_SHIFT) & CBQRI_CONTROL_REGISTE= RS_AT_MASK; + if (at =3D=3D CBQRI_CONTROL_REGISTERS_AT_CODE) + *access_type_supported =3D true; + else + *access_type_supported =3D false; + } + + /* Restore the original register value */ + iowrite64(saved_reg, ctrl->base + reg_offset); + if (cbqri_wait_busy_flag(ctrl, reg_offset) < 0) { + pr_err("%s(): BUSY timeout when restoring the original register value", = __func__); + return -EIO; + } + + return 0; +} + +/* + * Note: for the purposes of the CBQRI proof-of-concept, debug logging + * has been left in this function that detects the properties of CBQRI + * capable controllers in the system. pr_info calls would be removed + * before submitting non-RFC patches. + */ +static int cbqri_probe_controller(struct cbqri_controller_info *ctrl_info, + struct cbqri_controller *ctrl) +{ + int err =3D 0, status; + u64 reg; + + pr_info("controller info: type=3D%d addr=3D0x%lx size=3D%lu max-rcid=3D%u= max-mcid=3D%u", + ctrl_info->type, ctrl_info->addr, ctrl_info->size, + ctrl_info->rcid_count, ctrl_info->mcid_count); + + /* max_rmid is used by resctrl_arch_system_num_rmid_idx() */ + max_rmid =3D ctrl_info->mcid_count; + + ctrl->ctrl_info =3D ctrl_info; + + /* Try to access the memory-mapped CBQRI registers */ + if (!request_mem_region(ctrl_info->addr, ctrl_info->size, "cbqri_controll= er")) { + pr_warn("%s(): request_mem_region failed for cbqri_controller at 0x%lx", + __func__, ctrl_info->addr); + return -EBUSY; + } + ctrl->base =3D ioremap(ctrl_info->addr, ctrl_info->size); + if (!ctrl->base) { + pr_warn("%s(): goto err_release_mem_region", __func__); + goto err_release_mem_region; + } + + ctrl->alloc_capable =3D false; + ctrl->mon_capable =3D false; + + /* Probe capacity allocation and monitoring features */ + if (ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY) { + pr_info("probe capacity controller"); + + /* Make sure the register is implemented */ + reg =3D ioread64(ctrl->base + CBQRI_CC_CAPABILITIES_OFF); + if (reg =3D=3D 0) { + err =3D -ENODEV; + goto err_iounmap; + } + + ctrl->ver_minor =3D reg & CBQRI_CC_CAPABILITIES_VER_MINOR_MASK; + ctrl->ver_major =3D reg & CBQRI_CC_CAPABILITIES_VER_MAJOR_MASK; + + ctrl->cc.supports_alloc_op_flush_rcid =3D (reg >> CBQRI_CC_CAPABILITIES_= FRCID_SHIFT) + & CBQRI_CC_CAPABILITIES_FRCID_MASK; + + ctrl->cc.ncblks =3D (reg >> CBQRI_CC_CAPABILITIES_NCBLKS_SHIFT) & + CBQRI_CC_CAPABILITIES_NCBLKS_MASK; + + /* Calculate size of capacity block in bytes */ + ctrl->cc.blk_size =3D ctrl_info->cache.cache_size / ctrl->cc.ncblks; + ctrl->cc.cache_level =3D ctrl_info->cache.cache_level; + + pr_info("version=3D%d.%d ncblks=3D%d blk_size=3D%d cache_level=3D%d", + ctrl->ver_major, ctrl->ver_minor, + ctrl->cc.ncblks, ctrl->cc.blk_size, ctrl->cc.cache_level); + + /* Probe monitoring features */ + err =3D cbqri_probe_feature(ctrl, CBQRI_CC_MON_CTL_OFF, + CBQRI_CC_MON_CTL_OP_READ_COUNTER, &status, + &ctrl->cc.supports_mon_at_code); + if (err) { + pr_warn("%s() failed to probe cc_mon_ctl feature", __func__); + goto err_iounmap; + } + + if (status =3D=3D CBQRI_CC_MON_CTL_STATUS_SUCCESS) { + pr_info("cc_mon_ctl is supported"); + ctrl->cc.supports_mon_op_config_event =3D true; + ctrl->cc.supports_mon_op_read_counter =3D true; + ctrl->mon_capable =3D true; + } else { + pr_info("cc_mon_ctl is NOT supported"); + ctrl->cc.supports_mon_op_config_event =3D false; + ctrl->cc.supports_mon_op_read_counter =3D false; + ctrl->mon_capable =3D false; + } + /* + * AT data is "always" supported as it has the same value + * than when AT field is not supported. + */ + ctrl->cc.supports_mon_at_data =3D true; + pr_info("supports_mon_at_data: %d, supports_mon_at_code: %d", + ctrl->cc.supports_mon_at_data, ctrl->cc.supports_mon_at_code); + + /* Probe allocation features */ + err =3D cbqri_probe_feature(ctrl, CBQRI_CC_ALLOC_CTL_OFF, + CBQRI_CC_ALLOC_CTL_OP_READ_LIMIT, + &status, &ctrl->cc.supports_alloc_at_code); + if (err) { + pr_warn("%s() failed to probe cc_alloc_ctl feature", __func__); + goto err_iounmap; + } + + if (status =3D=3D CBQRI_CC_ALLOC_CTL_STATUS_SUCCESS) { + pr_info("cc_alloc_ctl is supported"); + ctrl->cc.supports_alloc_op_config_limit =3D true; + ctrl->cc.supports_alloc_op_read_limit =3D true; + ctrl->alloc_capable =3D true; + exposed_alloc_capable =3D true; + } else { + pr_info("cc_alloc_ctl is NOT supported"); + ctrl->cc.supports_alloc_op_config_limit =3D false; + ctrl->cc.supports_alloc_op_read_limit =3D false; + ctrl->alloc_capable =3D false; + } + /* + * AT data is "always" supported as it has the same value + * than when AT field is not supported + */ + ctrl->cc.supports_alloc_at_data =3D true; + pr_info("supports_alloc_at_data: %d, supports_alloc_at_code: %d", + ctrl->cc.supports_alloc_at_data, + ctrl->cc.supports_alloc_at_code); + } else if (ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_BANDWIDTH) { + pr_info("probe bandwidth controller"); + + /* Make sure the register is implemented */ + reg =3D ioread64(ctrl->base + CBQRI_BC_CAPABILITIES_OFF); + if (reg =3D=3D 0) { + err =3D -ENODEV; + goto err_iounmap; + } + + ctrl->ver_minor =3D reg & CBQRI_BC_CAPABILITIES_VER_MINOR_MASK; + ctrl->ver_major =3D reg & CBQRI_BC_CAPABILITIES_VER_MAJOR_MASK; + + ctrl->bc.nbwblks =3D (reg >> CBQRI_BC_CAPABILITIES_NBWBLKS_SHIFT) & + CBQRI_BC_CAPABILITIES_NBWBLKS_MASK; + ctrl->bc.mrbwb =3D (reg >> CBQRI_BC_CAPABILITIES_MRBWB_SHIFT) & + CBQRI_BC_CAPABILITIES_MRBWB_MASK; + + pr_info("version=3D%d.%d nbwblks=3D%d mrbwb=3D%d", + ctrl->ver_major, ctrl->ver_minor, + ctrl->bc.nbwblks, ctrl->bc.mrbwb); + + /* Probe monitoring features */ + err =3D cbqri_probe_feature(ctrl, CBQRI_BC_MON_CTL_OFF, + CBQRI_BC_MON_CTL_OP_READ_COUNTER, + &status, &ctrl->bc.supports_mon_at_code); + if (err) { + pr_warn("%s() failed to probe bc_mon_ctl feature", __func__); + goto err_iounmap; + } + + if (status =3D=3D CBQRI_BC_MON_CTL_STATUS_SUCCESS) { + pr_info("bc_mon_ctl is supported"); + ctrl->bc.supports_mon_op_config_event =3D true; + ctrl->bc.supports_mon_op_read_counter =3D true; + ctrl->mon_capable =3D true; + exposed_mon_capable =3D true; + } else { + pr_info("bc_mon_ctl is NOT supported"); + ctrl->bc.supports_mon_op_config_event =3D false; + ctrl->bc.supports_mon_op_read_counter =3D false; + ctrl->mon_capable =3D false; + } + /* + * AT data is "always" supported as it has the same value + * than when AT field is not supported + */ + ctrl->bc.supports_mon_at_data =3D true; + pr_info("supports_mon_at_data: %d, supports_mon_at_code: %d", + ctrl->bc.supports_mon_at_data, ctrl->bc.supports_mon_at_code); + + /* Probe allocation features */ + err =3D cbqri_probe_feature(ctrl, CBQRI_BC_ALLOC_CTL_OFF, + CBQRI_BC_ALLOC_CTL_OP_READ_LIMIT, + &status, &ctrl->bc.supports_alloc_at_code); + if (err) { + pr_warn("%s() failed to probe bc_alloc_ctl feature", __func__); + goto err_iounmap; + } + + if (status =3D=3D CBQRI_BC_ALLOC_CTL_STATUS_SUCCESS) { + pr_warn("bc_alloc_ctl is supported"); + ctrl->bc.supports_alloc_op_config_limit =3D true; + ctrl->bc.supports_alloc_op_read_limit =3D true; + ctrl->alloc_capable =3D true; + exposed_alloc_capable =3D true; + } else { + pr_warn("bc_alloc_ctl is NOT supported"); + ctrl->bc.supports_alloc_op_config_limit =3D false; + ctrl->bc.supports_alloc_op_read_limit =3D false; + ctrl->alloc_capable =3D false; + } + + /* + * AT data is "always" supported as it has the same value + * than when AT field is not supported + */ + ctrl->bc.supports_alloc_at_data =3D true; + pr_warn("supports_alloc_at_data: %d, supports_alloc_at_code: %d", + ctrl->bc.supports_alloc_at_data, ctrl->bc.supports_alloc_at_code); + } else { + pr_warn("controller type is UNKNOWN"); + err =3D -ENODEV; + goto err_release_mem_region; + } + + return 0; + +err_iounmap: + pr_warn("%s(): err_iounmap", __func__); + iounmap(ctrl->base); + +err_release_mem_region: + pr_warn("%s(): err_release_mem_region", __func__); + release_mem_region(ctrl_info->addr, ctrl_info->size); + + return err; +} + +static struct rdt_ctrl_domain *qos_new_domain(struct cbqri_controller *ctr= l) +{ + struct cbqri_resctrl_dom *hw_dom; + struct rdt_ctrl_domain *domain; + + hw_dom =3D kzalloc(sizeof(*hw_dom), GFP_KERNEL); + if (!hw_dom) + return NULL; + + /* associate this cbqri_controller with the domain */ + hw_dom->hw_ctrl =3D ctrl; + + /* the rdt_domain struct from inside the cbqri_resctrl_dom struct */ + domain =3D &hw_dom->resctrl_ctrl_dom; + + INIT_LIST_HEAD(&domain->hdr.list); + + return domain; +} + +static int qos_init_domain_ctrlval(struct rdt_resource *r, struct rdt_ctrl= _domain *d) +{ + struct cbqri_resctrl_res *hw_res; + struct cbqri_resctrl_dom *hw_dom; + u64 *dc; + int err =3D 0; + int i; + + hw_res =3D container_of(r, struct cbqri_resctrl_res, resctrl_res); + if (!hw_res) + return -ENOMEM; + + hw_dom =3D container_of(d, struct cbqri_resctrl_dom, resctrl_ctrl_dom); + if (!hw_dom) + return -ENOMEM; + + dc =3D kmalloc_array(hw_res->max_rcid, sizeof(*hw_dom->ctrl_val), + GFP_KERNEL); + if (!dc) + return -ENOMEM; + + hw_dom->ctrl_val =3D dc; + + for (i =3D 0; i < hw_res->max_rcid; i++, dc++) { + err =3D resctrl_arch_update_one(r, d, i, 0, resctrl_get_default_ctrl(r)); + if (err) + return 0; + *dc =3D resctrl_get_default_ctrl(r); + } + return 0; +} + +static int qos_resctrl_add_controller_domain(struct cbqri_controller *ctrl= , int *id) +{ + struct rdt_ctrl_domain *domain =3D NULL; + struct cbqri_resctrl_res *cbqri_res =3D NULL; + struct rdt_resource *res =3D NULL; + int internal_id =3D *id; + int err =3D 0; + + domain =3D qos_new_domain(ctrl); + if (!domain) + return -ENOSPC; + if (ctrl->ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY) { + cpumask_copy(&domain->hdr.cpu_mask, &ctrl->ctrl_info->cache.cpu_mask); + if (ctrl->ctrl_info->cache.cache_level =3D=3D 2) { + cbqri_res =3D &cbqri_resctrl_resources[RDT_RESOURCE_L2]; + cbqri_res->max_rcid =3D ctrl->ctrl_info->rcid_count; + cbqri_res->max_mcid =3D ctrl->ctrl_info->mcid_count; + res =3D &cbqri_res->resctrl_res; + res->mon.num_rmid =3D ctrl->ctrl_info->mcid_count; + res->rid =3D RDT_RESOURCE_L2; + res->name =3D "L2"; + res->alloc_capable =3D ctrl->alloc_capable; + res->mon_capable =3D ctrl->mon_capable; + res->schema_fmt =3D RESCTRL_SCHEMA_BITMAP; + res->ctrl_scope =3D RESCTRL_L2_CACHE; + res->cache.arch_has_sparse_bitmasks =3D false; + res->cache.arch_has_per_cpu_cfg =3D false; + res->cache.cbm_len =3D ctrl->cc.ncblks; + res->cache.shareable_bits =3D resctrl_get_default_ctrl(res); + res->cache.min_cbm_bits =3D 1; + } else if (ctrl->ctrl_info->cache.cache_level =3D=3D 3) { + cbqri_res =3D &cbqri_resctrl_resources[RDT_RESOURCE_L3]; + cbqri_res->max_rcid =3D ctrl->ctrl_info->rcid_count; + cbqri_res->max_mcid =3D ctrl->ctrl_info->mcid_count; + res =3D &cbqri_res->resctrl_res; + res->mon.num_rmid =3D ctrl->ctrl_info->mcid_count; + res->rid =3D RDT_RESOURCE_L3; + res->name =3D "L3"; + res->schema_fmt =3D RESCTRL_SCHEMA_BITMAP; + res->ctrl_scope =3D RESCTRL_L3_CACHE; + res->alloc_capable =3D ctrl->alloc_capable; + res->mon_capable =3D ctrl->mon_capable; + res->cache.arch_has_sparse_bitmasks =3D false; + res->cache.arch_has_per_cpu_cfg =3D false; + res->cache.cbm_len =3D ctrl->cc.ncblks; + res->cache.shareable_bits =3D resctrl_get_default_ctrl(res); + res->cache.min_cbm_bits =3D 1; + } else { + pr_warn("%s(): unknown cache level %d", __func__, + ctrl->ctrl_info->cache.cache_level); + err =3D -ENODEV; + goto err_free_domain; + } + } else if (ctrl->ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_BANDWIDTH) { + if (ctrl->alloc_capable) { + cbqri_res =3D &cbqri_resctrl_resources[RDT_RESOURCE_MBA]; + cbqri_res->max_rcid =3D ctrl->ctrl_info->rcid_count; + cbqri_res->max_mcid =3D ctrl->ctrl_info->mcid_count; + res =3D &cbqri_res->resctrl_res; + res->mon.num_rmid =3D ctrl->ctrl_info->mcid_count; + res->rid =3D RDT_RESOURCE_MBA; + res->name =3D "MB"; + res->schema_fmt =3D RESCTRL_SCHEMA_RANGE; + res->ctrl_scope =3D RESCTRL_L3_CACHE; + res->alloc_capable =3D ctrl->alloc_capable; + res->mon_capable =3D false; + res->membw.delay_linear =3D true; + res->membw.arch_needs_linear =3D true; + res->membw.throttle_mode =3D THREAD_THROTTLE_UNDEFINED; + // The minimum percentage allowed by the CBQRI spec + res->membw.min_bw =3D 1; + // The maximum percentage allowed by the CBQRI spec + res->membw.max_bw =3D 80; + res->membw.bw_gran =3D 1; + } + } else { + pr_warn("%s(): unknown resource %d", __func__, ctrl->ctrl_info->type); + err =3D -ENODEV; + goto err_free_domain; + } + + domain->hdr.id =3D internal_id; + err =3D qos_init_domain_ctrlval(res, domain); + if (err) + goto err_free_domain; + + if (cbqri_res) { + list_add_tail(&domain->hdr.list, &cbqri_res->resctrl_res.ctrl_domains); + *id =3D internal_id; + err =3D resctrl_online_ctrl_domain(res, domain); + if (err) { + pr_warn("%s(): failed to online cbqri_res domain", __func__); + goto err_free_domain; + } + } + + return 0; + +err_free_domain: + pr_warn("%s(): err_free_domain", __func__); + kfree(container_of(domain, struct cbqri_resctrl_dom, resctrl_ctrl_dom)); + + return err; +} + +int qos_resctrl_setup(void) +{ + struct rdt_ctrl_domain *domain, *domain_temp; + struct cbqri_controller_info *ctrl_info; + struct cbqri_controller *ctrl; + struct cbqri_resctrl_res *res; + static int found_controllers; + int err =3D 0; + int id =3D 0; + int i; + + list_for_each_entry(ctrl_info, &cbqri_controllers, list) { + err =3D cbqri_probe_controller(ctrl_info, &controllers[found_controllers= ]); + if (err) { + pr_warn("%s(): failed (%d)", __func__, err); + goto err_unmap_controllers; + } + + found_controllers++; + if (found_controllers > MAX_CONTROLLERS) { + pr_warn("%s(): increase MAX_CONTROLLERS value", __func__); + break; + } + } + + for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { + res =3D &cbqri_resctrl_resources[i]; + INIT_LIST_HEAD(&res->resctrl_res.ctrl_domains); + INIT_LIST_HEAD(&res->resctrl_res.mon_domains); + res->resctrl_res.rid =3D i; + } + + for (i =3D 0; i < found_controllers; i++) { + ctrl =3D &controllers[i]; + err =3D qos_resctrl_add_controller_domain(ctrl, &id); + if (err) { + pr_warn("%s(): failed to add controller domain (%d)", __func__, err); + goto err_free_controllers_list; + } + id++; + + /* + * CDP (code data prioritization) on x86 is similar to + * the AT (access type) field in CBQRI. CDP only supports + * caches so this must be a CBQRI capacity controller. + */ + if (ctrl->ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY && + ctrl->cc.supports_alloc_at_code && + ctrl->cc.supports_alloc_at_data) { + if (ctrl->ctrl_info->cache.cache_level =3D=3D 2) + exposed_cdp_l2_capable =3D true; + else + exposed_cdp_l3_capable =3D true; + } + } + + pr_info("exposed_alloc_capable =3D %d", exposed_alloc_capable); + pr_info("exposed_mon_capable =3D %d", exposed_mon_capable); + pr_info("exposed_cdp_l2_capable =3D %d", exposed_cdp_l2_capable); + pr_info("exposed_cdp_l3_capable =3D %d", exposed_cdp_l3_capable); + + return resctrl_init(); + +err_free_controllers_list: + for (i =3D 0; i < RDT_NUM_RESOURCES; i++) { + res =3D &cbqri_resctrl_resources[i]; + list_for_each_entry_safe(domain, domain_temp, &res->resctrl_res.ctrl_dom= ains, + hdr.list) { + kfree(domain); + } + } + +err_unmap_controllers: + for (i =3D 0; i < found_controllers; i++) { + iounmap(controllers[i].base); + release_mem_region(controllers[i].ctrl_info->addr, controllers[i].ctrl_i= nfo->size); + } + + return err; +} + +int qos_resctrl_online_cpu(unsigned int cpu) +{ + resctrl_online_cpu(cpu); + return 0; +} + +int qos_resctrl_offline_cpu(unsigned int cpu) +{ + resctrl_offline_cpu(cpu); + return 0; +} + --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87B50374751; Wed, 28 Jan 2026 20:28:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632088; cv=none; b=Xh5l0rZgrpBMhUrJ8f8UdeAKTJdlAy4AsXRQTGce7npHF00OeTi+aoLArfZ2xZYKjqWBuFwtwxldeOF9S3TUaHtjQL+dGmKQx0aMtajhM6uKdnpaVGVza1WFf7PnQrkdc+wo0H5iVFbY/4tEozFmIrLCWPj/RKneDDLcbmy412M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632088; c=relaxed/simple; bh=SXrtFbN0ix7KxT0GqeIs7HkzT3FdlhgaF3gCwM+F2Mc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QEIqcjJgHjlS69A23i9ievgkuQkvpgD5WIYv/mNzvTBnh/k7O2QaCinlNZaqTWv+BB3/FWsolIhBUz3NHVN3T5NCDpgpESoOz+53Nrtn/53wi6MbAcdaHQvFBaM2kurFVNO++3uq7iOwRg0OepHc+dFU1zjLqA8RsDo28HMeyUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SXHGNinc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SXHGNinc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8DC3C2BCB7; Wed, 28 Jan 2026 20:28:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632088; bh=SXrtFbN0ix7KxT0GqeIs7HkzT3FdlhgaF3gCwM+F2Mc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SXHGNincT1DeoGx7ssYkSIxdzYD3fa107Q47yezQ1LeJwiV7ONy7LToOgvXkr0ZTw S68V839gLSVlHktb33pZevH0NgFjRlLb4uTsqB7lP/nwom+MUzF2srHxzBO7UqKjRL A+YHYevDMB7kT5OadaQGqqUXK9iRjrOUEOokLC1pkS8QncUhifRrAoqrk+7C95SCzE 9rOkjDAeI5KTOmJxYrovOZp38l5w2ERAycGoY5PFVGIE5zdt0qE7N9RobXeDDGXkS6 bGzEeD+ksB8JeVfeg38UGEthfHxRDTSwoZ5sgumdZ5MpcHNwBamciSNHc2ZiF7Wl8w /E+is7bA4XZpA== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:30 -0800 Subject: [PATCH RFC v2 09/17] RISC-V: QoS: expose implementation to resctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-9-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1087; i=fustini@kernel.org; h=from:subject:message-id; bh=SXrtFbN0ix7KxT0GqeIs7HkzT3FdlhgaF3gCwM+F2Mc=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQZwVWzgevGUQymt74rxZA9L+66yIPZaRfbY6W7uB Q61/bc6SlkYxLgYZMUUWTZ9yLuwxCv064L5L7bBzGFlAhnCwMUpABOZMp/hn0qHm5PoJqH/af9y TM9v48sSELjomZSU/fxiS2xaiuC+R4wMp8/OnJf36OwJtsRDBaFS9//EPXecIMawUeqn1DmzpWx eTAA= X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 The generic resctrl header include/linux/resctrl.h includes linux/riscv_qos.h when CONFIG_ARCH_HAS_CPU_RESCTRL is set. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + arch/riscv/include/asm/resctrl.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 31e536304972..96ead357a634 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22510,6 +22510,7 @@ M: Drew Fustini L: linux-riscv@lists.infradead.org S: Supported F: arch/riscv/include/asm/qos.h +F: arch/riscv/include/asm/resctrl.h F: arch/riscv/kernel/qos/ F: include/linux/riscv_qos.h =20 diff --git a/arch/riscv/include/asm/resctrl.h b/arch/riscv/include/asm/resc= trl.h new file mode 100644 index 000000000000..7d247d87dab9 --- /dev/null +++ b/arch/riscv/include/asm/resctrl.h @@ -0,0 +1,2 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6E183783A4; Wed, 28 Jan 2026 20:28:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632089; cv=none; b=tt3VlrD4eNrVFt9uomlE2Ua9NumFzancFaE+Rn76vUOZQ0HHrc0VzAEwr1xcEtNouCgevqzXPPUuKpwlu+Ys6IWUovYSNyIw5WuepfdsKhdxgru/Tpy+Sryj6ZpjD8CZTb8i9Ifeqq5vL2EhL9r6OjgwMk0WUTIzpbVvWbXYdK4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632089; c=relaxed/simple; bh=jw+AW2ohMGVwE01frppRYwsxi/H3/LBPifNRE5CWvac=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qfZxSixkHYqA8NwXrjSVzAUs5KTBYbtYuWggckdfibKAKccQ49FFsz87aeJXTL4cz07f+1+JJYqj4eiRXpzQ1GCqkTOCw9lj6wEn88Hn5kW2vZSJWoD+SZA8U/6aIU/Uhoi+8NQKBUpP1p0k4T5QRc5MaWmIA3OGL7QimTvoV4A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PFEyCSFY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PFEyCSFY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 58B83C16AAE; Wed, 28 Jan 2026 20:28:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632088; bh=jw+AW2ohMGVwE01frppRYwsxi/H3/LBPifNRE5CWvac=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PFEyCSFY9buxPwA/UYfJ9y6TzNhi5d7Mf6yymH4zM5ftIqAxhd1mF4xPxnGghHzhn wVGMsgsb4yUrKbkbpI+5juyIXr2R4W2x0YmNhly8WM/cqyQJc6hvE7b0fQEYN8AR3y Di/wJ+Zuj1HCiTCTrlhcodoqTVkKv+tFGNa17wxeALUAzDSeX6fKk9NKtpJ8Aggmp0 PeLCIOKP+Z3m9OdCjPGIk5OMnC/GWqilwJHyt9zs8u3apVLhdEATe7N9OPz9t/zM3i lAZx3dNodfFAy350LNxRgFjbn34XG+sijz9MRiyIArDCul9XidFcPasnQGQ6CPi/Cx MepzuFjh+aGUg== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:31 -0800 Subject: [PATCH RFC v2 10/17] RISC-V: QoS: add late_initcall to setup resctrl interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-10-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1362; i=fustini@kernel.org; h=from:subject:message-id; bh=jw+AW2ohMGVwE01frppRYwsxi/H3/LBPifNRE5CWvac=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQbkXNyQ4ne0/N2Myrrrzzb82uG803Fee4CQVrjJ5 PURjJKzOkpZGMS4GGTFFFk2fci7sMQr9OuC+S+2wcxhZQIZwsDFKQATifnOyDBdaNvy9TZJU7fN cne4bfFXNnyS2tGelI9iyy8+8vf+OzGL4X9e5UnDRbFBxsbK4pN3Osyqf3m/y7RColuJ64Bh0sl tW3kB X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add late_initcall which checks if the Ssqosid extension is present, and if so, calls resctrl setup and sets cpu hotplug state to "qos:online". Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/qos.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/riscv/kernel/qos/qos.c b/arch/riscv/kernel/qos/qos.c index 7b06f7ae9056..2cd5d7be1d10 100644 --- a/arch/riscv/kernel/qos/qos.c +++ b/arch/riscv/kernel/qos/qos.c @@ -1,5 +1,32 @@ // SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include + +#include #include =20 +#include "internal.h" + /* cached value of sqoscfg csr for each cpu */ DEFINE_PER_CPU(u32, cpu_srmcfg); + +static int __init qos_arch_late_init(void) +{ + int err; + + if (!riscv_isa_extension_available(NULL, SSQOSID)) + return -ENODEV; + + err =3D qos_resctrl_setup(); + if (err !=3D 0) + return err; + + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "qos:online", qos_resctrl_online_c= pu, + qos_resctrl_offline_cpu); + + return err; +} +late_initcall(qos_arch_late_init); --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8ACF6376BEB; Wed, 28 Jan 2026 20:28:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632089; cv=none; b=p/Ho6zOXXh6Xq5Y8wUWVAPxVIhFRWwuLU6SZdqD9exYqnf+JkLdGpV4vXm7N+wrc7mw92BrubjgKzBS0HgaOgaXs6nNjoOh44ackp5j9wxf0bTTzGwtPRS9NJRW/zDpZWLo22t5orzJiaFSPfEB4wZhi30YjRUojnCdeNRvNS4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632089; c=relaxed/simple; bh=LLcYCf8E3m+c3NEGM6PLVB/b2aK0eRa7uHCxUc0B8eM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ogBTlN9kexJ5SDbD1VYLNipahNRHtnW1LEMwbMtMCvm0nacvaDnWemSAwfWZqe02CW2bfepD9/TKagP78MPkmtENJoBbhyePziggOqSh4ECUZo1GQH6fS5O0/K3lvHaSC2B34817cEniNaXAR/XPy6oiRErku3MImpCjQdHjp+c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EhM4N6sp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EhM4N6sp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E1AE3C4CEF1; Wed, 28 Jan 2026 20:28:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632089; bh=LLcYCf8E3m+c3NEGM6PLVB/b2aK0eRa7uHCxUc0B8eM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EhM4N6spWcTX8jUod7ooTwW2pQzTpXLDJHyiIXyOkD4SL+5HdLWkoDHTxDO7bi2Hi nouUOXfo+YKMR401HXpQSubprm0j+3PBDaR6rPU7CLq6N7v0pZkPlzfXq2fhLHMnOe 2nyqkGoGBP4KBgvwQXVesod7EY73IMRZUoLVoYqtQlDKfdjDitDmElP82Sw1S3zryh RdVtHPb0WPhPgT/+zPf7M1d6g0xF+bI2y8YsHzjwx/u8N+nstX++843GTr3WvoxfHf d/aSBkVnT630pDlsxsfh8Ih3yaDVL+YbSQc9iCLbkosVJKqLpH4YXCwiaBX6lyjneb RiLqcyeDSUL9Q== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:32 -0800 Subject: [PATCH RFC v2 11/17] RISC-V: QoS: add to build when CONFIG_RISCV_ISA_SSQOSID set Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-11-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=738; i=fustini@kernel.org; h=from:subject:message-id; bh=LLcYCf8E3m+c3NEGM6PLVB/b2aK0eRa7uHCxUc0B8eM=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQbe/6ucKK+kJ+cks0JsRXbcirMiy68l1xwRNT3K1 tBlwZPaUcrCIMbFICumyLLpQ96FJV6hXxfMf7ENZg4rE8gQBi5OAZjICwZGhmnTpT/+/Va91WWC CqNftv68qEeHueqaIlfyP5G4lTNr40NGhi1/sgQKKrgPf/3cVD3btpDnqvjKisscpzaViUdPjUt +zgsA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add the srmcfg CSR handling and the resctrl interface to the build when CONFIG_RISCV_ISA_SSQOSID is set. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/kernel/qos/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/qos/Makefile b/arch/riscv/kernel/qos/Makefile index 9f996263a86d..9ed0c13a854d 100644 --- a/arch/riscv/kernel/qos/Makefile +++ b/arch/riscv/kernel/qos/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos.o +obj-$(CONFIG_RISCV_ISA_SSQOSID) +=3D qos.o qos_resctrl.o --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25874378805; Wed, 28 Jan 2026 20:28:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632090; cv=none; b=moL55zLHI1QMGqY+VXmHTxPlx8SC9qcRcvsrw1qi+bPhT6iI1IAigJ8LjTTibRFoUxTgrXzt15EsluAUPeAQHxjuE+yj4XLWmnsFvFCIaScwUJzP8WunrZuxXQG0XFGliiPtn4Gl2n4bf4yMmmDcxfyKQWble8kGtYwrqjiqyps= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632090; c=relaxed/simple; bh=uFVTMJOPvCbobzJzlLLOywkmk/8YKf9YQOLxRrQYfB8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=K+7tFJwFkut1Y9ztJNeMESRnhU8UKOrE3O4O9LwrGiuTJBiaxCKEgnMN03za1tkr0s0Rjp8/4EWjwxJ1pn4Muq7QxRUKZDKGuICMFP91OuowuktxGTZqwiLVEc7MDB4qeffsSL8h9KLuKI3eXxQOw4KtZJQXSnra613eNJjkZWw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SPPkuaDg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SPPkuaDg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 71CBDC4CEF7; Wed, 28 Jan 2026 20:28:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632089; bh=uFVTMJOPvCbobzJzlLLOywkmk/8YKf9YQOLxRrQYfB8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SPPkuaDgcf/BvE0ZirdITV/+1qku/YWxWJrcZ7ODvLUS+ziSK4eRpeoN86oXxrxuv hUvJXiPJxwfGoTMU0NrA9PBme53oM2P2Sj6j1PaiS6oswVMgqPaM7ar14rupJk7RS+ y7dy/w7147MJX6/d/q2MSnxv6lbmHrxq2CrY+z0HD4qqVimIX0qfXJPLrGkWF/tFFf 8eS0as/v5sXvgIbi7yvdz8ZCsjgEE9UaG0p1/X1UPeG9R+rfaRfRBmq6CNH2pEMOSr D9B6nWgJcxjT1Y/KR3UEctH0ei3I6OlLCsQ1wjBC+x7S0dkJmjko4uI2ZRKXEvb3l3 pasmzSX/29q9A== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:33 -0800 Subject: [PATCH RFC v2 12/17] RISC-V: QoS: make CONFIG_RISCV_ISA_SSQOSID select resctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-12-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=875; i=fustini@kernel.org; h=from:subject:message-id; bh=uFVTMJOPvCbobzJzlLLOywkmk/8YKf9YQOLxRrQYfB8=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQa2ul2WMDnBtvGQZY1t1YQ7obmFv5+eiOHI/h1rK 8Wc0xvWUcrCIMbFICumyLLpQ96FJV6hXxfMf7ENZg4rE8gQBi5OAZjI93kM/+N8ns6Zv2thVmVO yi7r27o1X99LPIiWES0WtvNoy9xWEMjwV+yvzak3rAYW8vzctWWPJRSmX6g4l/X6hLDfNpV5+h5 izAA= X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Make CONFIG_RISCV_ISA_SSQOSID select the config options for resctrl: ARCH_HAS_CPU_RESCTRL, RESCTRL_FS and MISC_FILESYSTEMS. Co-developed-by: Adrien Ricciardi Signed-off-by: Adrien Ricciardi Signed-off-by: Drew Fustini --- arch/riscv/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 35a6238b02c5..8ff6d962b6b2 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -598,6 +598,9 @@ config RISCV_ISA_SVNAPOT config RISCV_ISA_SSQOSID bool "Ssqosid extension support for supervisor mode Quality of Service ID" default y + select ARCH_HAS_CPU_RESCTRL + select RESCTRL_FS + select MISC_FILESYSTEMS help Adds support for the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF4F2378837; Wed, 28 Jan 2026 20:28:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632091; cv=none; b=mubM2BXCbr5vBWY1t0s3N1cjNewHNMKHTTGoQmuAuJDqxiBcusxgE+p9vhq2rnMXqMqGNoQwfwWTClXUDIXjnCv80W9eguIdg1dpQM6xFZ9ab4jNXjzr5qRveDJIBk2kWLkbbGsF53VDGbtJt4rsm79hcDzO/D6R17v3HXCq8Pc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632091; c=relaxed/simple; bh=ocyqe4U7WsJJbTpfliXFcM4vxluIpCLTh7ZpGc7FQ9c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HFQo9ZxTXLxsR410HCm5IiOV4+sVt+YhPP37D/9K8JLUR1QgREkIhNr+kjxZ0iZF6bgHrQTAGkM9XbOQJNISzsHUREBps7MaYlIe1n0Wj09/6xT+AqAAVGfGh1212kJL06yxu5wDBxqw/sXojDmxXSan8w/aYvnV4VKXD6Ii4eo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HbukFBG+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HbukFBG+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0AE73C2BCB6; Wed, 28 Jan 2026 20:28:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632090; bh=ocyqe4U7WsJJbTpfliXFcM4vxluIpCLTh7ZpGc7FQ9c=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HbukFBG+BVdHcteku9MwelF3rnMrQgJFghq6OZXCg5Wo5w/M6fgaw9wzgtHBlHOW1 rW+G8vQfaNvEpize+pVloepoxynpzcwSDZtd1EvjSC7x6CRsoL+mEwfeiWcRaINuAB HteP3IzzZ4ADheYpxvQLwdEw4d45oPj+bD4erFph+GLriIDePg7Wy0A795AFfwg58Q oPznvx57FUi9ilO1GmxcLQEd3anBF7PgGs6eLNE0VUweCeMp0zy8wox7hUNXwW9sYN nrkbieancGhVy32DDtoVxFMZ22KPgdi7fRCht6u66H7FBBP/GsUmiYk9w4BxjqokkX +WncgTdQo4sjA== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:34 -0800 Subject: [PATCH RFC v2 13/17] acpi: pptt: Add helper to find a cache from id Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-13-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3896; i=fustini@kernel.org; h=from:subject:message-id; bh=ocyqe4U7WsJJbTpfliXFcM4vxluIpCLTh7ZpGc7FQ9c=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQZ+FZveccRm85//urc4F8ws39AV4PNEeSnr7A3fJ qQfjjZR6ihlYRDjYpAVU2TZ9CHvwhKv0K8L5r/YBjOHlQlkCAMXpwBMZN5JRoY9yR671mX9nXtM Y0eh5fX2lpN5ji2OBTNnHiqsUwgTMzZn+B86nb1+klSz0ddQYdlrLO/8j2srLPvgcEXN9ulepdj O1ywA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add function to find the pointer to an instance of acpi_pptt_cache. find_acpi_cache_from_id() is based on find_acpi_cache_level_from_id() from commit c4170570cc7f ("ACPI / PPTT: Find PPTT cache level by ID") in the morse/mpam/snapshot/v6.14-rc1 branch. TODO: find_acpi_cache_level_from_id() has changed since then so this function should be updated. In additon, there may be a simpler way for acpi_parse_rqsc() than adding this function to get a pointer to acpi_pptt_cache. Signed-off-by: Drew Fustini --- drivers/acpi/pptt.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/acpi.h | 8 +++++++ 2 files changed, 71 insertions(+) diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c index de5f8c018333..d1002673dc39 100644 --- a/drivers/acpi/pptt.c +++ b/drivers/acpi/pptt.c @@ -1063,3 +1063,66 @@ int acpi_pptt_get_cpumask_from_cache_id(u32 cache_id= , cpumask_t *cpus) =20 return 0; } + +/* + * find_acpi_cache_from_id() is adapted from find_acpi_cache_level_from_id= () + * introduced by c4170570cc7f ("ACPI / PPTT: Find PPTT cache level by ID") + * in the morse/mpam/snapshot/v6.14-rc1 branch. + * + * TODO: find_acpi_cache_level_from_id() has changed since then so this + * function should be updated. In additon, there may be a simpler way for + * acpi_parse_rqsc() than adding this function to get a pointer to + * acpi_pptt_cache. + */ +struct acpi_pptt_cache *find_acpi_cache_from_id(u32 cache_id) +{ + u32 acpi_cpu_id; + acpi_status status; + int level, cpu, num_levels; + struct acpi_pptt_cache *cache; + struct acpi_table_header *table; + struct acpi_pptt_cache_v1 *cache_v1; + struct acpi_pptt_processor *cpu_node; + + status =3D acpi_get_table(ACPI_SIG_PPTT, 0, &table); + if (ACPI_FAILURE(status)) { + acpi_pptt_warn_missing(); + return NULL; + } + + if (table->revision < 3) { + acpi_put_table(table); + return NULL; + } + + for_each_possible_cpu(cpu) { + num_levels =3D 0; + acpi_cpu_id =3D get_acpi_id_for_cpu(cpu); + + cpu_node =3D acpi_find_processor_node(table, acpi_cpu_id); + if (!cpu_node) + break; + num_levels =3D acpi_count_levels(table, cpu_node, NULL); + + for (level =3D 1; level <=3D num_levels; level++) { + cache =3D acpi_find_cache_node(table, acpi_cpu_id, + ACPI_PPTT_CACHE_TYPE_UNIFIED, + level, &cpu_node); + if (!cache) + continue; + + cache_v1 =3D ACPI_ADD_PTR(struct acpi_pptt_cache_v1, + cache, + sizeof(struct acpi_pptt_cache)); + + if (cache->flags & ACPI_PPTT_CACHE_ID_VALID && + cache_v1->cache_id =3D=3D cache_id) { + acpi_put_table(table); + return cache; + } + } + } + + acpi_put_table(table); + return NULL; +} diff --git a/include/linux/acpi.h b/include/linux/acpi.h index fbf0c3a65f59..fee6a5059a46 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1546,6 +1546,7 @@ int find_acpi_cpu_topology_package(unsigned int cpu); int find_acpi_cpu_topology_hetero_id(unsigned int cpu); void acpi_pptt_get_cpus_from_container(u32 acpi_cpu_id, cpumask_t *cpus); int find_acpi_cache_level_from_id(u32 cache_id); +struct acpi_pptt_cache *find_acpi_cache_from_id(u32 cache_id); int acpi_pptt_get_cpumask_from_cache_id(u32 cache_id, cpumask_t *cpus); #else static inline int acpi_pptt_cpu_is_thread(unsigned int cpu) @@ -1570,10 +1571,17 @@ static inline int find_acpi_cpu_topology_hetero_id(= unsigned int cpu) } static inline void acpi_pptt_get_cpus_from_container(u32 acpi_cpu_id, cpumask_t *cpus) { } + static inline int find_acpi_cache_level_from_id(u32 cache_id) { return -ENOENT; } + +static inline struct acpi_pptt_cache *find_acpi_cache_from_id(u32 cache_id) +{ + return NULL; +} + static inline int acpi_pptt_get_cpumask_from_cache_id(u32 cache_id, cpumask_t *cpus) { --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70EC6376472; Wed, 28 Jan 2026 20:28:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632091; cv=none; b=pOGb2gH3okGTOpoMhHSqr5O5eSvDalFuBiczeYvkx61Gd3Dz/sEFHa+QtYm2aSIxssdxNh9Xl5JAdoCfNSzXXNJshm3YeyndY5bia/Q+T4vOpjbIFfblWgFdqqt5rGxUqEUNZbn91TWWexEjds0JjAM3VBh+JvIReucpC/Vkjz0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632091; c=relaxed/simple; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-14-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3784; i=fustini@kernel.org; h=from:subject:message-id; bh=jn4odfUh7D9q/BnIUXd595ocfV3eTkf4xm4P7+F2KGs=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQYuf+rF9cdUp/OLUNZB9dDmGU1v8/a8TDT4kd770 Fs8T2hKRykLgxgXg6yYIsumD3kXlniFfl0w/8U2mDmsTCBDGLg4BWAiF7Yx/E/VP/jo2DT+dXOC L1V5Le1/cSEtaInd38bvD4/9YGFy+JTMyHB+ZtysU13nM+xZDl1pKptxhLP42asagWTH7GXyDe8 murAAAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add structs for the RQSC table which describes the properties of the RISC-V QoS controllers (CBQRI) in the system. The table also describes the topological arrangement of the QoS controllers and resources in the system. The topology is expressed in terms of the location of the resources within the system and the relation between the QoS Controller and the resource it manages. Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 Link: https://github.com/riscv-non-isa/riscv-rqsc/blob/main/src/chapter2.ad= oc Signed-off-by: Drew Fustini --- include/acpi/actbl2.h | 92 +++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 92 insertions(+) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index f726bce3eb84..7367990349ee 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -53,6 +53,7 @@ #define ACPI_SIG_RGRT "RGRT" /* Regulatory Graphics Resource Tab= le */ #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */ #define ACPI_SIG_RIMT "RIMT" /* RISC-V IO Mapping Table */ +#define ACPI_SIG_RQSC "RQSC" /* RISC-V RISC-V Quality of Service= Controller */ #define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Tabl= e */ #define ACPI_SIG_SDEI "SDEI" /* Software Delegated Exception Int= erface Table */ #define ACPI_SIG_SDEV "SDEV" /* Secure Devices table */ @@ -3165,6 +3166,97 @@ enum acpi_rgrt_image_type { ACPI_RGRT_TYPE_RESERVED =3D 2 /* 2 and greater are reserved */ }; =20 +/*************************************************************************= ****** + * + * RQSC - RISC-V Quality of Service Controller + * Version 1 + * + *************************************************************************= *****/ + +struct acpi_table_rqsc_fields_res { + u8 type; // 1 + u8 resv; // 1 + u16 length; // 2 + u16 flags; // 2 + u8 resv2; // 1 + u8 id_type; // 1 + u64 id1; // 8 + u32 id2; // 4 +}; + +struct acpi_table_rqsc_fields { + u8 type; // 1 + u8 resv; // 1 + u16 length; // 2 + u32 reg[3]; // 12 + u32 rcid; // 4 + u32 mcid; // 4 + u16 flags; // 2 + u16 nres; // 2 + struct acpi_table_rqsc_fields_res res; // 20 +}; + +struct acpi_table_rqsc { + struct acpi_table_header header; /* Common ACPI table header */ + u32 num; + struct acpi_table_rqsc_fields f[6]; +}; + +/* RQSC Flags */ +#define ACPI_RQSC_TIMER_CANNOT_WAKEUP_CPU (1) + +/* + * RQSC subtables + */ +struct acpi_rqsc_node_header { + u16 type; + u16 length; + u16 revision; +}; + +/* Values for RQSC subtable Type above */ +enum acpi_rqsc_node_type { + ACPI_RQSC_NODE_TYPE_ISA_STRING =3D 0x0000, + ACPI_RQSC_NODE_TYPE_CMO =3D 0x0001, + ACPI_RQSC_NODE_TYPE_MMU =3D 0x0002, + ACPI_RQSC_NODE_TYPE_RESERVED =3D 0x0003, + ACPI_RQSC_NODE_TYPE_HART_INFO =3D 0xFFFF, +}; + +/* + * RQSC node specific subtables + */ + +/* ISA string node structure */ +struct acpi_rqsc_isa_string { + u16 isa_length; + char isa[]; +}; + +struct acpi_rqsc_cmo_node { + u8 reserved; /* Must be zero */ + u8 cbom_size; /* CBOM size in powerof 2 */ + u8 cbop_size; /* CBOP size in powerof 2 */ + u8 cboz_size; /* CBOZ size in powerof 2 */ +}; + +struct acpi_rqsc_mmu_node { + u8 reserved; /* Must be zero */ + u8 mmu_type; /* Virtual Address Scheme */ +}; + +enum acpi_rqsc_mmu_type { + ACPI_RQSC_MMU_TYPE_SV39 =3D 0, + ACPI_RQSC_MMU_TYPE_SV48 =3D 1, + ACPI__MMU_TYPE_SV57 =3D 2 +}; + +/* Hart Info node structure */ +struct acpi_rqsc_hart_info { + u16 num_offsets; + u32 uid; /* ACPI processor UID */ +}; + /*************************************************************************= ****** * * RHCT - RISC-V Hart Capabilities Table --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2464374720; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="vJq1dOMe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4242EC19421; Wed, 28 Jan 2026 20:28:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632091; bh=4o0KFAigHCtXfQSjAvAOAbc0aP+19v9iIO4nX66XDCM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=vJq1dOMePTouoidO/P2tv+4dKpxFdEC2aSVyZi0wNFbc6ZsUxexPgDwcQi96Ht9E3 pxTjJFsUzUNZiAbloJoMLqK2b6OyYUFBESwWfzSZUdhu9rQa2ZS+hoKUY6Kmvtwkwm wBVOuHKRAGZZthnQHbjcESTZIazXMrj7KBvoFCxBYAyn05MPA4pUnGno7CFafh3H/S Y/EMMUO3C+beVB6aNfLRIo7XkNbmIZqgvmkyOl7IyU7uQP/I1c/32WrRl/aOyS3CK0 YN2gEB5ZkokGY20mtw0zFTfD7i91rj6M+Nq0muzJA6k/z4bsNtJMUIqXsWFflTX7tY Rsmrpn5quQUdg== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:36 -0800 Subject: [PATCH RFC v2 15/17] RISC-V: QoS: add Cache ID and Prox Dom to CBQRI controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-15-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=899; i=fustini@kernel.org; h=from:subject:message-id; bh=4o0KFAigHCtXfQSjAvAOAbc0aP+19v9iIO4nX66XDCM=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQYKivn8UZhwb8bOXbu6v8tnpR05HvQsufNYFt+j1 afM6u6od5SyMIhxMciKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAmsqae4X94zqLaLyYnUleZ KwvYv8uQ8nPp4djz44G1stUU3YVf4m8w/C/18GCrmGqa9rfnLzOP2282w/m9/VW2p9ee41n83XB /Py8A X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Expand cbqri_controller_info to contain: - Cache ID from the PPTT table's Cache Type Structure - Proximity Domain from SRAT table Memory Affifinty Controller Signed-off-by: Drew Fustini --- include/linux/riscv_qos.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/linux/riscv_qos.h b/include/linux/riscv_qos.h index 0c551ed85fe1..4812b6811327 100644 --- a/include/linux/riscv_qos.h +++ b/include/linux/riscv_qos.h @@ -27,7 +27,14 @@ struct cbqri_controller_info { u32 cache_level; u32 cache_size; /* in bytes */ struct cpumask cpu_mask; + // Unique Cache ID from the PPTT table's Cache Type Structure + u32 cache_id; } cache; + + struct mem_controller { + // Proximity Domain from SRAT table Memory Affifinty Controller + u32 prox_dom; + } mem; }; =20 extern struct list_head cbqri_controllers; --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EF803793BE; Wed, 28 Jan 2026 20:28:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632092; cv=none; b=aKjlj3AKOIt2BFsfDtSfNVQzuOCOMlNwBHCyEulBzGVPuHeOtS/tLDopg2yTAHCbmiLk8AwFFdjl6Qzam3c4rjGFwzQskXL67MFmQlt1c5rrRFOvkbdRR4DX+n4rMD9kZCqSTA5C/dKZKacFR8tHE7deLLGqyYi1DCfrg3DsePw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769632092; c=relaxed/simple; bh=/31EreH53ZbfLgFROUgaazBzJSVsVuqJTT5oOs7SCjM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e1ga4kkXUtpwyIRI5LhctQFtbRUyBt/SuGGhm6TQ7KVFdZEooMwpe3yoHEv5reoYmUl0nrWObDau2KTbwlpD2r2LYxOZHk4uu1Oo7fDfZzPZlf6hTWdQJpt3QWWIKsIjvMOZz2q64JVR9FBD0DNsMLPsalhvoPT+UibFUOZXJtk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ucbNnild; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ucbNnild" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CB782C16AAE; Wed, 28 Jan 2026 20:28:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632092; bh=/31EreH53ZbfLgFROUgaazBzJSVsVuqJTT5oOs7SCjM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ucbNnildD1YQ95dVxpJ2kkQXeMWx+bA6Mc2FsARgFcVczjwggyqCOcgGWKsjXfec0 51D6f5QPatAMeAu9Vw6HX+6MRLWkyyK6yzpjQQlivsYVrTrYieeOmAAYjkYpC6njYK K7NE0shSt3timYgnt9sBnvphGh2hQP16PqKuqTDkVV3H2wkYDF5c/dL9sHxeiHygKF 6QL+fgFZpGiBtC1RH0UUPAzxFv/9qe2Nje7LN9WU+3iv6g+cZCTL5ZvPakAArH+9Lp 9GlN8ysBJm1zNmO5ChhjFmzSnxiSs0gdkJhnT9j7aw0P+nGRKD/uKtDX9+BI2hS/q1 dAoFoM2VcjExQ== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:37 -0800 Subject: [PATCH RFC v2 16/17] acpi: riscv: Parse RISC-V Quality of Service Controller (RQSC) table Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-16-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5705; i=fustini@kernel.org; h=from:subject:message-id; bh=/31EreH53ZbfLgFROUgaazBzJSVsVuqJTT5oOs7SCjM=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQZGmc3dXWH840Dfap/on9x8wdaVnnOLfHdbrlfoZ HF8f8W3o5SFQYyLQVZMkWXTh7wLS7xCvy6Y/2IbzBxWJpAhDFycAjCRfdsZGf7cnRk68dAd/agJ ifslzvismBv8apVhxuS3PauDbFtSvs9mZOgQt1u7wGulryvHyoVrpmtsZF2jVzO1cZL8hI91bI+ mqnABAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Add driver to parse the ACPI RISC-V Quality of Service Controller (RQSC) table which describes the capacity and bandwidth QoS controllers in a system. The QoS controllers implement the RISC-V Capacity and Bandwidth Controller QoS Register Interface (CBQRI) specification. Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 Link: https://github.com/riscv-non-isa/riscv-rqsc/blob/main/src/ Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + arch/riscv/include/asm/acpi.h | 10 ++++ drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/rqsc.c | 112 ++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 124 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 96ead357a634..e96a83dc9a02 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22512,6 +22512,7 @@ S: Supported F: arch/riscv/include/asm/qos.h F: arch/riscv/include/asm/resctrl.h F: arch/riscv/kernel/qos/ +F: drivers/acpi/riscv/rqsc.c F: include/linux/riscv_qos.h =20 RISC-V RPMI AND MPXY DRIVERS diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 6e13695120bc..16c6e25eed1e 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -71,6 +71,16 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, =20 void acpi_get_cbo_block_size(struct acpi_table_header *table, u32 *cbom_si= ze, u32 *cboz_size, u32 *cbop_size); + +#ifdef CONFIG_RISCV_ISA_SSQOSID +int acpi_parse_rqsc(struct acpi_table_header *table); +#else +static inline int acpi_parse_rqsc(struct acpi_table_header *table) +{ + return -EINVAL; +} +#endif /* CONFIG_RISCV_ISA_SSQOSID */ + #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 1284a076fa88..cf0f38c93a9f 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y +=3D rhct.o init.o irq.o +obj-y +=3D rhct.o rqsc.o init.o irq.o obj-$(CONFIG_ACPI_PROCESSOR_IDLE) +=3D cpuidle.o obj-$(CONFIG_ACPI_CPPC_LIB) +=3D cppc.o obj-$(CONFIG_ACPI_RIMT) +=3D rimt.o diff --git a/drivers/acpi/riscv/rqsc.c b/drivers/acpi/riscv/rqsc.c new file mode 100644 index 000000000000..a86ddb39fae4 --- /dev/null +++ b/drivers/acpi/riscv/rqsc.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Tenstorrent + * Author: Drew Fustini + * + */ + +#define pr_fmt(fmt) "ACPI: RQSC: " fmt + +#include +#include +#include + +#ifdef CONFIG_RISCV_ISA_SSQOSID + +#define CBQRI_CTRL_SIZE 0x1000 + +static struct acpi_table_rqsc *acpi_get_rqsc(void) +{ + static struct acpi_table_header *rqsc; + acpi_status status; + + /* + * RQSC will be used at runtime on every CPU, so we + * don't need to call acpi_put_table() to release the table mapping. + */ + if (!rqsc) { + status =3D acpi_get_table(ACPI_SIG_RQSC, 0, &rqsc); + if (ACPI_FAILURE(status)) { + pr_warn_once("No RQSC table found\n"); + return NULL; + } + } + + return (struct acpi_table_rqsc *)rqsc; +} + +int acpi_parse_rqsc(struct acpi_table_header *table) +{ + struct acpi_table_rqsc *rqsc; + int err; + + BUG_ON(acpi_disabled); + if (!table) { + rqsc =3D acpi_get_rqsc(); + if (!rqsc) + return -ENOENT; + } else { + rqsc =3D (struct acpi_table_rqsc *)table; + } + + for (int i =3D 0; i < rqsc->num; i++) { + struct cbqri_controller_info *ctrl_info; + + ctrl_info =3D kzalloc(sizeof(*ctrl_info), GFP_KERNEL); + if (!ctrl_info) + return -ENOMEM; + + ctrl_info->type =3D rqsc->f[i].type; + ctrl_info->addr =3D rqsc->f[i].reg[1]; + ctrl_info->size =3D CBQRI_CTRL_SIZE; + ctrl_info->rcid_count =3D rqsc->f[i].rcid; + ctrl_info->mcid_count =3D rqsc->f[i].mcid; + + pr_info("Found controller with type %u addr 0x%lx size %lu rcid %u mci= d %u", + ctrl_info->type, ctrl_info->addr, ctrl_info->size, + ctrl_info->rcid_count, ctrl_info->mcid_count); + + if (ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_CAPACITY) { + ctrl_info->cache.cache_id =3D rqsc->f[i].res.id1; + ctrl_info->cache.cache_level =3D + find_acpi_cache_level_from_id(ctrl_info->cache.cache_id); + + struct acpi_pptt_cache *cache; + + cache =3D find_acpi_cache_from_id(ctrl_info->cache.cache_id); + if (cache) { + ctrl_info->cache.cache_size =3D cache->size; + } else { + pr_warn("%s(): failed to determine size for cache id 0x%x", + __func__, ctrl_info->cache.cache_id); + ctrl_info->cache.cache_size =3D 0; + } + + pr_info("Cache controller has ID 0x%x level %u size %u ", + ctrl_info->cache.cache_id, ctrl_info->cache.cache_level, + ctrl_info->cache.cache_size); + + /* + * For CBQRI, any cpu (technically a hart in RISC-V terms) + * can access the memory-mapped registers of any CBQRI + * controller in the system. + */ + err =3D cpumask_parse("FF", &ctrl_info->cache.cpu_mask); + if (err) + pr_err("Failed to convert cores mask string to cpumask (%d)", err); + + } else if (ctrl_info->type =3D=3D CBQRI_CONTROLLER_TYPE_BANDWIDTH) { + ctrl_info->mem.prox_dom =3D rqsc->f[i].res.id1; + pr_info("Memory controller with proximity domain %u", + ctrl_info->mem.prox_dom); + } + + /* Fill the list shared with RISC-V QoS resctrl */ + INIT_LIST_HEAD(&ctrl_info->list); + list_add_tail(&ctrl_info->list, &cbqri_controllers); + } + + return 0; +} + +#endif /* CONFIG_RISCV_ISA_SSQOSID */ --=20 2.43.0 From nobody Sat Feb 7 07:12:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 205C43793D2; Wed, 28 Jan 2026 20:28:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Wed, 28 Jan 2026 20:28:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769632092; bh=2p876OLLX8prfj4iRVt0MftQApA/Ndfp5I0kmihgDv8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=nvNmYpXNTrs2Gd+j6e50jmN2l9Z23bYLF6ssVdaiXzTPbUxc1qT0mjM+DcxcHugJA J/87PsgTsnafBZfhqlt4m2QgOzifGKJFseryVtiSaY/M0PZYJrWd3Zv+x6wuWpMVbc a1FuXbEM4c1p717fgARM4pWgqSQ/6nuzP/cOqvACY6mrFevw2R7SPPJXKH407qNmfj p0xLmcEpdgDon99ai9bazDER0LJA7+06Vrm4HlSAQdMY5mHWpeFfHtKjcFyPq/YjCS TdH8SRbUVexwp+kUyzm/u5LFPIRobL4hdKcn85jEL3DIxztlARfclD0EkOvOxPxA7G eqS2ZdeZ/bEiw== From: Drew Fustini Date: Wed, 28 Jan 2026 12:27:38 -0800 Subject: [PATCH RFC v2 17/17] acpi: riscv: Add support for RISC-V Quality of Service Controller (RQSC) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-ssqosid-cbqri-v2-17-dca586b091b9@kernel.org> References: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> In-Reply-To: <20260128-ssqosid-cbqri-v2-0-dca586b091b9@kernel.org> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , Samuel Holland , Adrien Ricciardi , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Patra , Atish Kumar Patra , Vasudevan Srinivasan , Ved Shanbhogue , yunhui cui , Chen Pei , Liu Zhiwei , Weiwei Li , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Reinette Chatre , Tony Luck , Babu Moger , Peter Newman , Fenghua Yu , James Morse , Ben Horgan , Dave Martin , Drew Fustini , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, x86@kernel.org, Rob Herring , "Rafael J. Wysocki" , Len Brown , Robert Moore , Sunil V L , Krzysztof Kozlowski , Conor Dooley Cc: Paul Walmsley , linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, devicetree@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1324; i=fustini@kernel.org; h=from:subject:message-id; bh=2p876OLLX8prfj4iRVt0MftQApA/Ndfp5I0kmihgDv8=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWRWFQbtj1tz8omO0oPqJVoaSzVyZ5XOXdDCNGlde9i+1 cb+1ue5O0pZGMS4GGTFFFk2fci7sMQr9OuC+S+2wcxhZQIZwsDFKQATSbnM8FfULF18ztyD7n2W pqyZ+yauDr77hnXnoYku5rIKxUJ/WFcyMhy7rmJWJHzzwKmlUrNj/W1SknNrz7VFH7jXoNB0Qjb wEgcA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Enable support for the RQSC table which describes the capacity and bandwidth QoS (CBQRI) controllers in a system. Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 Link: https://github.com/riscv-non-isa/riscv-rqsc/blob/main/src/ Signed-off-by: Drew Fustini --- drivers/acpi/riscv/init.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index 7c00f7995e86..784fa0c56516 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -6,10 +6,29 @@ =20 #include #include "init.h" +#include =20 void __init acpi_arch_init(void) { + struct acpi_table_header *rqsc; + acpi_status status; + int rc; + riscv_acpi_init_gsi_mapping(); + if (IS_ENABLED(CONFIG_ACPI_RIMT)) riscv_acpi_rimt_init(); + + if (!acpi_disabled) { + status =3D acpi_get_table(ACPI_SIG_RQSC, 0, &rqsc); + if (ACPI_FAILURE(status)) { + pr_err("%s(): failed to find ACPI RQSC table: %d", __func__, + ACPI_FAILURE(status)); + } else { + rc =3D acpi_parse_rqsc(rqsc); + if (rc < 0) + pr_err("%s(): failed to parse ACPI RQSC table: %d", __func__, rc); + } + acpi_put_table((struct acpi_table_header *)rqsc); + } } --=20 2.43.0