From nobody Tue Feb 10 15:28:33 2026 Received: from mail-ej1-f67.google.com (mail-ej1-f67.google.com [209.85.218.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EA5E34F275 for ; Wed, 28 Jan 2026 12:26:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.67 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769603222; cv=none; b=ANTrhBCYyFONkawh060Rj1y80pPriRoeXZwIA0PgebFzlk7699gjk18fQZAJV9JsvsfEERr9/qBcozizrlCsuK4eS4c/PxdzBCGig/T+BcY8rLCxnL9qOQR9kBHysD45rcgEfwg8d3cD7sV/xLx5CvL7T1G67iItopDndotDqkU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769603222; c=relaxed/simple; bh=aYBhXyfeGAiKcjO0bljvvMwVi3NEa7dlY1olVgUIsz0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Jr+/vjkGrKTIvB8VzScUYXMxSgc/Xl6G6x5303HyuugQA195MrMmjh5pK0RTm36+En9bIWqBmtaEO8Rg4b8RyXzu7SNPkIu0I0QLRAjn2MGL08SOQCj7fCjW1nnKpyL/WLctoRA/D9SkXNh5Y7oSMC9+BVAm7aX5uADnwCU57yU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=J8bOyXtC; arc=none smtp.client-ip=209.85.218.67 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="J8bOyXtC" Received: by mail-ej1-f67.google.com with SMTP id a640c23a62f3a-b885e8c6727so170891966b.1 for ; Wed, 28 Jan 2026 04:26:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1769603216; x=1770208016; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2qgpD9LbGNFmxJFyhinMbda0sk3N9bu+o/hT9+cSIlY=; b=J8bOyXtCWQ7xFL9PXieKp0SMLRX2j/dPw6NywCxHZmvrRz43SqDTEpQ7Gaatq8V9eN hTIyS1wDov8qoR00iL1lBtXCXSF5rYSl2epg1EQmdIGlH3U8xYLvu7C3PqGlJ8NwKPdR Ib77FzFdax8DgSDRhkWrRFj+Oun/rxcOI6q8BUyLhpDH90z/lpvGab0+wnYJB67F8vP7 C2pGSgkpZ7aH7A4lwr4IT7985HSrVK7No4YBfZnC5+UYrsitUakMmMJf6zCKogdD9OlP uBGDe9wLNYxEQ6ZzpLodRoZhLXua+/ofar+E16d4UiRrZLufMgfNJ7uZo95YonLjsVPG E3Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769603216; x=1770208016; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=2qgpD9LbGNFmxJFyhinMbda0sk3N9bu+o/hT9+cSIlY=; b=r+Lcmw+jAPZpGTQ/WEKLQUpvySa729URIGWfWz3ovTnwXJz8mCiAZYI9L0yejNsivz u0kmLxbaI+ojlHVHv2AYe8qg12zplLE3AY5Tv/xSDcs7xUbZZlI8YOne97RP25h/55iF TXOHu2tEVmRK0f4VnGzbl3YYT7A9WVOx0H2Foc+i3Z6JfWl+0ie12Nrv0dzMn9tCLyDw Et88oLhK9V4uGJ10oDoi2MyxJBEWwdYJX1xUJ+8eyEpPvzazNBlRGsSyK4jHgCtYAscT vXguCc3dUp13+WK4rRlIAkMWQ5WzgPnuQjR8q3MJj3PW25rT3fUVK3XirC/q1I8pNlWp pf3A== X-Forwarded-Encrypted: i=1; AJvYcCVQw2pWG/1L+n1J2/8jcnty3lj8Z5lYR7XSWpsmxyWkNBEjfGge4cn6aBLMmhMoXTWfS+RqUvHOI1NdfIQ=@vger.kernel.org X-Gm-Message-State: AOJu0YxhvLEy6RDTH1ojzFU8eRomJP7gHtQF/tMhCnSWlcQzQlFZGzIj nxGhtH4uA0wd159gNOU9KwgVNPTQajHIta3hzufI1MuFUGm/FMFK2uwve+gbK7KNm8w= X-Gm-Gg: AZuq6aIYdWgjdWJXL55xubBOqhbvpiJmZU4yCcgJhxpghxcltEwvV/1k5RNvGBwsT96 i87PKv4UR8kFol301S/oR7L2LKh9KdMVi4PuZNEoJlsPY1myzKPv8jUUswMDlcYwys9cThZm261 0PTjeqqCusbxJykJ6ExqDNmyZWEgYxF1s/btONp0qV4pGXrSjBUt47f7D/rBWZJAYRY2EHbA8B1 dOG5zdlGcbWnNuGW7vHByF+5o+Z6kmw7/Bl+MRz7/P4NUGfcu9hGZ8GfQB7UofqAZvJmVePvN22 aI0mhWeJhi2/PNRvRhD+Jx4CyGQfI/6AT4IduRytorFJf676oN78aNVHmAqLT4lG15TlAZVhPSA pHkAvbcjOV/qtyxSNtbVwghbXGPnfPFiNswks3e1LjZk5XnY1KNG1kuk1ZWJW3DeMOgm/LXIwbe EkMVhc4CyHnue3cezOrG1Kec/Zpp1MicMj5y6ywjVdq4OFEjkzy2ogRUiYZSx4x95v8g== X-Received: by 2002:a17:907:96a1:b0:b87:1ffc:bfc0 with SMTP id a640c23a62f3a-b8dacc4210dmr371179166b.20.1769603215509; Wed, 28 Jan 2026 04:26:55 -0800 (PST) Received: from [172.16.220.101] (144-178-202-139.static.ef-service.nl. [144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf1baa42sm119536866b.46.2026.01.28.04.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 04:26:54 -0800 (PST) From: Luca Weiss Date: Wed, 28 Jan 2026 13:26:51 +0100 Subject: [PATCH 3/5] pinctrl: qcom: Add SM6350 LPASS LPI TLMM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-sm6350-lpi-tlmm-v1-3-36583f2a2a2a@fairphone.com> References: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> In-Reply-To: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769603212; l=7472; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=aYBhXyfeGAiKcjO0bljvvMwVi3NEa7dlY1olVgUIsz0=; b=Z1sPCnTYjq8e93G9ajmQ1Xt6J8npA69WIKX8ZYM9ToolGZYM1LOfPsFuJqYEDiZ8wdCpGCSA1 d5KNijgtBsBCQX+OqWNISkx4qdzrNv+Y2O02+jsOZFuq0FNJTvSUZwM X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add support for the pin controller block on SM6350 Low Power Island. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/pinctrl/qcom/Kconfig | 9 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c | 149 ++++++++++++++++++++= ++++ 3 files changed, 159 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index f56592411cf6..9010b5879a0b 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -98,6 +98,15 @@ config PINCTRL_SM6115_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SM6115 platfo= rm. =20 +config PINCTRL_SM6350_LPASS_LPI + tristate "Qualcomm Technologies Inc SM6350 LPASS LPI pin controller drive= r" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM6350 platfo= rm. + config PINCTRL_SM8250_LPASS_LPI tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller drive= r" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4269d1781015..ee63035c554c 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_PINCTRL_SM6115) +=3D pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) +=3D pinctrl-sm6115-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM6125) +=3D pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM6350) +=3D pinctrl-sm6350.o +obj-$(CONFIG_PINCTRL_SM6350_LPASS_LPI) +=3D pinctrl-sm6350-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM6375) +=3D pinctrl-sm6375.o obj-$(CONFIG_PINCTRL_SM7150) +=3D pinctrl-sm7150.o obj-$(CONFIG_PINCTRL_SM8150) +=3D pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm6350-lpass-lpi.c new file mode 100644 index 000000000000..4d06abcfedfd --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026, Luca Weiss + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc sm6350_lpi_pins[] =3D { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), +}; + +static const char * const swr_tx_clk_groups[] =3D { "gpio0" }; +static const char * const swr_tx_data_groups[] =3D { "gpio1", "gpio2", "gp= io14" }; +static const char * const swr_rx_clk_groups[] =3D { "gpio3" }; +static const char * const swr_rx_data_groups[] =3D { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] =3D { "gpio6" }; +static const char * const dmic1_data_groups[] =3D { "gpio7" }; +static const char * const dmic2_clk_groups[] =3D { "gpio8" }; +static const char * const dmic2_data_groups[] =3D { "gpio9" }; +static const char * const i2s2_clk_groups[] =3D { "gpio10" }; +static const char * const i2s2_ws_groups[] =3D { "gpio11" }; +static const char * const dmic3_clk_groups[] =3D { "gpio12" }; +static const char * const dmic3_data_groups[] =3D { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] =3D { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] =3D { "gpio1" }; +static const char * const qua_mi2s_data_groups[] =3D { "gpio2", "gpio3", "= gpio4", "gpio5" }; +static const char * const i2s1_clk_groups[] =3D { "gpio6" }; +static const char * const i2s1_ws_groups[] =3D { "gpio7" }; +static const char * const i2s1_data_groups[] =3D { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] =3D { "gpio10" }; +static const char * const wsa_swr_data_groups[] =3D { "gpio11" }; +static const char * const i2s2_data_groups[] =3D { "gpio12", "gpio13" }; + +static const struct lpi_pingroup sm6350_groups[] =3D { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _), + LPI_PINGROUP_SLEW_SPARE_1(14, 0, swr_tx_data, _, _, _), +}; + +static const struct lpi_function sm6350_functions[] =3D { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data sm6350_lpi_data =3D { + .pins =3D sm6350_lpi_pins, + .npins =3D ARRAY_SIZE(sm6350_lpi_pins), + .groups =3D sm6350_groups, + .ngroups =3D ARRAY_SIZE(sm6350_groups), + .functions =3D sm6350_functions, + .nfunctions =3D ARRAY_SIZE(sm6350_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] =3D { + { + .compatible =3D "qcom,sm6350-lpass-lpi-pinctrl", + .data =3D &sm6350_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver =3D { + .driver =3D { + .name =3D "qcom-sm6350-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + }, + .probe =3D lpi_pinctrl_probe, + .remove =3D lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("Qualcomm SM6350 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); --=20 2.52.0