From nobody Tue Feb 10 11:14:41 2026 Received: from mail-ej1-f67.google.com (mail-ej1-f67.google.com [209.85.218.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0B843451CE for ; Wed, 28 Jan 2026 12:26:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.67 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769603220; cv=none; b=dZDbRZKOu2lIKqlfjls1YeYgEdpMBEN8UUPHPE/yPfhXXXPwrQ6AoUcObez47sK7zFV5nMdkTx4sj6DpRy37AhE0R7sNVJC14yKt3EaB4C1l/128JJFIPX5l4hA6lO9QZmozy3bHVmM8mKP6RRngWQc6wWifTQvG73ImVlmz0aw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769603220; c=relaxed/simple; bh=qkR3N/gsmXgYO2JfgTiDk4iF41iC5S+pPDgTyzbp068=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XeZdTZap9t/3mGOLa7rnJNW+e3qUP3ctnm7AAk8fs2okW+aZXrL/uOWZ9W6SDximfzdxIWrubl3/Weu0kcru/Pv1/tPqaO1HhmDxhE2Co5lzpTQ/DEkHhlPYMwkzUJHiRamNts/yhduCzm2tgTY+ujwyq+fAP9kdS8iS7fE2ZmY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=5hl43f8t; arc=none smtp.client-ip=209.85.218.67 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="5hl43f8t" Received: by mail-ej1-f67.google.com with SMTP id a640c23a62f3a-b8863db032dso863084566b.0 for ; Wed, 28 Jan 2026 04:26:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1769603214; x=1770208014; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2jzxQ31iaqft+vnkSfOSrEvDmT77JQeklbr0dv7ayhI=; b=5hl43f8tCT+fXFyJnWSVbtiDKCcAqmUka7mwUc/CLWGJjrnRGoaLoAB68aZ3gs4LdI CqXxVEqhzLB62jnDGc/V98sPF6ItSJfb2xCDb4RGU5sEMGR1n8OTZZ6EvOhpQFAMqCZS xjC1ginQaW2G4VTTS+7xvq0rjHuUzstpHECd8/DhW5rlFPju402deJnCArhXR+V4IXv2 eDwDV4PFj/FvqjvXDMTnnbv3hnL1DpfJb4NNXRFJabpLFqHzjFpjaTOA5cX3SH16Qm2g x3duLwhIudFhZ6mlypxpGGG8LLVY2cqudTk+55QzAmILbYojRx4QLBeAJUZY7up6EUfG 5IgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769603214; x=1770208014; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=2jzxQ31iaqft+vnkSfOSrEvDmT77JQeklbr0dv7ayhI=; b=jAEkNmYmCtrtOgvsyacmeXwvMe+CktB4CT7nm2THaGxlIoWK4VlJGAjEaC2S/Zt8uu sev2BgSGmfTeAZZCa/QVMvugMvYabGSinsJACWATJ8FW5SJpUgd+xXKqtMCzwlEmIW3k WcYmAIEFGCaLMoL2rUZJm/iqZwVl4tqZ2yZpwvwJ1uKuQBx8oUPk0JFmLBLT1fd7kZr1 WJrfoKF/e+BNJVWNDGRiR8O9tcWABSkyYMRwgB+v9mC2i/ZRFUn0uc5fqaeIJ/+P3sus SKu9eGkUXY6vCuSExLyuy1sIuRmZtCVoRv6As3fDu12kmTM6Dki6bPAoffCmyAxmGJmh qxzQ== X-Forwarded-Encrypted: i=1; AJvYcCVUEgVGdK6NNkJwhAKjGOKFsKQ0t5wvUQYdSUEgq+g5zlGPvK7nGC6HquAKE4TtRqdfVX3AENy7Xeoh+Qg=@vger.kernel.org X-Gm-Message-State: AOJu0Yxkz2HzDPaGlHUHVS3qd1OAXcJF2XUAaNFhR2n5Ueb+WpPLgp2Y 1ly2uko9xoftZVaFzS1VUHvedbIP0Ys1sFWH9RfwfjFt6SAexGHCM6vETBMX8gkHA5w= X-Gm-Gg: AZuq6aIYiCuxaER2ufNX3b0oQ7sipUaWwslZVtCIn1m/1EqpPVVfJpX0+aIk87tDWhH yYyDMtNGq7MxQHNrseo5KbC7drSV4Ugo+wMh1Ya7ZVXCQW5Nc/AwAscw4zLxXnhJEQYkFnBpAQA Oi2bHQmXwARtOP2AiYaKAHoVVXp4VcB4I7xH8waEsfhZNhIQ7Hn9lkOuIr6qgRn2X+ve4g99CEj MfBzBi7ObGvL5VzIvPDm/zhN1dCTe7ZOV7jxSMnCXBF7aPM2k0ib99VovJnlxooVpk9A3hjI3B3 xnCJmO4PWE5EWlFyeq+IaIFqS/MVCYth9D9mRf+eo+AC4WX+HOayYtsfmgHPAj3fvCmzY7KoHaB z32ntKXNCYvaLZ/Da/Xnz595ItDLoqg50GF85qfFXasgf79347rIO0Zv3WceW68wNXPQESL0SUp Cm5R+gqegyYcj9/a6oCZqNTbmqbD2Ueh6TVpmX5mByrmDZ2sB+YUgTqxlaifWg/WSGwA== X-Received: by 2002:a17:907:c807:b0:b7a:1bde:a01a with SMTP id a640c23a62f3a-b8dab3cfca5mr370108866b.62.1769603214620; Wed, 28 Jan 2026 04:26:54 -0800 (PST) Received: from [172.16.220.101] (144-178-202-139.static.ef-service.nl. [144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf1baa42sm119536866b.46.2026.01.28.04.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 04:26:54 -0800 (PST) From: Luca Weiss Date: Wed, 28 Jan 2026 13:26:50 +0100 Subject: [PATCH 2/5] pinctrl: qcom: lpass-lpi: Add ability to use SPARE_1 for slew control Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-sm6350-lpi-tlmm-v1-2-36583f2a2a2a@fairphone.com> References: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> In-Reply-To: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769603212; l=2683; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=qkR3N/gsmXgYO2JfgTiDk4iF41iC5S+pPDgTyzbp068=; b=D03/QgscWazU563APEDJzM7rEkI223CiQQFxLqunbjc4WLt6AEk/9Rcq6Fo7fPo/PsMFqsCIA aY6xDo9C375CY9IyyCLXn67jvPq9wusbNMRO5nHBoS2ZwcxH22VIlga X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= On some platforms like SM6350 (Bitra), some pins have their slew controlled with the SPARE_1 register - probably because they ran out of register space for an extra pin. Add support for that. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 ++ drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 76aed3296279..15ced5027579 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -220,6 +220,8 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl = *pctrl, =20 if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG) reg =3D pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_RE= G; + else if (g->slew_base_spare_1) + reg =3D pctrl->slew_base + LPI_SPARE_1_REG; else reg =3D pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; =20 diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.h index f48368492861..6ba0c4eba984 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -16,6 +16,7 @@ struct platform_device; struct pinctrl_pin_desc; =20 #define LPI_SLEW_RATE_CTL_REG 0xa000 +#define LPI_SPARE_1_REG 0xc000 #define LPI_TLMM_REG_OFFSET 0x1000 #define LPI_SLEW_RATE_MAX 0x03 #define LPI_SLEW_BITS_SIZE 0x02 @@ -47,6 +48,7 @@ struct pinctrl_pin_desc; { \ .pin =3D id, \ .slew_offset =3D soff, \ + .slew_base_spare_1 =3D false, \ .funcs =3D (int[]){ \ LPI_MUX_gpio, \ LPI_MUX_##f1, \ @@ -62,6 +64,7 @@ struct pinctrl_pin_desc; { \ .pin =3D id, \ .slew_offset =3D soff, \ + .slew_base_spare_1 =3D false, \ .funcs =3D (int[]){ \ LPI_MUX_gpio, \ LPI_MUX_##f1, \ @@ -73,6 +76,22 @@ struct pinctrl_pin_desc; .pin_offset =3D poff, \ } =20 +#define LPI_PINGROUP_SLEW_SPARE_1(id, soff, f1, f2, f3, f4) \ + { \ + .pin =3D id, \ + .slew_offset =3D soff, \ + .slew_base_spare_1 =3D true, \ + .funcs =3D (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + }, \ + .nfuncs =3D 5, \ + .pin_offset =3D 0, \ + } + /* * Slew rate control is done in the same register as rest of the * pin configuration. @@ -87,6 +106,7 @@ struct lpi_pingroup { unsigned int *funcs; unsigned int nfuncs; unsigned int pin_offset; + bool slew_base_spare_1; }; =20 struct lpi_function { --=20 2.52.0