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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf1baa42sm119536866b.46.2026.01.28.04.26.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 04:26:53 -0800 (PST) From: Luca Weiss Date: Wed, 28 Jan 2026 13:26:49 +0100 Subject: [PATCH 1/5] dt-bindings: pinctrl: qcom: Add SM6350 LPI pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-sm6350-lpi-tlmm-v1-1-36583f2a2a2a@fairphone.com> References: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> In-Reply-To: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769603212; l=4248; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=hJzi+1WVJi3bViEFfHTLerRF56fSuL0dTkBkrX7hZ2g=; b=lIHYjQ0cXxLLwj1T5hLZ2ritI4/NmHhGE1D5u6eSjvyTteYEuDnEs46ziWjOyej1zWV6sV2uR kJu2vPZOI8IAUG7IzFiZCrLTjWVw7Dieku7WJfS80m9UIGV8oXDJyC8 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add bindings for pin controller in Low Power Audio SubSystem (LPASS). Signed-off-by: Luca Weiss --- .../pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml | 124 +++++++++++++++++= ++++ 1 file changed, 124 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lp= i-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpas= s-lpi-pinctrl.yaml new file mode 100644 index 000000000000..2fa2484e7bc7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinct= rl.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 SoC LPASS LPI TLMM + +maintainers: + - Luca Weiss + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSyst= em + (LPASS) Low Power Island (LPI) of Qualcomm SM6350 SoC. + +properties: + compatible: + const: qcom,sm6350-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm6350-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm6350-lpass-state" + additionalProperties: false + +$defs: + qcom-sm6350-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-4])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, gpio, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, qua_mi2s_data, qua_mi2s_sclk, qua_mi2s= _ws, + swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_= clk, + wsa_swr_data ] + description: + Specify the alternative function to be configured for the specif= ied + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + lpass_tlmm: pinctrl@33c0000 { + compatible =3D "qcom,sm6350-lpass-lpi-pinctrl"; + reg =3D <0x033c0000 0x20000>, + <0x03550000 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 15>; + + clocks =3D <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPL= E_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE= _NO>; + clock-names =3D "core", + "audio"; + + i2s1_active: i2s1-active-pins { + clk { + pins =3D "gpio6"; + function =3D "i2s1_clk"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + + ws { + pins =3D "gpio7"; + function =3D "i2s1_ws"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + + data { + pins =3D "gpio8", "gpio9"; + function =3D "i2s1_data"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + }; + }; --=20 2.52.0 From nobody Sat Feb 7 05:56:16 2026 Received: from mail-ej1-f67.google.com (mail-ej1-f67.google.com [209.85.218.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0B843451CE for ; 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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf1baa42sm119536866b.46.2026.01.28.04.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 04:26:54 -0800 (PST) From: Luca Weiss Date: Wed, 28 Jan 2026 13:26:50 +0100 Subject: [PATCH 2/5] pinctrl: qcom: lpass-lpi: Add ability to use SPARE_1 for slew control Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-sm6350-lpi-tlmm-v1-2-36583f2a2a2a@fairphone.com> References: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> In-Reply-To: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769603212; l=2683; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=qkR3N/gsmXgYO2JfgTiDk4iF41iC5S+pPDgTyzbp068=; b=D03/QgscWazU563APEDJzM7rEkI223CiQQFxLqunbjc4WLt6AEk/9Rcq6Fo7fPo/PsMFqsCIA aY6xDo9C375CY9IyyCLXn67jvPq9wusbNMRO5nHBoS2ZwcxH22VIlga X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= On some platforms like SM6350 (Bitra), some pins have their slew controlled with the SPARE_1 register - probably because they ran out of register space for an extra pin. Add support for that. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 ++ drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 76aed3296279..15ced5027579 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -220,6 +220,8 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl = *pctrl, =20 if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG) reg =3D pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_RE= G; + else if (g->slew_base_spare_1) + reg =3D pctrl->slew_base + LPI_SPARE_1_REG; else reg =3D pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; =20 diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.h index f48368492861..6ba0c4eba984 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -16,6 +16,7 @@ struct platform_device; struct pinctrl_pin_desc; =20 #define LPI_SLEW_RATE_CTL_REG 0xa000 +#define LPI_SPARE_1_REG 0xc000 #define LPI_TLMM_REG_OFFSET 0x1000 #define LPI_SLEW_RATE_MAX 0x03 #define LPI_SLEW_BITS_SIZE 0x02 @@ -47,6 +48,7 @@ struct pinctrl_pin_desc; { \ .pin =3D id, \ .slew_offset =3D soff, \ + .slew_base_spare_1 =3D false, \ .funcs =3D (int[]){ \ LPI_MUX_gpio, \ LPI_MUX_##f1, \ @@ -62,6 +64,7 @@ struct pinctrl_pin_desc; { \ .pin =3D id, \ .slew_offset =3D soff, \ + .slew_base_spare_1 =3D false, \ .funcs =3D (int[]){ \ LPI_MUX_gpio, \ LPI_MUX_##f1, \ @@ -73,6 +76,22 @@ struct pinctrl_pin_desc; .pin_offset =3D poff, \ } =20 +#define LPI_PINGROUP_SLEW_SPARE_1(id, soff, f1, f2, f3, f4) \ + { \ + .pin =3D id, \ + .slew_offset =3D soff, \ + .slew_base_spare_1 =3D true, \ + .funcs =3D (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + }, \ + .nfuncs =3D 5, \ + .pin_offset =3D 0, \ + } + /* * Slew rate control is done in the same register as rest of the * pin configuration. @@ -87,6 +106,7 @@ struct lpi_pingroup { unsigned int *funcs; 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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf1baa42sm119536866b.46.2026.01.28.04.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 04:26:54 -0800 (PST) From: Luca Weiss Date: Wed, 28 Jan 2026 13:26:51 +0100 Subject: [PATCH 3/5] pinctrl: qcom: Add SM6350 LPASS LPI TLMM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-sm6350-lpi-tlmm-v1-3-36583f2a2a2a@fairphone.com> References: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> In-Reply-To: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769603212; l=7472; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=aYBhXyfeGAiKcjO0bljvvMwVi3NEa7dlY1olVgUIsz0=; b=Z1sPCnTYjq8e93G9ajmQ1Xt6J8npA69WIKX8ZYM9ToolGZYM1LOfPsFuJqYEDiZ8wdCpGCSA1 d5KNijgtBsBCQX+OqWNISkx4qdzrNv+Y2O02+jsOZFuq0FNJTvSUZwM X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add support for the pin controller block on SM6350 Low Power Island. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/pinctrl/qcom/Kconfig | 9 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c | 149 ++++++++++++++++++++= ++++ 3 files changed, 159 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index f56592411cf6..9010b5879a0b 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -98,6 +98,15 @@ config PINCTRL_SM6115_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SM6115 platfo= rm. =20 +config PINCTRL_SM6350_LPASS_LPI + tristate "Qualcomm Technologies Inc SM6350 LPASS LPI pin controller drive= r" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SM6350 platfo= rm. + config PINCTRL_SM8250_LPASS_LPI tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller drive= r" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4269d1781015..ee63035c554c 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_PINCTRL_SM6115) +=3D pinctrl-sm6115.o obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) +=3D pinctrl-sm6115-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM6125) +=3D pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM6350) +=3D pinctrl-sm6350.o +obj-$(CONFIG_PINCTRL_SM6350_LPASS_LPI) +=3D pinctrl-sm6350-lpass-lpi.o obj-$(CONFIG_PINCTRL_SM6375) +=3D pinctrl-sm6375.o obj-$(CONFIG_PINCTRL_SM7150) +=3D pinctrl-sm7150.o obj-$(CONFIG_PINCTRL_SM8150) +=3D pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm6350-lpass-lpi.c new file mode 100644 index 000000000000..4d06abcfedfd --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6350-lpass-lpi.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026, Luca Weiss + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_qua_mi2s_data, + LPI_MUX_qua_mi2s_sclk, + LPI_MUX_qua_mi2s_ws, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc sm6350_lpi_pins[] =3D { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), +}; + +static const char * const swr_tx_clk_groups[] =3D { "gpio0" }; +static const char * const swr_tx_data_groups[] =3D { "gpio1", "gpio2", "gp= io14" }; +static const char * const swr_rx_clk_groups[] =3D { "gpio3" }; +static const char * const swr_rx_data_groups[] =3D { "gpio4", "gpio5" }; +static const char * const dmic1_clk_groups[] =3D { "gpio6" }; +static const char * const dmic1_data_groups[] =3D { "gpio7" }; +static const char * const dmic2_clk_groups[] =3D { "gpio8" }; +static const char * const dmic2_data_groups[] =3D { "gpio9" }; +static const char * const i2s2_clk_groups[] =3D { "gpio10" }; +static const char * const i2s2_ws_groups[] =3D { "gpio11" }; +static const char * const dmic3_clk_groups[] =3D { "gpio12" }; +static const char * const dmic3_data_groups[] =3D { "gpio13" }; +static const char * const qua_mi2s_sclk_groups[] =3D { "gpio0" }; +static const char * const qua_mi2s_ws_groups[] =3D { "gpio1" }; +static const char * const qua_mi2s_data_groups[] =3D { "gpio2", "gpio3", "= gpio4", "gpio5" }; +static const char * const i2s1_clk_groups[] =3D { "gpio6" }; +static const char * const i2s1_ws_groups[] =3D { "gpio7" }; +static const char * const i2s1_data_groups[] =3D { "gpio8", "gpio9" }; +static const char * const wsa_swr_clk_groups[] =3D { "gpio10" }; +static const char * const wsa_swr_data_groups[] =3D { "gpio11" }; +static const char * const i2s2_data_groups[] =3D { "gpio12", "gpio13" }; + +static const struct lpi_pingroup sm6350_groups[] =3D { + LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, _, qua_mi2s_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, _, _), + LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, _, _), + LPI_PINGROUP_SLEW_SPARE_1(14, 0, swr_tx_data, _, _, _), +}; + +static const struct lpi_function sm6350_functions[] =3D { + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(qua_mi2s_data), + LPI_FUNCTION(qua_mi2s_sclk), + LPI_FUNCTION(qua_mi2s_ws), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data sm6350_lpi_data =3D { + .pins =3D sm6350_lpi_pins, + .npins =3D ARRAY_SIZE(sm6350_lpi_pins), + .groups =3D sm6350_groups, + .ngroups =3D ARRAY_SIZE(sm6350_groups), + .functions =3D sm6350_functions, + .nfunctions =3D ARRAY_SIZE(sm6350_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] =3D { + { + .compatible =3D "qcom,sm6350-lpass-lpi-pinctrl", + .data =3D &sm6350_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver =3D { + .driver =3D { + .name =3D "qcom-sm6350-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + }, + .probe =3D lpi_pinctrl_probe, + .remove =3D lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("Qualcomm SM6350 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); --=20 2.52.0 From nobody Sat Feb 7 05:56:16 2026 Received: from mail-ej1-f66.google.com (mail-ej1-f66.google.com [209.85.218.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B90834F468 for ; Wed, 28 Jan 2026 12:26:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.66 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769603223; cv=none; b=EIsnYvu8bjKkDzoCPRW3WTDYk5uy0E7rr5eUUqUW3DQ9kmqwyRylZH++brkljcw4fX5khM1lussK7ixweaRlzqLJH80uwJhrXi2W7XmWUDJR4SkDmtB2eG2cUXnHzjQksmG9Ep0Q2SnEryxsbdqRY2f3zMu6hrQsjngV55np/5M= ARC-Message-Signature: i=1; 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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf1baa42sm119536866b.46.2026.01.28.04.26.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 04:26:55 -0800 (PST) From: Luca Weiss Date: Wed, 28 Jan 2026 13:26:52 +0100 Subject: [PATCH 4/5] arm64: dts: qcom: sm6350: add LPASS LPI pin controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-sm6350-lpi-tlmm-v1-4-36583f2a2a2a@fairphone.com> References: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> In-Reply-To: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769603212; l=2150; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=DAIXJZLgc99QDCiZ1C54DNaCXxm8xbhdrA2aDX9YeRs=; b=D91UBY5cJfLVMutL2lsGmg1v4mvGKWsRzbXpEV4eu/U4K9lh0e5fm7C+ouiiz0kgmE3NtTPM0 6L9OFAXNAvxDq12KGz1dCTCCPaJ3gME7iJyvbMthwVmtBDUV92lcK72 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add LPASS LPI pinctrl node required for audio functionality on SM6350. Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 9f9b9f9af0da..b1fb6c812da7 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1448,6 +1448,72 @@ compute-cb@5 { }; }; =20 + lpass_tlmm: pinctrl@33c0000 { + compatible =3D "qcom,sm6350-lpass-lpi-pinctrl"; + reg =3D <0x0 0x033c0000 0x0 0x20000>, + <0x0 0x03550000 0x0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 15>; + + clocks =3D <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", + "audio"; + + i2s1_active: i2s1-active-state { + clk-pins { + pins =3D "gpio6"; + function =3D "i2s1_clk"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins =3D "gpio7"; + function =3D "i2s1_ws"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + + data-pins { + pins =3D "gpio8", "gpio9"; + function =3D "i2s1_data"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + }; + + i2s1_sleep: i2s1-sleep-state { + clk-pins { + pins =3D "gpio6"; + function =3D "i2s1_clk"; + drive-strength =3D <2>; + bias-pull-down; + input-enable; + }; + + ws-pins { + pins =3D "gpio7"; + function =3D "i2s1_ws"; + drive-strength =3D <2>; + bias-pull-down; + input-enable; + }; + + data-pins { + pins =3D "gpio8", "gpio9"; + function =3D "i2s1_data"; + drive-strength =3D <2>; + bias-pull-down; + input-enable; + }; + }; + }; + gpu: gpu@3d00000 { compatible =3D "qcom,adreno-619.0", "qcom,adreno"; reg =3D <0x0 0x03d00000 0x0 0x40000>, --=20 2.52.0 From nobody Sat Feb 7 05:56:16 2026 Received: from mail-ed1-f65.google.com (mail-ed1-f65.google.com [209.85.208.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CD8126F28A for ; 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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf1baa42sm119536866b.46.2026.01.28.04.26.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 04:26:56 -0800 (PST) From: Luca Weiss Date: Wed, 28 Jan 2026 13:26:53 +0100 Subject: [PATCH 5/5] arm64: defconfig: Enable LPASS LPI pin controller for SM6350 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-sm6350-lpi-tlmm-v1-5-36583f2a2a2a@fairphone.com> References: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> In-Reply-To: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769603212; l=778; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=6q37WeeQdbfyWtDQufhuNOaDmHWFyJ3gZhhYFvngdNU=; b=O2JhrNZ4cx0yR4rIclFuPK5si3IJLYw2s5Eatlepxy7kLpFKU0/o9C0bpUkv9kgglYZW4StSQ pnf0PMnNfZeBCJmTjmFtj3Uh+/chxTyFPoXE08AMOzWjHIem6EMS5tE X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Build the LPASS LPI pin controller driver for SM6350 as module, which is required for audio functionality on boards such as the Fairphone 4. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7a6d7e70d383..5160b81afc6b 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -694,6 +694,7 @@ CONFIG_PINCTRL_QCOM_SPMI_PMIC=3Dy CONFIG_PINCTRL_LPASS_LPI=3Dm CONFIG_PINCTRL_SC7280_LPASS_LPI=3Dm CONFIG_PINCTRL_SM6115_LPASS_LPI=3Dm +CONFIG_PINCTRL_SM6350_LPASS_LPI=3Dm CONFIG_PINCTRL_SM8250_LPASS_LPI=3Dm CONFIG_PINCTRL_SM8450_LPASS_LPI=3Dm CONFIG_PINCTRL_SC8280XP_LPASS_LPI=3Dm --=20 2.52.0