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Tue, 27 Jan 2026 11:26:58 -0800 (PST) Received: from hu-jkona-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a88b414fc4sm1322225ad.32.2026.01.27.11.26.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jan 2026 11:26:58 -0800 (PST) From: Jagadeesh Kona Date: Wed, 28 Jan 2026 00:56:34 +0530 Subject: [PATCH 3/8] clk: qcom: videocc-x1p42100: Add support for video clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-purwa-videocc-camcc-v1-3-b23de57df5ba@oss.qualcomm.com> References: <20260128-purwa-videocc-camcc-v1-0-b23de57df5ba@oss.qualcomm.com> In-Reply-To: <20260128-purwa-videocc-camcc-v1-0-b23de57df5ba@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jagadeesh Kona , Bryan O'Donoghue , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jagadeesh Kona X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI3MDE1OCBTYWx0ZWRfX3rVjiSIpgeOR /WOAUJ0OVIx+MJmoD2Rs0rYYEJWdLOT/wkzwXbJMlLbFyGkw1+h2+TVbm9Corj/gvq+i6yMwoXh fA2suPkgqpiRLqXFs04kc/qNQJJMh1utfIC5HaRoXWn9Suhluha07OqEod0zgGuvqYhdEfGwYjN gX+O+8NCTtTKxZ45uqTJDrwAEz2/iA3HOz3bT6hA6RV2Og61+kTigyhPRWx9cUETjz6kqILps1R ifPQcODUXsar/e1nrNjySFtkzyVTdgNXeXq4zZsoV+w655O1NEnUVdgtwY1DxgImV8bZOHvDMwJ +ZovnhlNjFny09qfMG1yFSnONF7XbF7gi56K0VRDtrT05HN3XubbSLFPd7gxR4BzfkKT/glJzhz DgKL5XMhQP0ufZj8qTV+0bbnFNv7NZtI6BP4uRmyEPUC/A1WqtGDF8ba4BnbThn1MW67sEn+7kq drRAifAV5sj5xVkGpEw== X-Authority-Analysis: v=2.4 cv=Qelrf8bv c=1 sm=1 tr=0 ts=69791185 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=RKjULyPvNO9injS1lHcA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: UgJo_0tqEzHG0KQgMc9INMVCkARsaJoJ X-Proofpoint-GUID: UgJo_0tqEzHG0KQgMc9INMVCkARsaJoJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-27_04,2026-01-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 adultscore=0 phishscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601270158 Add support for the video clock controller for video clients to be able to request for videocc clocks on X1P42100 platform. Signed-off-by: Jagadeesh Kona Reviewed-by: Taniya Das --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-x1p42100.c | 585 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 596 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index a8a86ea6bb7445e396048a5bba23fce8d719281f..b1b1ed70871c1b348985d6f5149= 152e57637d904 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -155,6 +155,16 @@ config CLK_X1P42100_GPUCC Say Y if you want to support graphics controller devices and functionality such as 3D graphics. =20 +config CLK_X1P42100_VIDEOCC + tristate "X1P42100 Video Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_X1E80100_GCC + help + Support for the video clock controller on Qualcomm Technologies, Inc. + X1P42100 devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. + config CLK_QCM2290_GPUCC tristate "QCM2290 Graphics Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 6b0ad8832b55f1914079f15323b8cdd1608ad4c0..b746e5046774259cebe3da8dad1= f226561268a8b 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_X1E80100_GCC) +=3D gcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GPUCC) +=3D gpucc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_TCSRCC) +=3D tcsrcc-x1e80100.o obj-$(CONFIG_CLK_X1P42100_GPUCC) +=3D gpucc-x1p42100.o +obj-$(CONFIG_CLK_X1P42100_VIDEOCC) +=3D videocc-x1p42100.o obj-$(CONFIG_CLK_QCM2290_GPUCC) +=3D gpucc-qcm2290.o obj-$(CONFIG_IPQ_APSS_PLL) +=3D apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_5424) +=3D apss-ipq5424.o diff --git a/drivers/clk/qcom/videocc-x1p42100.c b/drivers/clk/qcom/videocc= -x1p42100.c new file mode 100644 index 0000000000000000000000000000000000000000..2bb40ac6fcc57e817ce8f0b6727= a571c7c072ffa --- /dev/null +++ b/drivers/clk/qcom/videocc-x1p42100.c @@ -0,0 +1,585 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, +}; + +enum { + P_BI_TCXO, + P_VIDEO_CC_PLL0_OUT_MAIN, + P_VIDEO_CC_PLL1_OUT_MAIN, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +/* 420.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll0_config =3D { + .l =3D 0x15, + .alpha =3D 0xe000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll video_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &video_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1050.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll1_config =3D { + .l =3D 0x36, + .alpha =3D 0xb000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000005, +}; + +static struct clk_alpha_pll video_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &video_cc_pll1_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll0.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL1_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll1.clkr.hw }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_bse_clk_src[] =3D { + F(420000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(670000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(848000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(920000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_bse_clk_src =3D { + .cmd_rcgr =3D 0x8154, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_mvs0_bse_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_bse_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] =3D { + F(210000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(300000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(335000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(424000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), + F(460000000, P_VIDEO_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src =3D { + .cmd_rcgr =3D 0x8000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_mvs0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] =3D { + F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs1_clk_src =3D { + .cmd_rcgr =3D 0x8018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_2, + .freq_tbl =3D ftbl_video_cc_mvs1_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_clk_src", + .parent_data =3D video_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_xo_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x810c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_xo_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_xo_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs0_bse_div4_div_clk_src =3D { + .reg =3D 0x817c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_bse_div4_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_bse_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1_div_clk_src =3D { + .reg =3D 0x80ec, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src =3D { + .reg =3D 0x809c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1c_div2_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_bse_clk =3D { + .halt_reg =3D 0x8170, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8170, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_bse_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_bse_div4_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_clk =3D { + .halt_reg =3D 0x80b8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80b8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_shift_clk =3D { + .halt_reg =3D 0x8128, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8128, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk =3D { + .halt_reg =3D 0x8064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_shift_clk =3D { + .halt_reg =3D 0x812c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x812c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_clk =3D { + .halt_reg =3D 0x80e0, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80e0, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80e0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1_shift_clk =3D { + .halt_reg =3D 0x8130, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8130, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1c_clk =3D { + .halt_reg =3D 0x8090, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1c_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs1c_div2_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs1c_shift_clk =3D { + .halt_reg =3D 0x8134, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8134, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs1c_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc video_cc_mvs0c_gdsc =3D { + .gdscr =3D 0x804c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0c_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_gdsc =3D { + .gdscr =3D 0x80a4, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &video_cc_mvs0c_gdsc.pd, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs1c_gdsc =3D { + .gdscr =3D 0x8078, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "video_cc_mvs1c_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs1_gdsc =3D { + .gdscr =3D 0x80cc, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "video_cc_mvs1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &video_cc_mvs1c_gdsc.pd, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *video_cc_x1p42100_clocks[] =3D { + [VIDEO_CC_MVS0_BSE_CLK] =3D &video_cc_mvs0_bse_clk.clkr, + [VIDEO_CC_MVS0_BSE_CLK_SRC] =3D &video_cc_mvs0_bse_clk_src.clkr, + [VIDEO_CC_MVS0_BSE_DIV4_DIV_CLK_SRC] =3D &video_cc_mvs0_bse_div4_div_clk_= src.clkr, + [VIDEO_CC_MVS0_CLK] =3D &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] =3D &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_SHIFT_CLK] =3D &video_cc_mvs0_shift_clk.clkr, + [VIDEO_CC_MVS0C_CLK] =3D &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_SHIFT_CLK] =3D &video_cc_mvs0c_shift_clk.clkr, + [VIDEO_CC_MVS1_CLK] =3D &video_cc_mvs1_clk.clkr, + [VIDEO_CC_MVS1_CLK_SRC] =3D &video_cc_mvs1_clk_src.clkr, + [VIDEO_CC_MVS1_DIV_CLK_SRC] =3D &video_cc_mvs1_div_clk_src.clkr, + [VIDEO_CC_MVS1_SHIFT_CLK] =3D &video_cc_mvs1_shift_clk.clkr, + [VIDEO_CC_MVS1C_CLK] =3D &video_cc_mvs1c_clk.clkr, + [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] =3D &video_cc_mvs1c_div2_div_clk_src.cl= kr, + [VIDEO_CC_MVS1C_SHIFT_CLK] =3D &video_cc_mvs1c_shift_clk.clkr, + [VIDEO_CC_PLL0] =3D &video_cc_pll0.clkr, + [VIDEO_CC_PLL1] =3D &video_cc_pll1.clkr, + [VIDEO_CC_XO_CLK_SRC] =3D &video_cc_xo_clk_src.clkr, +}; + +static struct gdsc *video_cc_x1p42100_gdscs[] =3D { + [VIDEO_CC_MVS0_GDSC] =3D &video_cc_mvs0_gdsc, + [VIDEO_CC_MVS0C_GDSC] =3D &video_cc_mvs0c_gdsc, + [VIDEO_CC_MVS1_GDSC] =3D &video_cc_mvs1_gdsc, + [VIDEO_CC_MVS1C_GDSC] =3D &video_cc_mvs1c_gdsc, +}; + +static const struct qcom_reset_map video_cc_x1p42100_resets[] =3D { + [CVP_VIDEO_CC_INTERFACE_BCR] =3D { 0x80f0 }, + [CVP_VIDEO_CC_MVS0_BCR] =3D { 0x80a0 }, + [CVP_VIDEO_CC_MVS0C_BCR] =3D { 0x8048 }, + [CVP_VIDEO_CC_MVS1_BCR] =3D { 0x80c8 }, + [CVP_VIDEO_CC_MVS1C_BCR] =3D { 0x8074 }, + [VIDEO_CC_MVS0_BSE_BCR] =3D { 0x816c }, + [VIDEO_CC_MVS0C_CLK_ARES] =3D { 0x8064, 2 }, + [VIDEO_CC_MVS1C_CLK_ARES] =3D { 0x8090, 2 }, + [VIDEO_CC_XO_CLK_ARES] =3D { 0x8124, 2 }, +}; + +static struct clk_alpha_pll *video_cc_x1p42100_plls[] =3D { + &video_cc_pll0, + &video_cc_pll1, +}; + +static u32 video_cc_x1p42100_critical_cbcrs[] =3D { + 0x80f4, /* VIDEO_CC_AHB_CLK */ + 0x8150, /* VIDEO_CC_SLEEP_CLK */ + 0x8124, /* VIDEO_CC_XO_CLK */ +}; + +static const struct regmap_config video_cc_x1p42100_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9f54, + .fast_io =3D true, +}; + +static struct qcom_cc_driver_data video_cc_x1p42100_driver_data =3D { + .alpha_plls =3D video_cc_x1p42100_plls, + .num_alpha_plls =3D ARRAY_SIZE(video_cc_x1p42100_plls), + .clk_cbcrs =3D video_cc_x1p42100_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(video_cc_x1p42100_critical_cbcrs), +}; + +static const struct qcom_cc_desc video_cc_x1p42100_desc =3D { + .config =3D &video_cc_x1p42100_regmap_config, + .clks =3D video_cc_x1p42100_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_x1p42100_clocks), + .resets =3D video_cc_x1p42100_resets, + .num_resets =3D ARRAY_SIZE(video_cc_x1p42100_resets), + .gdscs =3D video_cc_x1p42100_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_x1p42100_gdscs), + .use_rpm =3D true, + .driver_data =3D &video_cc_x1p42100_driver_data, +}; + +static const struct of_device_id video_cc_x1p42100_match_table[] =3D { + { .compatible =3D "qcom,x1p42100-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_x1p42100_match_table); + +static int video_cc_x1p42100_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &video_cc_x1p42100_desc); +} + +static struct platform_driver video_cc_x1p42100_driver =3D { + .probe =3D video_cc_x1p42100_probe, + .driver =3D { + .name =3D "videocc-x1p42100", + .of_match_table =3D video_cc_x1p42100_match_table, + }, +}; + +module_platform_driver(video_cc_x1p42100_driver); + +MODULE_DESCRIPTION("QTI VIDEOCC X1P42100 Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1