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Wed, 28 Jan 2026 03:57:24 -0500 (EST) From: Janne Grunau Date: Wed, 28 Jan 2026 09:57:08 +0100 Subject: [PATCH v2 1/2] dt-bindings: interrupt-controller: apple,aic2: Add AICv3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-irq-apple-aic3-v2-1-b4bc8e16c997@jannau.net> References: <20260128-irq-apple-aic3-v2-0-b4bc8e16c997@jannau.net> In-Reply-To: <20260128-irq-apple-aic3-v2-0-b4bc8e16c997@jannau.net> To: Sven Peter , Neal Gompa , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3408; i=j@jannau.net; s=yk2025; h=from:subject:message-id; bh=7rYWOaAxEQ+tfxwVBs89sgYINPPcGPnwXDpwGQLDa90=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhszK8wUR86+HPH6iki57Ki1E2rshJF9R1LQ2u+P/EdszV YE2VXc6SlkYxLgYZMUUWZK0X3YwrK5RjKl9EAYzh5UJZAgDF6cATCRDnZFhs0sLX+dWs/OsF+bM /y3LnmohUCv81DPcSnxuvWvpm475jAwXlYL3ud/VCf4cvuGTW0ddO8Pn3gvtCZPeaffaOBYx7GM EAA== X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 AIC version 3 as found on the Apple M3 (t8122) is very similar to AICv2 in its base functionality. It can use the same device tree bindings as AICv2 so add it to the AICv2 bindings. This interrupt controller is used on all Apple SoCs starting with M3 up to at least M5. The only apparent difference is the increased IRQ config offset. Apple's device tree codes this new offset as property of the "aic" node but the value stayed constant for all SoCs with "aic,3". Since the SoC specific compatible "apple,t8122-aic3" will be used in the driver this offset can remain a driver implementation detail. Signed-off-by: Janne Grunau --- .../bindings/interrupt-controller/apple,aic2.yaml | 45 +++++++++++++++++-= ---- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,a= ic2.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic= 2.yaml index ee5a0dfff437816056bda0de5523bf38be4f49ba..a6e2251fcc111340c0a27ab6912= 452f6b1255be2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml @@ -4,10 +4,10 @@ $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Apple Interrupt Controller 2 +title: Apple Interrupt Controller 2 and 3 =20 maintainers: - - Hector Martin + - Janne Grunau =20 description: | The Apple Interrupt Controller 2 is a simple interrupt controller presen= t on @@ -28,14 +28,24 @@ description: | which do not go through a discrete interrupt controller. It also handles FIQ-based Fast IPIs. =20 + The Apple Interrupt Controller 3 is in its base functionality very simil= ar to + the Apple Interrupt Controller 2 and uses the same device tree bindings.= It is + found on Apple ARM SoCs platforms starting with t8122 (M3). + properties: compatible: - items: - - enum: - - apple,t8112-aic - - apple,t6000-aic - - apple,t6020-aic - - const: apple,aic2 + oneOf: + - items: + - enum: + - apple,t8112-aic + - apple,t6000-aic + - apple,t6020-aic + - const: apple,aic2 + - items: + - enum: + - apple,t6030-aic3 + - const: apple,t8122-aic3 + - const: apple,t8122-aic3 =20 interrupt-controller: true =20 @@ -117,7 +127,9 @@ allOf: properties: compatible: contains: - const: apple,t8112-aic + enum: + - apple,t8112-aic + - apple,t8122-aic3 then: properties: '#interrupt-cells': @@ -141,4 +153,19 @@ examples: <0x2 0x8e10c000 0x0 0x4>; reg-names =3D "core", "event"; }; + + }; + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + aic_t8122: interrupt-controller@2d1000000 { + compatible =3D "apple,t8122-aic3"; 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Wed, 28 Jan 2026 03:57:26 -0500 (EST) From: Janne Grunau Date: Wed, 28 Jan 2026 09:57:09 +0100 Subject: [PATCH v2 2/2] irqchip/apple-aic: Add support for "apple,t8122-aic3" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-irq-apple-aic3-v2-2-b4bc8e16c997@jannau.net> References: <20260128-irq-apple-aic3-v2-0-b4bc8e16c997@jannau.net> In-Reply-To: <20260128-irq-apple-aic3-v2-0-b4bc8e16c997@jannau.net> To: Sven Peter , Neal Gompa , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Janne Grunau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3142; i=j@jannau.net; s=yk2025; h=from:subject:message-id; bh=c8+y7YK8j4mLCVCoVK1eu9NeJiQU/vi7Kvi5/Rxprhw=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhszK8wUZqhsXL5Y3b+uo/9jZetvjhpRrjlSronjFP7UYk e7rXModpSwMYlwMsmKKLEnaLzsYVtcoxtQ+CIOZw8oEMoSBi1MAJnL5LcP/4EVSM7f0vRPq1JWa zPBsrd3Lxy2+Jgd+SR/c+8YgK3XCVkaGm70h83eHp17d8cLyu4/2VMnftfGl10VTBW/6+IVX5s3 mAAA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Introduce support for the new AICv3 hardware block in t8122 and t603x SoCs. AICv3 is similar to AICv2 but has an increased IRQ config offset. These MMIO offsets are coded as properties of the "aic,3" node in Apple's device tree. The actual offsets are the same for all SoCs starting from M3 through at least M5. So do not bother to follow suit but use AICv3 specific defines in the driver. The compatible string is SoC specific so future SoCs with AICv3 and different offsets would just use their own compatible string as base and add their new offsets. Reviewed-by: Sven Peter Signed-off-by: Janne Grunau --- drivers/irqchip/irq-apple-aic.c | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-apple-aic.c b/drivers/irqchip/irq-apple-ai= c.c index 3c70364e7cddd6ed6285595f136146ab04b897b2..4607d28f23887fb4bfe286a398d= 5a5b2f840e716 100644 --- a/drivers/irqchip/irq-apple-aic.c +++ b/drivers/irqchip/irq-apple-aic.c @@ -134,8 +134,12 @@ =20 #define AIC2_IRQ_CFG 0x2000 =20 +/* AIC v3 registers (MMIO) */ +#define AIC3_IRQ_CFG 0x10000 + /* * AIC2 registers are laid out like this, starting at AIC2_IRQ_CFG: + * AIC3 registers use the same layout but start at AIC3_IRQ_CFG: * * Repeat for each die: * IRQ_CFG: u32 * MAX_IRQS @@ -293,6 +297,15 @@ static const struct aic_info aic2_info __initconst =3D= { .local_fast_ipi =3D true, }; =20 +static const struct aic_info aic3_info __initconst =3D { + .version =3D 3, + + .irq_cfg =3D AIC3_IRQ_CFG, + + .fast_ipi =3D true, + .local_fast_ipi =3D true, +}; + static const struct of_device_id aic_info_match[] =3D { { .compatible =3D "apple,t8103-aic", @@ -310,6 +323,10 @@ static const struct of_device_id aic_info_match[] =3D { .compatible =3D "apple,aic2", .data =3D &aic2_info, }, + { + .compatible =3D "apple,t8122-aic3", + .data =3D &aic3_info, + }, {} }; =20 @@ -620,7 +637,7 @@ static int aic_irq_domain_map(struct irq_domain *id, un= signed int irq, u32 type =3D FIELD_GET(AIC_EVENT_TYPE, hw); struct irq_chip *chip =3D &aic_chip; =20 - if (ic->info.version =3D=3D 2) + if (ic->info.version =3D=3D 2 || ic->info.version =3D=3D 3) chip =3D &aic2_chip; =20 if (type =3D=3D AIC_EVENT_TYPE_IRQ) { @@ -991,7 +1008,7 @@ static int __init aic_of_ic_init(struct device_node *n= ode, struct device_node *p =20 break; } - case 2: { + case 2 ... 3: { u32 info1, info3; =20 info1 =3D aic_ic_read(irqc, AIC2_INFO1); @@ -1065,7 +1082,7 @@ static int __init aic_of_ic_init(struct device_node *= node, struct device_node *p off +=3D irqc->info.die_stride; } =20 - if (irqc->info.version =3D=3D 2) { + if (irqc->info.version =3D=3D 2 || irqc->info.version =3D=3D 3) { u32 config =3D aic_ic_read(irqc, AIC2_CONFIG); =20 config |=3D AIC2_CONFIG_ENABLE; @@ -1116,3 +1133,4 @@ static int __init aic_of_ic_init(struct device_node *= node, struct device_node *p =20 IRQCHIP_DECLARE(apple_aic, "apple,aic", aic_of_ic_init); IRQCHIP_DECLARE(apple_aic2, "apple,aic2", aic_of_ic_init); +IRQCHIP_DECLARE(apple_aic3, "apple,t8122-aic3", aic_of_ic_init); --=20 2.52.0