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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59e074bfe83sm459483e87.97.2026.01.28.01.55.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 01:55:04 -0800 (PST) From: Marcus Folkesson Date: Wed, 28 Jan 2026 10:54:27 +0100 Subject: [PATCH v4 1/5] i2c: core: add callback to change bus frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-i2c-mux-v4-1-dee49ce276c0@gmail.com> References: <20260128-i2c-mux-v4-0-dee49ce276c0@gmail.com> In-Reply-To: <20260128-i2c-mux-v4-0-dee49ce276c0@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1616; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=eRPT6fwWSu39UFp184/6KNALMdSEu1tiZOm0jan9AEk=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBpedzehXVLc5la3fttcAt9Pf63CW8xGjrpt9Gtl m5Jrx2wvzCJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaXnc3gAKCRCIgE5vWV1S MkRqEADXrxdBsBlenpKcAm45b1vgUJl5qzd/GhpRErNbr50L14Aj7bdwJ2ihLfpLoh60Qft2yBy NNAl7O56qyFBmGeWfyLSQehsIh775Ud4kJ7icMlu3t8clHbjFtCrnlygOiTL6HjIHg8pQiivtRl GYv6hW7pFiU2cmCQ7c9PEx5J7o3WM3f3R/HWi+VS1WP7+0WGVjEV+7mnQjOFAAfpl1vtf0UfqLn JFXWQ9WvO1sTUUAMtAklTsoztuIL6csWXW/4KJlJV3TwmylgA+4Hojjfm7mDMrjC8VZ3e806uLk eG1iPk9kvJuKpkWng6bVCPmlCcocTgEtgDLe5HkAV+MUaBFldysjcJiooWse/4mvGui2ZuhfNoe 9hsXpZqX4pxg7vHNsF+7IjgixG5VlAyB+kufL3Ul0X5m8Xh+XrMx69S0041/Eon1ROMHxWZEqBQ 7VeysczxzbQRPSrAPv0bUHW1Aq4z9xLC2KxAzzto6P1IAdLgliqaB7W47k+dYFSEzRVlBx/RgGe rzPrux72Ged1sYyIBsVr8oo/WV5bKbfg69dk0jGBjUs7y7mxh87UrBeZwFgYtT4r3+xGb42CtYw 702+BI6VraEFM4CivtIYhY1Eaay41GgmI5F/gTmMF5XX5FwzWJwTyAk1SI62UyoRViH1Uf/KiTE X4kYiUc2CpYCVHQ== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 All devices on the same I2C bus share the same clock line and the bus frequency has therefor be chosen so that all attached devices are able to tolarate that clock rate. IOW, the bus speed must be set for the slowest attached device. With I2C multiplexers/switches on the other hand, it would be possible to have different "domains" that runs with different speeds. Prepare for such a feature by provide an optional callback function to change bus frequency. Signed-off-by: Marcus Folkesson --- include/linux/i2c.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/i2c.h b/include/linux/i2c.h index 20fd41b51d5c..d147e388dbab 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -742,6 +742,8 @@ struct i2c_adapter { struct rt_mutex mux_lock; =20 int timeout; /* in jiffies */ + int clock_hz; + int (*set_clk_freq)(struct i2c_adapter *adap, u32 clock_hz); /* Optional = */ int retries; struct device dev; /* the adapter device */ unsigned long locked_flags; /* owned by the I2C core */ @@ -835,6 +837,17 @@ i2c_unlock_bus(struct i2c_adapter *adapter, unsigned i= nt flags) adapter->lock_ops->unlock_bus(adapter, flags); } =20 +static inline int +i2c_adapter_set_clk_freq(struct i2c_adapter *adapter, u32 clock_hz) +{ + int ret =3D -EOPNOTSUPP; + + if (adapter->set_clk_freq) + ret =3D adapter->set_clk_freq(adapter, clock_hz); + + return ret; +} + /** * i2c_mark_adapter_suspended - Report suspended state of the adapter to t= he core * @adap: Adapter to mark as suspended --=20 2.52.0 From nobody Sat Feb 7 08:23:18 2026 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A058A34DB52 for ; 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59e074bfe83sm459483e87.97.2026.01.28.01.55.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 01:55:05 -0800 (PST) From: Marcus Folkesson Date: Wed, 28 Jan 2026 10:54:28 +0100 Subject: [PATCH v4 2/5] i2c: mux: add support for per channel bus frequency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-i2c-mux-v4-2-dee49ce276c0@gmail.com> References: <20260128-i2c-mux-v4-0-dee49ce276c0@gmail.com> In-Reply-To: <20260128-i2c-mux-v4-0-dee49ce276c0@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7463; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=zGbz+pVrLmaMtnSNrlYn54fESL7esdXmRLMMNcwIf6k=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBpedzm0S4PL15YJnIkLNwLSsRAPOQD+Ms7LXZSU Nq5cqqtauqJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaXnc5gAKCRCIgE5vWV1S MhOeEADTIxXYKIPxrPfFpvluokTAsbhQb0ncWTgS4dNJ+H4iFQUPs6mVvw2aLi6tRkFd12IN38z kD7v3jJ2b8w2IwM6Qd4CCeAqiSUklrQSiA4beaQt2Akh6pOlsWXejatmLZdta84hSsDQSEs7Dr/ efMnf6gyV+NuLovi1qWP9KeTlHBb80vQvbmH5oJobUwuemVP7GR/UowDN9JyUhzEGAftHOdtlEn 4vH1tmnf1DsxR5JwMjszsCrnK4ykPdoJY4FRnnCni/hhr1rtFXSpFptHCSa0Ncr0kL6ptJXkYZc 3Fw7I8lOSCRYxhJtpDd2QxQ/oJGa6moQF95VOI2Nix3LT6vZPppt4ijI72KB2a26FQiBOgae4uj xSVBaNbBD3hu/0qznCpYwSW6MYv+oGWCCu8a9zCVeyQfX7sakTladFxBLvUk7xwTHNfdv1D60lV wew3trRfE9mvIODbRz+IC9lIxbsOSwSjSSDqXMdo34akdh6yTybk503NdcFwrfIJJCNzkdrbXNC Gk9+8LEJCaYspLKV/nCfW7nR/isiMUWV5zKe7WtcJQGfRyBi1O23Rn7pi9ecEPaGP5wH//NPfoF 9I/GppOi3KiGlQYw3crh7BAK1oJ5SObwylvujkYA6M0xav0cA+UDPTJSvr+55z7Qe5FxUsu9Bk8 pkE2rqQU7+EviHg== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 There may be several reasons why you may need to use a certain speed on an I2C bus. E.g. - When several devices are attached to the bus, the speed must be selected according to the slowest device. - Electrical conditions may limit the usuable speed on the bus for different reasons. With an I2C multiplexer, it is possible to group the attached devices after their preferred speed by e.g. put all "slow" devices on a separate channel on the multiplexer. Consider the following topology: .----------. 100kHz .--------. .--------. 400kHz | |--------| dev D1 | | root |--+-----| I2C MUX | '--------' '--------' | | |--. 400kHz .--------. | '----------' '-------| dev D2 | | .--------. '--------' '--| dev D3 | '--------' One requirement with this design is that a multiplexer may only use the same or lower bus speed as its parent. Otherwise, if the multiplexer would have to increase the bus frequency, then all siblings (D3 in this case) would run into a clock speed it may not support. The bus frequency for each channel is set in the devicetree. As the i2c-mux bindings import the i2c-controller schema, the clock-frequency property is already allowed. If no clock-frequency property is set, the channel inherit their parent bus speed. The following example uses dt bindings to illustrate the topology above: i2c { clock-frequency =3D <400000>; i2c-mux { i2c@0 { clock-frequency =3D <100000>; D1 { ... }; }; i2c@1 { D2 { ... }; }; }; D3 { ... } }; Signed-off-by: Marcus Folkesson --- drivers/i2c/i2c-mux.c | 116 ++++++++++++++++++++++++++++++++++++++++++++--= ---- 1 file changed, 104 insertions(+), 12 deletions(-) diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c index d59644e50f14..b7974161be4a 100644 --- a/drivers/i2c/i2c-mux.c +++ b/drivers/i2c/i2c-mux.c @@ -36,6 +36,72 @@ struct i2c_mux_priv { u32 chan_id; }; =20 +static int i2c_mux_select_chan(struct i2c_adapter *adap, u32 chan_id) +{ + struct i2c_mux_priv *priv =3D adap->algo_data; + struct i2c_mux_core *muxc =3D priv->muxc; + struct i2c_adapter *parent =3D muxc->parent; + struct i2c_adapter *root; + int ret; + + if (priv->adap.clock_hz && priv->adap.clock_hz !=3D parent->clock_hz) { + root =3D i2c_root_adapter(&adap->dev); + + /* if we are parent-locked and the root adapter is our parent, + * we already have the lock we need. Otherwise take the bus lock for the= root + * adapter before changing bus clock. + */ + if ((root !=3D parent && !muxc->mux_locked) || muxc->mux_locked) + i2c_lock_bus(parent, I2C_LOCK_ROOT_ADAPTER); + + ret =3D i2c_adapter_set_clk_freq(root, priv->adap.clock_hz); + + if ((root !=3D parent && !muxc->mux_locked) || muxc->mux_locked) + i2c_unlock_bus(parent, I2C_LOCK_ROOT_ADAPTER); + + if (ret < 0) { + dev_err(&adap->dev, + "Failed to set clock frequency %dHz on root adapter %s: %d\n", + priv->adap.clock_hz, root->name, ret); + + return ret; + } + } + + return muxc->select(muxc, priv->chan_id); +} + +static void i2c_mux_deselect_chan(struct i2c_adapter *adap, u32 chan_id) +{ + struct i2c_mux_priv *priv =3D adap->algo_data; + struct i2c_mux_core *muxc =3D priv->muxc; + struct i2c_adapter *parent =3D muxc->parent; + struct i2c_adapter *root; + int ret; + + if (parent->clock_hz && parent->clock_hz !=3D priv->adap.clock_hz) { + root =3D i2c_root_adapter(&parent->dev); + + /* if we are parent-locked and the root adapter is our parent, + * we already have the lock we need. Otherwise take the bus lock for the= root + * adapter before changing bus clock. + */ + if ((root !=3D parent && !muxc->mux_locked) || muxc->mux_locked) + i2c_lock_bus(parent, I2C_LOCK_ROOT_ADAPTER); + + ret =3D i2c_adapter_set_clk_freq(root, parent->clock_hz); + + if ((root !=3D parent && !muxc->mux_locked) || muxc->mux_locked) + i2c_unlock_bus(parent, I2C_LOCK_ROOT_ADAPTER); + + if (ret < 0) + return; + } + + if (muxc->deselect) + muxc->deselect(muxc, priv->chan_id); +} + static int __i2c_mux_master_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { @@ -46,11 +112,11 @@ static int __i2c_mux_master_xfer(struct i2c_adapter *a= dap, =20 /* Switch to the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id); if (ret >=3D 0) ret =3D __i2c_transfer(parent, msgs, num); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id); =20 return ret; } @@ -65,11 +131,11 @@ static int i2c_mux_master_xfer(struct i2c_adapter *ada= p, =20 /* Switch to the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id); if (ret >=3D 0) ret =3D i2c_transfer(parent, msgs, num); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id); =20 return ret; } @@ -86,12 +152,12 @@ static int __i2c_mux_smbus_xfer(struct i2c_adapter *ad= ap, =20 /* Select the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id); if (ret >=3D 0) ret =3D __i2c_smbus_xfer(parent, addr, flags, read_write, command, size, data); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id); =20 return ret; } @@ -108,12 +174,12 @@ static int i2c_mux_smbus_xfer(struct i2c_adapter *ada= p, =20 /* Select the right mux port and perform the transfer. */ =20 - ret =3D muxc->select(muxc, priv->chan_id); + ret =3D i2c_mux_select_chan(adap, priv->chan_id); if (ret >=3D 0) ret =3D i2c_smbus_xfer(parent, addr, flags, read_write, command, size, data); - if (muxc->deselect) - muxc->deselect(muxc, priv->chan_id); + + i2c_mux_deselect_chan(adap, priv->chan_id); =20 return ret; } @@ -362,6 +428,32 @@ int i2c_mux_add_adapter(struct i2c_mux_core *muxc, } } =20 + of_property_read_u32(child, "clock-frequency", &priv->adap.clock_hz); + + /* If the mux adapter has no clock-frequency property, inherit from pare= nt */ + if (!priv->adap.clock_hz) + priv->adap.clock_hz =3D parent->clock_hz; + + /* + * Warn if the mux adapter is not parent-locked as + * this may cause issues for some hardware topologies. + */ + if ((priv->adap.clock_hz < parent->clock_hz) && muxc->mux_locked) + dev_warn(muxc->dev, + "channel %u is slower than parent on a non parent-locked mux\n", + chan_id); + + /* We don't support mux adapters faster than their parent */ + if (priv->adap.clock_hz > parent->clock_hz) { + dev_err(muxc->dev, + "channel (%u) is faster (%u) than parent (%u)\n", + chan_id, priv->adap.clock_hz, parent->clock_hz); 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59e074bfe83sm459483e87.97.2026.01.28.01.55.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 01:55:07 -0800 (PST) From: Marcus Folkesson Date: Wed, 28 Jan 2026 10:54:29 +0100 Subject: [PATCH v4 3/5] i2c: davinci: calculate bus freq from Hz instead of kHz Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-i2c-mux-v4-3-dee49ce276c0@gmail.com> References: <20260128-i2c-mux-v4-0-dee49ce276c0@gmail.com> In-Reply-To: <20260128-i2c-mux-v4-0-dee49ce276c0@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2849; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=NgWDqx3izSY9aW9W75gFytkLHJndTcTMdemaHAZbfa4=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBpedztECNc3VxUquFpfx8TQoFrSB7cIxNlSZrqJ OhN7zzlH9eJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaXnc7QAKCRCIgE5vWV1S MlXrD/sE0/W8x83hap7Dhta6qJH+6wF6kDCcG1nxuNfBbrETgbLx4/lBqTEH+JGM1kh6cLk+cBC OXhIvL0znx8Ye6vGhce2X3A05Vxr81wpEbQbRe9QUN6obI9cvRO9lgAgQbU/G1E3LN0WuPUDpGq 2keTYvwNLTRFhKa3oNJ0jVezTvxaBjegypn7VqGh/2wsAKFBac0He5JPPm5Y0QHZ0HynM7e6eKR vLjy2123DV8Y37F8GNwXvsgh/V8ArPWLz/AFWJgKnP1Jg71uGQkpoE/o+KHJg0VPmGzjdhecORg INeawLbjnZElkte5DoMf0b3Cgmef5Ai/CydViiGWFB5LtjrnpIOTC6nPXsekboiTW5n+BS5ce0r z8mC53lIH+iNWjMK/EloWDzWZRW9c5r+F5fRIedKlapVON883bMtMNPt6rfwpTjUWxPDfeOzbGr WAu806t53dfko2sVuyMr9WpeZcneLS+p0leVem6G+fD7tjUPct3N7Rt/g+0IY1ZFsDPZkMXxBq3 awFcReXJ0Q0+/CwQCoZrfLAo8FZuVAwXO5fShHCu+8VuzXvmOkM+bsW+bF9VkSmRzrtPGDV3P5J LIVRvkRAjDPrO5S+pppy0mF3xvBoxjiUycdjY8TxrWA8CkRLSZqyUEosPD2ifkHPGiGF3stiWZs PhoubjCsc3jj1wA== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 The bus frequency is unnecessarily converted between Hz and kHz in several places. This is probably an old legacy from the old times (pre-devicetrees) when the davinci_i2c_platform_data took the bus_freq in kHz. Stick to Hz. Reviewed-by: Bartosz Golaszewski Signed-off-by: Marcus Folkesson --- drivers/i2c/busses/i2c-davinci.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davi= nci.c index a773ba082321..761de5a814df 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -117,8 +117,6 @@ /* timeout for pm runtime autosuspend */ #define DAVINCI_I2C_PM_TIMEOUT 1000 /* ms */ =20 -#define DAVINCI_I2C_DEFAULT_BUS_FREQ 100 - struct davinci_i2c_dev { struct device *dev; void __iomem *base; @@ -134,8 +132,8 @@ struct davinci_i2c_dev { #ifdef CONFIG_CPU_FREQ struct notifier_block freq_transition; #endif - /* standard bus frequency (kHz) */ - unsigned int bus_freq; + /* standard bus frequency */ + unsigned int bus_freq_hz; /* Chip has a ICPFUNC register */ bool has_pfunc; }; @@ -209,16 +207,16 @@ static void i2c_davinci_calc_clk_dividers(struct davi= nci_i2c_dev *dev) if (device_is_compatible(dev->dev, "ti,keystone-i2c")) d =3D 6; =20 - clk =3D ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)); + clk =3D ((input_clock / (psc + 1)) / (dev->bus_freq_hz)); /* Avoid driving the bus too fast because of rounding errors above */ - if (input_clock / (psc + 1) / clk > dev->bus_freq * 1000) + if (input_clock / (psc + 1) / clk > dev->bus_freq_hz) clk++; /* * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at * least 1.3uS, which is not the case with 50% duty cycle. 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Acked-by: Bartosz Golaszewski Signed-off-by: Marcus Folkesson --- drivers/i2c/busses/i2c-davinci.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davi= nci.c index 761de5a814df..3daa823dcb9e 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -279,6 +279,27 @@ static int i2c_davinci_init(struct davinci_i2c_dev *de= v) return 0; } =20 +static int davinci_i2c_set_clk(struct i2c_adapter *adap, u32 clock_hz) +{ + struct davinci_i2c_dev *dev =3D i2c_get_adapdata(adap); + + if (dev->bus_freq_hz =3D=3D clock_hz) + return 0; + + dev->bus_freq_hz =3D clock_hz; + + /* put I2C into reset */ + davinci_i2c_reset_ctrl(dev, 0); + + /* compute clock dividers */ + i2c_davinci_calc_clk_dividers(dev); + + /* Take the I2C module out of reset: */ + davinci_i2c_reset_ctrl(dev, 1); + + return 0; +} + /* * This routine does i2c bus recovery by using i2c_generic_scl_recovery * which is provided by I2C Bus recovery infrastructure. @@ -809,6 +830,8 @@ static int davinci_i2c_probe(struct platform_device *pd= ev) adap->dev.parent =3D &pdev->dev; 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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-59e074bfe83sm459483e87.97.2026.01.28.01.55.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jan 2026 01:55:11 -0800 (PST) From: Marcus Folkesson Date: Wed, 28 Jan 2026 10:54:31 +0100 Subject: [PATCH v4 5/5] docs: i2c: i2c-topology: add section about bus speed Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-i2c-mux-v4-5-dee49ce276c0@gmail.com> References: <20260128-i2c-mux-v4-0-dee49ce276c0@gmail.com> In-Reply-To: <20260128-i2c-mux-v4-0-dee49ce276c0@gmail.com> To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Marcus Folkesson X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8159; i=marcus.folkesson@gmail.com; h=from:subject:message-id; bh=G8r8z7mFndx6RhNUdA+WKfKocioUhRmN3d9RveqxuFs=; b=owEBbQKS/ZANAwAKAYiATm9ZXVIyAcsmYgBpedz3ayCz4hIuoaAf9as6dbL/CguP9iycbTa1a HYpkfvi2+SJAjMEAAEKAB0WIQQFUaLotmy1TWTBLGWIgE5vWV1SMgUCaXnc9wAKCRCIgE5vWV1S MhLyD/9g6rixHuYEpXz2umKPHT07E4y/jjWHMeiM0NQi12GeE79wmvswD6wNcNyWN4mi7AGKf3i cQd3TtbCh/lXw1CY5ezARXKRG9UfTkbHh3npBOdQb7Qag3iyp92/sIZXi5j6RnypZM2nGxc3WxM 3hIMXf2Q3CFfkAgNOKNS2MbGATdu2ZeFRBqQ+B4LVpI3a8J0SDsVLbKjZ14MnMD/b5upaJe9w/E ikU+yDvHi2OAdHjW9dXGGoQEN/7eOX91RJ780aX5f0OUo1THZjHAxFpZYoKkVa1r3hZ2BcuYSn2 3SNiALo14Rf3pQcmLXZEBjTix8IMdSWBWHy2wHxHjt6PvAD3XI4GlsFNvOsfBaJlioHoevg/KnB 0sgX08+LiPwxw87nu7Q+UnGDmVDATZ5PV+Md3mHNzNFgVasZ99vO37/bMAR1O9IoXhGD6Gek9Oa 2OCV/F5j51SBXQpziKzO8F0Ys0u2QfFu6KbstEvpUoLlc+le0ta57RqRUoWxYeY9FH8dPZarScf Nc2Rx43D1M2s6/Owp16pVmYBDh6SV5tnushh9gNcGDdT3IT6ghGOI+BmGG+MdbNbbJq4xiRGfye t34VVOCnQ2vkN2mTIsLPyQY2O0dOjwbBbLWAIicC4sdo+FU4zXhYoeHqp3ouiVscOl37rd80O8/ 5sGfADmexTHd5wA== X-Developer-Key: i=marcus.folkesson@gmail.com; a=openpgp; fpr=AB91D46C7E0F6E6FB2AB640EC0FE25D598F6C127 Describe what needs to be consideraed and taken into account when using different bus speeds for different mux channels. Signed-off-by: Marcus Folkesson --- Documentation/i2c/i2c-topology.rst | 176 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 176 insertions(+) diff --git a/Documentation/i2c/i2c-topology.rst b/Documentation/i2c/i2c-top= ology.rst index 48fce0f7491b..2c4a1364ce82 100644 --- a/Documentation/i2c/i2c-topology.rst +++ b/Documentation/i2c/i2c-topology.rst @@ -367,6 +367,182 @@ When D1 or D2 are accessed, accesses to D3 and D4 are= locked out while accesses to D5 may interleave. When D3 or D4 are accessed, accesses to all other devices are locked out. =20 +Bus Speed and I2C Multiplexers +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +I2C bus multiplexers allows multiple downstream channels to be exposed +as separate I2C adapters which also could set their own bus speed. + +The multiplexer itself cannot change the bus speed as it use the upstream +clock and data lines to communicate with the downstream devices. The speed +is therfor changed in the root adapter resulting in that the whole bus is +affected. + +This increases the complexity of the topology and some considerations must +be taken into. + +Bus speed +---------- + +Downstream channels of an I2C multiplexer can only operate at the same or +lower bus speed as the upstream bus. This is because the upstream bus may +have devices that cannot operate at higher speeds and those will be affect= ed +by the speed change. + +The example below illustrates the problem. +The root adapter is operating at 100kHz. D2 can only operate with 100kHz, +but D2 can operate at 400kHz. When D1 is selected, the bus speed of the +root adapter would have to be is set to 400kHz, a speed that D2 may not su= pport. + +This topology is therefor not allowed: :: + + .----------. 400kHz .--------. + .--------. 100kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 | + | '----------' + | .--------. + '--| dev D2 | + '--------' + + +This topology is allowed: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D2 | + | root |--+-----| locked | '--------' + '--------' | mux M1 |--. 400kHz .--------. + '----------' '--------| dev D1 | + '--------' + +Preferred topology +------------------- + +The preferred topology when using different bus speeds is to have the mult= iplexer +connected directly to the root adapter without any devices as siblings. +By this arrangement, the bus speed can be changed without affecting any ot= her devices +and many of the caveats are avoided. + +Other multiplexers in parallell is still okay as those are locked out duri= ng transfers. + +This is the preferred topology: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D2 | + | root |--+-----| locked | '--------' + '--------' | mux M1 |--. 400kHz .--------. + '----------' '--------| dev D1 | + '--------' +Locking +-------- + +If the multiplexer is mux-locked, transfers to D3 may interleave between t= he +select-transfer-deselect to D1 or D2. +This results in a situation where the bus speed to D3 may be lower than it +is supposed to be. This is usually not a problem. + +This topology is allowed but some transfers to D3 may be at 100kHz: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 |--. 400kHz .--------. + | '----------' '--------| dev D2 | + | .--------. '--------' + '--| dev D3 | + '--------' + +Multiple muxes in series +-------------------------- + +When multiple muxes are used in series the same rules applies. + +Transfers to D3 may interleave between select-transfer-deselect to D1, whi= ch +results that the bus speed to D2 or D3 will be at 100KHz. + +Transfers to D2 may interleave between select-transfer-deselect to D1, whi= ch +results in that the bus speed to D1 may be at 400kHz as the transfer to D2 +will set the bus speed to before the transfer to D1 starts. + +This is probably a bad topology :: + + .----------. 400kHz .----------. 100kHz .--------. + .--------.400kHz | mux- |--------| mux- |--------| dev D1 | + | root |--+----| locked | 400kHz | locked | '--------' + '--------' | | mux M1 |--. | mux M2 | + | '----------' | '----------' + | .--------. | .--------. + '--| dev D3 | '--| dev D2 | + '--------' '--------' + +Multiple muxes in parallell +---------------------------- + +When multiple muxes are used in parallell all access to other muxes are lo= cked out +so this is not a problem. + +If the muxes are mux-locked, access to D3 may still interleave though. + +In the example below, D3 may not interleave between select-transfer-desele= ct for D1 +or D2 as both muxes are parent-locked: :: + + + .----------. 100kHz .--------. + | parent- |----------| dev D1 | + .--| locked | '--------' + | | mux M1 | + | '----------' + | .----------. 400KHz .--------. + .--------. 400kHz | parent- |---------| dev D2 | + | root |--+------| locked | '--------' + '--------' | | mux M2 | + | '----------' + | .--------. + '--| dev D3 | + '--------' + +Idle state +----------- + +Muxes have an idle state, which is the state the channels is put into when= no channel +is active. The state is typically one of the following: + +- All channels are disconnected +- The last selected channel is left as-is +- A predefined channel is selected + +Muxes that support an idle state where all channels are disconnected are p= referred when using +different bus speeds. Otherwise high bus speeds may "leak" through to devi= ces that +may not support that higher speed. + +Consider the following example: :: + + .----------. 100kHz .--------. + .--------. 400kHz | mux- |--------| dev D1 | + | root |--+-----| locked | '--------' + '--------' | | mux M1 |--. 400kHz .--------. + | '----------' '--------| dev D2 | + | .--------. '--------' + '--| dev D3 | + '--------' + +If the idle state of M1 is: +- All channels disconnected: No problem, D1 and D2 are not affected by com= munication + to D3. +- Last selected channel: Problem if D1 was the last selected channel. High= speed + communication to D3 will be "leaked" to D1. +- Predefined channel: Problem, if the predefined channel D1. Set predefine= d channel + to D2 as D2 may handle 400kHz. + +Supported controllers +----------------------- + +Not all I2C controllers support setting the bus speed dynamically. +At the time of writint, the following controllers has support: + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +i2c-davinci Supports dynamic bus speed +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 Mux type of existing device drivers =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --=20 2.52.0