From nobody Tue Feb 10 00:58:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC48C339844; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769590197; cv=none; b=Wb4r9iZLt8ukxgxaTVt33vve/qoNkIxym6S2wQ33PaRJZP+p3aBPjobDOUSgS1ss8ASRMnguER88HiZyRuiM0xYz052Z/JcWY/e/HFkzY1T+imQCUyq5EaSOvWeuI1oVE4NSB8rNwh7FJrQQScTdrXKb0AAv5dU7PGyGb6lA3AY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769590197; c=relaxed/simple; bh=jPApKe4OnUHqDCmVrRe+5LbHO4U2RPR4SqBfUuQaobI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=skJNsmha7zzAQ5D7z5FsY/PqcdxeajLL+6fwu33Yo9mMmcUiz4/CfyBdeWroE4G//f0reN5aa6hoJxxFAKupNf9ltPJjLgd0I92XbyBFgzvNpg37w2gDGKE4et+UfJzIhPTbvU67CLbEnGYr4hFNU5UuAwJdhlZ9+zQTrxxZSwM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Mr/Phjvk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Mr/Phjvk" Received: by smtp.kernel.org (Postfix) with ESMTPS id B3795C2BCB4; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769590197; bh=jPApKe4OnUHqDCmVrRe+5LbHO4U2RPR4SqBfUuQaobI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Mr/PhjvkPWThtzj+jBqy7ij02xYvR6N/zfnZDu3NIpKaaifanMfxhYK3YUFKSQ6BH hOoPmzFi7tI9L04vrY3Mdgre55/DqW5LoGUtspGCAB3egoipohTp0FktlAWw+tpltW nNM60cvAcEj/OQdjvr1aj8w6VOhsPmFp03JqiAkkIws+9n6C1fcsmxOUCt9Sk0RA6i 6ejhrt+O7QoMBI2zGbovryvg8tvkMbmO+nmCFMXvSEZex2FPhtzVig4orcOgM+goq7 jerw3g46/E9/gmMKw6AnJ8lJW0oG/rYBUC1py18/DgjxzSCLSRDoimdEy94RGCSOtg YMh9RczEnIAAw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0C85D35692; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Wed, 28 Jan 2026 09:49:54 +0100 Subject: [PATCH v4 3/4] arm64: dts: s32: set Ethernet channel irqs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-dwmac_multi_irq-v4-3-82fa34fcf2f2@oss.nxp.com> References: <20260128-dwmac_multi_irq-v4-0-82fa34fcf2f2@oss.nxp.com> In-Reply-To: <20260128-dwmac_multi_irq-v4-0-82fa34fcf2f2@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769590195; l=4163; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=+bEJwX/3spHrmCusaHSSPK6wPAR1HCTfpAlGDA5P1YA=; b=vIN+HXciTpOHUqUDxNPWM6CkKic057xj2uyyBnyM5d/9gwSF2zq5RrS5qanARCUGxClzBMw74 4gX5zl4Eh37DGUy1maQF2fOrE/zajahR9r8le6wXCP3kFez45HrDOJs X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The GMAC Ethernet controller found on S32G2/S32G3 and S32R45 contains up to 5 RX and 5 TX channels. It can operate in two interrupt modes: 1) Sharing IRQ mode: only MAC IRQ line is used for all channels. 2) Multiple IRQ mode: every channel uses two IRQ lines, one for RX and second for TX. Specify all IRQ twins for all channels. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++++++++++++++++++--- arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 +++++++++++++++++++++++--- 2 files changed, 46 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 51d00dac12de..5a553d503137 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright 2017-2021, 2024-2025 NXP + * Copyright 2017-2021, 2024-2026 NXP */ =20 #include @@ -732,8 +732,28 @@ gmac0: ethernet@4033c000 { reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; status =3D "disabled"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index eff7673e7f34..e1f248d3aedb 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2025 NXP + * Copyright 2021-2026 NXP * * Authors: Ghennadi Procopciuc * Ciprian Costea @@ -809,8 +809,28 @@ gmac0: ethernet@4033c000 { reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; status =3D "disabled"; --=20 2.47.0