From nobody Mon Feb 9 10:12:32 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C17F73396E8; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769590197; cv=none; b=XZzJQd9aCEEy3dbjNps/lr1gc+znXbBT0TdtawPYy71uAUmjh6upbNZKU9CzPR8mI4MU9wwQX3X/PPCWS2PGoIySH/0ns83Y1HzQe9hzHevC1tqZSVAAMHovQ2OeBVftAzx1I50kPDSuiqFMVwhs5ROMnJ+ydC91FxhrkObvm+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769590197; c=relaxed/simple; bh=/uyunbAFyWz73pwhxvZxxjAT7WQI0mMKq8d0GLlcH+o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fnqqsEpky3FIE3RVHHwbJoJsQvXr2X97uypGJAqjkMNmnvdO1Xb4ut7Iw/D2le61wBl9YAmVog3ajpWmeIfS7UDbsQdJn0Rl160TgNTMvULiE3XUE1Lxn+5J3I4LWM/XKrkf+AV7FlYe+UYQjUqQeNChdTwiZxtmGOw91g446kw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=am1MPw00; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="am1MPw00" Received: by smtp.kernel.org (Postfix) with ESMTPS id 932D6C19422; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769590197; bh=/uyunbAFyWz73pwhxvZxxjAT7WQI0mMKq8d0GLlcH+o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=am1MPw00eiIKmRNswvuatQj+H7O+XXy8Cu8fZ0t9DwalB2lL8pQNfloKhkmeiYNsC YlIOjIlx4TZHo53Om0VJ+o3Q+8xMQo2oLjaExu7y9sL+tLtcFezvjN+vCOrV7ghn7O 54IXQw684z7heP+KhFrjpyPyQcxHa0j7LM2rLzr3N/5j/vdsXkicm5pkAx83TGltrj smc8UmucnQXTElKGS9+V1N8nZsUhpqPe4Vn5vsGcqWblV7tnbSlk2kKFdGp7Yxs/Bt jM1jDE4PVCLJXwMLx/ChkzNSeyubnCNKol7HFlyYM+4zt9vg8VtkXNpIGmLg9np38J +GeTaYX+Y6lMA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 820F4D35696; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Wed, 28 Jan 2026 09:49:53 +0100 Subject: [PATCH v4 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-dwmac_multi_irq-v4-2-82fa34fcf2f2@oss.nxp.com> References: <20260128-dwmac_multi_irq-v4-0-82fa34fcf2f2@oss.nxp.com> In-Reply-To: <20260128-dwmac_multi_irq-v4-0-82fa34fcf2f2@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769590195; l=3436; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=IDIUEAasYnGEnlJkNZygiJ9HZplC9b8+OT2lVVZkZiA=; b=moVnyHpZh6OO0BYSd14hEB8pt4RQ5TKjxJaTrx8LJbnNuaf3FBrIIlJweQ8d/4A45x2elNgph 2h/UQmbGu/YDhbzLPhcqSkfIA8CNFfpAWSw5A0drbrLrkUWeLALb4yO X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines, set them to allow using Multi-IRQ mode. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 44 ++++++++++++++++++= +--- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Doc= umentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 2b8b74c5feec..c5bba453bd0e 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright 2021-2024 NXP +# Copyright 2021-2026 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml# @@ -16,6 +16,8 @@ description: the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII interface over Pinctrl device or the output can be routed to the embedded SerDes for SGMII connectivity. + The DWMAC instances have connected all RX/TX queues interrupts, + enabling load balancing of data traffic across all CPU cores. =20 properties: compatible: @@ -33,10 +35,22 @@ properties: - description: GMAC PHY mode control register =20 interrupts: - maxItems: 1 + minItems: 11 + maxItems: 11 =20 interrupt-names: - const: macirq + items: + - const: macirq + - const: tx-queue-0 + - const: rx-queue-0 + - const: tx-queue-1 + - const: rx-queue-1 + - const: tx-queue-2 + - const: rx-queue-2 + - const: tx-queue-3 + - const: rx-queue-3 + - const: tx-queue-4 + - const: rx-queue-4 =20 clocks: items: @@ -75,8 +89,28 @@ examples: reg =3D <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */ <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; clocks =3D <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>; --=20 2.47.0