From nobody Sun Feb 8 17:13:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF5BE3396E6; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769590197; cv=none; b=dpFwEbov7CCOBRvxstZFVdc5T84xlHLtwGHmj8EXpoct34bEdlW9EDgAvZQzIUUdeD7k6Zla1M4+7Oqqnr5bUUitiiMms4ArL1lrBw2AHTBUOxQ0JutGdSSgjkeZ2xRoYBx2pletgkM9zx2Un5CkxT9Bt7YY919le6Mt0T77Xvk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769590197; c=relaxed/simple; bh=POOrLQ7MmklMY5XTpUxtW8dqPF4Tvcgft6k5w8JnMlE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pWhDT5UM3qIHXJ+ytSEudQa0xKCfQlDcqi4/czb6kVjxB27wc+/ijo3HVtUx6pYcAng21CZoh0Ly5PWMHsP0h7jNmELnb5W51FlhMUhsYlmgn/nMw7Q9tx8xlfSyvRdvFUFdsoxorRYn6FWOHKetEgOW3oggpC/oItuxsuSGXwo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tEg9vszD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tEg9vszD" Received: by smtp.kernel.org (Postfix) with ESMTPS id 74133C2BCAF; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769590197; bh=POOrLQ7MmklMY5XTpUxtW8dqPF4Tvcgft6k5w8JnMlE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=tEg9vszDuW1kv1ToIAwHlG+dwwZK/yrjOu1gaooKQuDfJvRhxDmFQl/dXVHNIH0Fc 0AWXjiBNsxGpxGSFsQpWb3u+f2E8QKPYyBdLiTbDlwbb4lxQFjA3AXehSTETKpgrdT xt7dpKSCT9PLGJnWz8nL2lPSdFK92l1RXez6d2nnEsxaJ7qGCsimscHau5m3K+VRKP V6XkIwVk3sJHGLffTfzNdDs+VjupxSrNERu+u7mNLWHmCzcjEA+RmzvNQbVKxaLrIG 7R3/LhnP6lK8PmQxnm7GAzFSE0mPB8eeLgJJKMqaYEt7xreXyB2KWjkXdMfLuiXApC A/56EeaKbkrAw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57B5ED35693; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Wed, 28 Jan 2026 09:49:52 +0100 Subject: [PATCH v4 1/4] net: stmmac: platform: read channels irq Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-dwmac_multi_irq-v4-1-82fa34fcf2f2@oss.nxp.com> References: <20260128-dwmac_multi_irq-v4-0-82fa34fcf2f2@oss.nxp.com> In-Reply-To: <20260128-dwmac_multi_irq-v4-0-82fa34fcf2f2@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769590195; l=2269; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=qCsESZBMy89pwsWTlxW82yylaPKe2lczm3jPGKQ5OYY=; b=VTScslSigOVSXikeYjCNy8XZUc/zMqLNQ9WJMKt8jU5KLP3y90Unql11i5nx3T1X3ZSd/vrIG 1jaXsww1JA4BX8KFy5E+Slg2CCyUubJAciN3Zyn4yTuZv/pgWluT4G+ X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" Read IRQ resources for all rx/tx channels, to allow Multi-IRQ mode for platform glue drivers. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 38 ++++++++++++++++++= +++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/driver= s/net/ethernet/stmicro/stmmac/stmmac_platform.c index 8979a50b5507..94854bfb6e0d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -700,6 +700,9 @@ EXPORT_SYMBOL_GPL(stmmac_pltfr_find_clk); int stmmac_get_platform_resources(struct platform_device *pdev, struct stmmac_resources *stmmac_res) { + char name[16]; + int i; + memset(stmmac_res, 0, sizeof(*stmmac_res)); =20 /* Get IRQ information early to have an ability to ask for deferred @@ -743,7 +746,40 @@ int stmmac_get_platform_resources(struct platform_devi= ce *pdev, =20 stmmac_res->addr =3D devm_platform_ioremap_resource(pdev, 0); =20 - return PTR_ERR_OR_ZERO(stmmac_res->addr); + if (IS_ERR(stmmac_res->addr)) + return PTR_ERR(stmmac_res->addr); + + /* RX channels irq */ + for (i =3D 0; i < MTL_MAX_RX_QUEUES; i++) { + scnprintf(name, sizeof(name), "rx-queue-%d", i); + stmmac_res->rx_irq[i] =3D platform_get_irq_byname_optional(pdev, + name); + if (stmmac_res->rx_irq[i] <=3D 0) { + if (stmmac_res->rx_irq[i] =3D=3D -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_dbg(&pdev->dev, "IRQ rx-queue-%d not found\n", i); + + /* Stop on first unset rx-queue-%i property member */ + break; + } + } + + /* TX channels irq */ + for (i =3D 0; i < MTL_MAX_TX_QUEUES; i++) { + scnprintf(name, sizeof(name), "tx-queue-%d", i); + stmmac_res->tx_irq[i] =3D platform_get_irq_byname_optional(pdev, + name); + if (stmmac_res->tx_irq[i] <=3D 0) { + if (stmmac_res->tx_irq[i] =3D=3D -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_dbg(&pdev->dev, "IRQ tx-queue-%d not found\n", i); + + /* Stop on first unset tx-queue-%i property member */ + break; + } + } + + return 0; } EXPORT_SYMBOL_GPL(stmmac_get_platform_resources); =20 --=20 2.47.0 From nobody Sun Feb 8 17:13:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C17F73396E8; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769590197; cv=none; b=XZzJQd9aCEEy3dbjNps/lr1gc+znXbBT0TdtawPYy71uAUmjh6upbNZKU9CzPR8mI4MU9wwQX3X/PPCWS2PGoIySH/0ns83Y1HzQe9hzHevC1tqZSVAAMHovQ2OeBVftAzx1I50kPDSuiqFMVwhs5ROMnJ+ydC91FxhrkObvm+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769590197; c=relaxed/simple; bh=/uyunbAFyWz73pwhxvZxxjAT7WQI0mMKq8d0GLlcH+o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fnqqsEpky3FIE3RVHHwbJoJsQvXr2X97uypGJAqjkMNmnvdO1Xb4ut7Iw/D2le61wBl9YAmVog3ajpWmeIfS7UDbsQdJn0Rl160TgNTMvULiE3XUE1Lxn+5J3I4LWM/XKrkf+AV7FlYe+UYQjUqQeNChdTwiZxtmGOw91g446kw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=am1MPw00; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="am1MPw00" Received: by smtp.kernel.org (Postfix) with ESMTPS id 932D6C19422; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769590197; bh=/uyunbAFyWz73pwhxvZxxjAT7WQI0mMKq8d0GLlcH+o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=am1MPw00eiIKmRNswvuatQj+H7O+XXy8Cu8fZ0t9DwalB2lL8pQNfloKhkmeiYNsC YlIOjIlx4TZHo53Om0VJ+o3Q+8xMQo2oLjaExu7y9sL+tLtcFezvjN+vCOrV7ghn7O 54IXQw684z7heP+KhFrjpyPyQcxHa0j7LM2rLzr3N/5j/vdsXkicm5pkAx83TGltrj smc8UmucnQXTElKGS9+V1N8nZsUhpqPe4Vn5vsGcqWblV7tnbSlk2kKFdGp7Yxs/Bt jM1jDE4PVCLJXwMLx/ChkzNSeyubnCNKol7HFlyYM+4zt9vg8VtkXNpIGmLg9np38J +GeTaYX+Y6lMA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 820F4D35696; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Wed, 28 Jan 2026 09:49:53 +0100 Subject: [PATCH v4 2/4] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-dwmac_multi_irq-v4-2-82fa34fcf2f2@oss.nxp.com> References: <20260128-dwmac_multi_irq-v4-0-82fa34fcf2f2@oss.nxp.com> In-Reply-To: <20260128-dwmac_multi_irq-v4-0-82fa34fcf2f2@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769590195; l=3436; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=IDIUEAasYnGEnlJkNZygiJ9HZplC9b8+OT2lVVZkZiA=; b=moVnyHpZh6OO0BYSd14hEB8pt4RQ5TKjxJaTrx8LJbnNuaf3FBrIIlJweQ8d/4A45x2elNgph 2h/UQmbGu/YDhbzLPhcqSkfIA8CNFfpAWSw5A0drbrLrkUWeLALb4yO X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines, set them to allow using Multi-IRQ mode. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 44 ++++++++++++++++++= +--- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Doc= umentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 2b8b74c5feec..c5bba453bd0e 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright 2021-2024 NXP +# Copyright 2021-2026 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml# @@ -16,6 +16,8 @@ description: the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII interface over Pinctrl device or the output can be routed to the embedded SerDes for SGMII connectivity. + The DWMAC instances have connected all RX/TX queues interrupts, + enabling load balancing of data traffic across all CPU cores. =20 properties: compatible: @@ -33,10 +35,22 @@ properties: - description: GMAC PHY mode control register =20 interrupts: - maxItems: 1 + minItems: 11 + maxItems: 11 =20 interrupt-names: - const: macirq + items: + - const: macirq + - const: tx-queue-0 + - const: rx-queue-0 + - const: tx-queue-1 + - const: rx-queue-1 + - const: tx-queue-2 + - const: rx-queue-2 + - const: tx-queue-3 + - const: rx-queue-3 + - const: tx-queue-4 + - const: rx-queue-4 =20 clocks: items: @@ -75,8 +89,28 @@ examples: reg =3D <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */ <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; clocks =3D <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>; --=20 2.47.0 From nobody Sun Feb 8 17:13:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC48C339844; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769590197; cv=none; b=Wb4r9iZLt8ukxgxaTVt33vve/qoNkIxym6S2wQ33PaRJZP+p3aBPjobDOUSgS1ss8ASRMnguER88HiZyRuiM0xYz052Z/JcWY/e/HFkzY1T+imQCUyq5EaSOvWeuI1oVE4NSB8rNwh7FJrQQScTdrXKb0AAv5dU7PGyGb6lA3AY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769590197; c=relaxed/simple; bh=jPApKe4OnUHqDCmVrRe+5LbHO4U2RPR4SqBfUuQaobI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=skJNsmha7zzAQ5D7z5FsY/PqcdxeajLL+6fwu33Yo9mMmcUiz4/CfyBdeWroE4G//f0reN5aa6hoJxxFAKupNf9ltPJjLgd0I92XbyBFgzvNpg37w2gDGKE4et+UfJzIhPTbvU67CLbEnGYr4hFNU5UuAwJdhlZ9+zQTrxxZSwM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Mr/Phjvk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Mr/Phjvk" Received: by smtp.kernel.org (Postfix) with ESMTPS id B3795C2BCB4; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769590197; bh=jPApKe4OnUHqDCmVrRe+5LbHO4U2RPR4SqBfUuQaobI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Mr/PhjvkPWThtzj+jBqy7ij02xYvR6N/zfnZDu3NIpKaaifanMfxhYK3YUFKSQ6BH hOoPmzFi7tI9L04vrY3Mdgre55/DqW5LoGUtspGCAB3egoipohTp0FktlAWw+tpltW nNM60cvAcEj/OQdjvr1aj8w6VOhsPmFp03JqiAkkIws+9n6C1fcsmxOUCt9Sk0RA6i 6ejhrt+O7QoMBI2zGbovryvg8tvkMbmO+nmCFMXvSEZex2FPhtzVig4orcOgM+goq7 jerw3g46/E9/gmMKw6AnJ8lJW0oG/rYBUC1py18/DgjxzSCLSRDoimdEy94RGCSOtg YMh9RczEnIAAw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0C85D35692; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Wed, 28 Jan 2026 09:49:54 +0100 Subject: [PATCH v4 3/4] arm64: dts: s32: set Ethernet channel irqs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-dwmac_multi_irq-v4-3-82fa34fcf2f2@oss.nxp.com> References: <20260128-dwmac_multi_irq-v4-0-82fa34fcf2f2@oss.nxp.com> In-Reply-To: <20260128-dwmac_multi_irq-v4-0-82fa34fcf2f2@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769590195; l=4163; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=+bEJwX/3spHrmCusaHSSPK6wPAR1HCTfpAlGDA5P1YA=; b=vIN+HXciTpOHUqUDxNPWM6CkKic057xj2uyyBnyM5d/9gwSF2zq5RrS5qanARCUGxClzBMw74 4gX5zl4Eh37DGUy1maQF2fOrE/zajahR9r8le6wXCP3kFez45HrDOJs X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The GMAC Ethernet controller found on S32G2/S32G3 and S32R45 contains up to 5 RX and 5 TX channels. It can operate in two interrupt modes: 1) Sharing IRQ mode: only MAC IRQ line is used for all channels. 2) Multiple IRQ mode: every channel uses two IRQ lines, one for RX and second for TX. Specify all IRQ twins for all channels. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++++++++++++++++++--- arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 +++++++++++++++++++++++--- 2 files changed, 46 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 51d00dac12de..5a553d503137 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright 2017-2021, 2024-2025 NXP + * Copyright 2017-2021, 2024-2026 NXP */ =20 #include @@ -732,8 +732,28 @@ gmac0: ethernet@4033c000 { reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; status =3D "disabled"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index eff7673e7f34..e1f248d3aedb 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2025 NXP + * Copyright 2021-2026 NXP * * Authors: Ghennadi Procopciuc * Ciprian Costea @@ -809,8 +809,28 @@ gmac0: ethernet@4033c000 { reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; status =3D "disabled"; --=20 2.47.0 From nobody Sun Feb 8 17:13:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AF7933A71A; Wed, 28 Jan 2026 08:49:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769590198; cv=none; b=mZhYSTToRrnpJJyqmq9rvf29f+DU+w9/MB9aXLyVncVhtHjwqq7XnHvxRehR3HlbvJyKsSKn2GnEtZZOb/cSUbSjExhVtezf21Hpt+uDbO6qsK/RRmtkt/oWhRVHyGgBuWwPbjNQYi4lRhcvAdvtR+/AHniZAT8jKTnP7yuDKUU= ARC-Message-Signature: i=1; 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b=bALrlQbEMGkAolqBk9DExUb3FBfk1ov2ZITw/sUoCznI4ThO9/XJ/4NlBm13YPqIY t3ExTvN9Dc32S4zyJaiXumqHht/k6o3GhCQbwRtQX1Mr+8EptUMOWKP5xy7g6YBrBW iI8MoWLUj081fdkXAtB1/Pyi5uxUE1yanzXjDfh5YFA0aul3FR/EA9uW/2Nqg34iAV hhaPBq/mqzpXZojIODSrbySkuJ7rEv6zJ4PdCT4aF0z7kXAZnXpAXCwlw+JDahCbNS f4QuTecSIZO4j+NSAilyrcdK/Njc0dmBBr2pnZm303MloSMJFEfg2Urwhjjmm/VZCm X7st+jKcsX0ng== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C71E5D35694; Wed, 28 Jan 2026 08:49:57 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Wed, 28 Jan 2026 09:49:55 +0100 Subject: [PATCH v4 4/4] stmmac: s32: enable support for Multi-IRQ mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260128-dwmac_multi_irq-v4-4-82fa34fcf2f2@oss.nxp.com> References: <20260128-dwmac_multi_irq-v4-0-82fa34fcf2f2@oss.nxp.com> In-Reply-To: <20260128-dwmac_multi_irq-v4-0-82fa34fcf2f2@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769590195; l=3825; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=F5iLqXdHMZ2qiiJkqKhxBpUsPyBKNhvXgKzEG4aoAks=; b=GMmeRxime6Zalz6f8cJNInShlnHl2IGRspApM3aNDxKsncINGGej0ms30rkwEIshXjUDTw4hS pLuP9QH+OdyD4LrfdukIsvsC6+xAkZUEhQkih4wlGHMk13XiWnhWw7R X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" To get enabled Multi-IRQ mode, the driver checks: 1) property of 'snps,mtl-xx-config' subnode defines 'snps,xx-queues-to-use' bigger then one, ie: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; ... snps,mtl-rx-config =3D <&mtl_rx_setup>; ... mtl_rx_setup: rx-queues-config { snps,rx-queues-to-use =3D <2>; }; 2) queue based IRQs are set, ie: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; ... interrupts =3D , /* CHN 0: tx, rx */ , , /* CHN 1: tx, rx */ , ; interrupt-names =3D "macirq", "tx-queue-0", "rx-queue-0", "tx-queue-1", "rx-queue-1"; If those prerequisites are met, the driver switch to Multi-IRQ mode, using per-queue IRQs for rx/tx data pathr: [ 1.387045] s32-dwmac 4033c000.ethernet: Multi-IRQ mode (per queue IRQs)= selected Now the driver owns all queues IRQs: root@s32g399aevb3:~# grep eth /proc/interrupts 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac 30: 0 0 0 0 0 0 0 0 GICv3 91 Level eth0:rx-0 31: 0 0 0 0 0 0 0 0 GICv3 93 Level eth0:rx-1 32: 0 0 0 0 0 0 0 0 GICv3 95 Level eth0:rx-2 33: 0 0 0 0 0 0 0 0 GICv3 97 Level eth0:rx-3 34: 0 0 0 0 0 0 0 0 GICv3 99 Level eth0:rx-4 35: 0 0 0 0 0 0 0 0 GICv3 90 Level eth0:tx-0 36: 0 0 0 0 0 0 0 0 GICv3 92 Level eth0:tx-1 37: 0 0 0 0 0 0 0 0 GICv3 94 Level eth0:tx-2 38: 0 0 0 0 0 0 0 0 GICv3 96 Level eth0:tx-3 39: 0 0 0 0 0 0 0 0 GICv3 98 Level eth0:tx-4 Otherwise, if one of the prerequisite don't met, the driver continue with MAC IRQ mode: [ 1.387045] s32-dwmac 4033c000.ethernet: MAC IRQ mode selected And only MAC IRQ will be attached: root@s32g399aevb3:~# grep eth /proc/interrupts 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac What represents the original MAC IRQ mode and is fully backward compatible. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/= ethernet/stmicro/stmmac/dwmac-s32.c index 5a485ee98fa7..37a5b7b46973 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c @@ -2,7 +2,7 @@ /* * NXP S32G/R GMAC glue layer * - * Copyright 2019-2024 NXP + * Copyright 2019-2026 NXP * */ =20 @@ -149,6 +149,16 @@ static int s32_dwmac_probe(struct platform_device *pde= v) plat->core_type =3D DWMAC_CORE_GMAC4; plat->pmt =3D 1; plat->flags |=3D STMMAC_FLAG_SPH_DISABLE; + + /* Check for multi-IRQ config. Assumption: symetrical rx/tx queues */ + if (plat->rx_queues_to_use > 1 && + (res.rx_irq[0] > 0 && res.tx_irq[0] > 0)) { + plat->flags |=3D STMMAC_FLAG_MULTI_MSI_EN; + dev_info(dev, "Multi-IRQ mode (per queue IRQs) selected\n"); + } else { + dev_info(dev, "MAC IRQ mode selected\n"); + } + plat->rx_fifo_size =3D 20480; plat->tx_fifo_size =3D 20480; =20 --=20 2.47.0