From nobody Sat Feb 7 15:59:54 2026 Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFDCC32BF43; Tue, 27 Jan 2026 21:47:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.19.166.228 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769550427; cv=none; b=obPZqTOZXwGuP/lNmwLCLH9gz75mbTOMWJ2adXMsvqOdrfQPhVg7EGjf441d/Qu6CmNxbxM8uUEk6HL1rglXbmhn7l9SZ/IyyJ8vKVpws+g4e6IvIKU8Obfoyammjfa5MLHJgwadbFUvgshyvYIBRERABolQkHPs6Nmy3in8Yx4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769550427; c=relaxed/simple; bh=HTp+Do+BE5EGcVI/v3yRKJyoUKPYpIeDXAWsrGMIs+E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z+ZKHJK6eVqyDYbqA7nfYDLp3oGteBZeMwdgrmfuz77Vn5aVICkJ7FStLP7o6ruRwbSz5RtN2uXdOyqSSswo5fMVGs7/mXkfbqZuvYp4x4T5QItMPmM11MnnuI2GHlIGfbvDu3SQhMFeptG9+g+tbYoEmduUjDt80amdxXIDJhU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=JL/m4LRo; arc=none smtp.client-ip=192.19.166.228 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="JL/m4LRo" Received: from mail-lvn-it-01.broadcom.com (mail-lvn-it-01.lvn.broadcom.net [10.36.132.253]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id 863FDC0010F7; Tue, 27 Jan 2026 13:46:59 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 863FDC0010F7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1769550419; bh=HTp+Do+BE5EGcVI/v3yRKJyoUKPYpIeDXAWsrGMIs+E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JL/m4LRoHff4Yo/FCjV4dCOBQYkMHaUEBiHdlEVKXOc5CBzgp0ZanD+0jig0AY8IX 8sz4TfM5lQsSvYPkg0AZbD66m9AmmaKDuo3CVwowxMdroPAYY3du8W/xtCCcnjuu3g Xvh78SO3TFvIh6oa2zwcj7MnbraxNJWYKSQF1bGM= Received: from fainelli-desktop.igp.broadcom.net (fainelli-desktop.dhcp.broadcom.net [10.67.48.245]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail-lvn-it-01.broadcom.com (Postfix) with ESMTPSA id 6743D199D1; Tue, 27 Jan 2026 13:46:59 -0800 (PST) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Doug Berger , Florian Fainelli , Broadcom internal kernel review list , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Christophe Leroy , linux-gpio@vger.kernel.org (open list:GPIO SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH v2 1/3] gpio: brcmstb: correct hwirq to bank map Date: Tue, 27 Jan 2026 13:46:54 -0800 Message-ID: <20260127214656.447333-2-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260127214656.447333-1-florian.fainelli@broadcom.com> References: <20260127214656.447333-1-florian.fainelli@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Doug Berger The brcmstb_gpio_hwirq_to_bank() function was designed to accommodate the downward numbering of dynamic GPIOs by traversing the bank list in the reverse order. However, the dynamic numbering has changed to increment upward which can produce an incorrect mapping. The function is modified to no longer assume an ordering of the list to accommodate either option. Fixes: 7b61212f2a07 ("gpiolib: Get rid of ARCH_NR_GPIOS") Signed-off-by: Doug Berger Signed-off-by: Florian Fainelli Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij --- drivers/gpio/gpio-brcmstb.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c index af9287ff5dc4..2352d099709c 100644 --- a/drivers/gpio/gpio-brcmstb.c +++ b/drivers/gpio/gpio-brcmstb.c @@ -301,12 +301,10 @@ static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_t= o_bank( struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq) { struct brcmstb_gpio_bank *bank; - int i =3D 0; =20 - /* banks are in descending order */ - list_for_each_entry_reverse(bank, &priv->bank_list, node) { - i +=3D bank->chip.gc.ngpio; - if (hwirq < i) + list_for_each_entry(bank, &priv->bank_list, node) { + if (hwirq >=3D bank->chip.gc.offset && + hwirq < (bank->chip.gc.offset + bank->chip.gc.ngpio)) return bank; } return NULL; --=20 2.43.0 From nobody Sat Feb 7 15:59:54 2026 Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93AC328A3FA; Tue, 27 Jan 2026 21:47:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.19.166.231 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769550427; cv=none; b=gLGLCQplJtGbqufbfIiupSpmhiMxghpSDeiddnCCjhIAR+w1TJGhjSY+YeBW5x9GFaZLOENn17nj86ibfr33Gy0RkQNAA3fk+osKKnuIfou9aa16LBK7Qz5aavzE5ydqdgQ8E/v0pCb7sf4ST2H2HoSrUrzo5M47TfeYCAb4Vf8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769550427; c=relaxed/simple; bh=L374EcJRAc/qEjuY/FVQi+JhFU4/ncCIa2WaXKx/r3M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dxQ85bG+AyBG98Ap66bdE7ywViJesF4Jnu8cCXjeOQCqOcCM+dNHZZzcPjIMWliyLiU1VrIV0UJngml15WHL1POPKNDhC/QkhkO3j8X8L6a9h+HUcHwf3+JM+pxbO2WM8MPFzD77eygwu38ucWNsfew7Vlb4N0mHxoEBSKZpakI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com; spf=fail smtp.mailfrom=broadcom.com; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b=oHRqNqF+; arc=none smtp.client-ip=192.19.166.231 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=broadcom.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=broadcom.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="oHRqNqF+" Received: from mail-lvn-it-01.broadcom.com (mail-lvn-it-01.lvn.broadcom.net [10.36.132.253]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id B7644C000733; Tue, 27 Jan 2026 13:46:59 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com B7644C000733 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1769550419; bh=L374EcJRAc/qEjuY/FVQi+JhFU4/ncCIa2WaXKx/r3M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oHRqNqF+tyTHzIkMeUB9UZc25HkYip9O6CkZnbM8l9jwsOw3W7/6DgUtc3ABp0Lro Z7GNoVn2am/w2ZNt0f6/qEVhS6sZuOIWuogId44csbP7CF2lkUfAsCM34uRRgrVBXb 5KOcHb/haul/M3f7Ta63rDD+jEcnLZ+UJq7KTyC8= Received: from fainelli-desktop.igp.broadcom.net (fainelli-desktop.dhcp.broadcom.net [10.67.48.245]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail-lvn-it-01.broadcom.com (Postfix) with ESMTPSA id 9174D199D2; Tue, 27 Jan 2026 13:46:59 -0800 (PST) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Doug Berger , Florian Fainelli , Broadcom internal kernel review list , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Christophe Leroy , linux-gpio@vger.kernel.org (open list:GPIO SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH v2 2/3] gpio: brcmstb: implement irq_mask_ack Date: Tue, 27 Jan 2026 13:46:55 -0800 Message-ID: <20260127214656.447333-3-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260127214656.447333-1-florian.fainelli@broadcom.com> References: <20260127214656.447333-1-florian.fainelli@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Doug Berger The irq_mask_ack operation is slightly more efficient than doing irq_mask and irq_ack separately. More importantly for this driver it bypasses the check of irqd_irq_masked ensuring a previously masked but still active interrupt gets remasked if unmasked at the hardware level. This allows the driver to more efficiently unmask the wake capable interrupts when quiescing without needing to enable the irqs individually to clear the irqd_irq_masked state. Signed-off-by: Doug Berger Co-developed-by: Florian Fainelli Signed-off-by: Florian Fainelli Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij --- drivers/gpio/gpio-brcmstb.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c index 2352d099709c..bf0192b82276 100644 --- a/drivers/gpio/gpio-brcmstb.c +++ b/drivers/gpio/gpio-brcmstb.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -// Copyright (C) 2015-2017 Broadcom +// Copyright (C) 2015-2017, 2026 Broadcom =20 #include #include @@ -95,15 +95,13 @@ static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t= hwirq, return hwirq - bank->chip.gc.offset; } =20 -static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, - unsigned int hwirq, bool enable) +static void __brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, + unsigned int hwirq, bool enable) { struct brcmstb_gpio_priv *priv =3D bank->parent_priv; u32 mask =3D BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank)); u32 imask; =20 - guard(gpio_generic_lock_irqsave)(&bank->chip); - imask =3D gpio_generic_read_reg(&bank->chip, priv->reg_base + GIO_MASK(bank->id)); if (enable) @@ -114,6 +112,13 @@ static void brcmstb_gpio_set_imask(struct brcmstb_gpio= _bank *bank, priv->reg_base + GIO_MASK(bank->id), imask); } =20 +static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, + unsigned int hwirq, bool enable) +{ + guard(gpio_generic_lock_irqsave)(&bank->chip); + __brcmstb_gpio_set_imask(bank, hwirq, enable); +} + static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) { struct brcmstb_gpio_priv *priv =3D brcmstb_gpio_gc_to_priv(gc); @@ -135,6 +140,19 @@ static void brcmstb_gpio_irq_mask(struct irq_data *d) brcmstb_gpio_set_imask(bank, d->hwirq, false); } =20 +static void brcmstb_gpio_irq_mask_ack(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct brcmstb_gpio_bank *bank =3D gpiochip_get_data(gc); + struct brcmstb_gpio_priv *priv =3D bank->parent_priv; + u32 mask =3D BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank)); + + guard(gpio_generic_lock_irqsave)(&bank->chip); + __brcmstb_gpio_set_imask(bank, d->hwirq, false); + gpio_generic_write_reg(&bank->chip, + priv->reg_base + GIO_STAT(bank->id), mask); +} + static void brcmstb_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); @@ -471,6 +489,7 @@ static int brcmstb_gpio_irq_setup(struct platform_devic= e *pdev, priv->irq_chip.name =3D dev_name(dev); priv->irq_chip.irq_disable =3D brcmstb_gpio_irq_mask; priv->irq_chip.irq_mask =3D brcmstb_gpio_irq_mask; + priv->irq_chip.irq_mask_ack =3D brcmstb_gpio_irq_mask_ack; priv->irq_chip.irq_unmask =3D brcmstb_gpio_irq_unmask; priv->irq_chip.irq_ack =3D brcmstb_gpio_irq_ack; priv->irq_chip.irq_set_type =3D brcmstb_gpio_irq_set_type; --=20 2.43.0 From nobody Sat Feb 7 15:59:54 2026 Received: from relay.smtp-ext.broadcom.com (relay.smtp-ext.broadcom.com [192.19.166.231]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93A5226ED37; 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Tue, 27 Jan 2026 13:46:59 -0800 (PST) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Doug Berger , Florian Fainelli , Broadcom internal kernel review list , Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Christophe Leroy , linux-gpio@vger.kernel.org (open list:GPIO SUBSYSTEM), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH v2 3/3] gpio: brcmstb: allow parent_irq to wake Date: Tue, 27 Jan 2026 13:46:56 -0800 Message-ID: <20260127214656.447333-4-florian.fainelli@broadcom.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260127214656.447333-1-florian.fainelli@broadcom.com> References: <20260127214656.447333-1-florian.fainelli@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Doug Berger The classic parent_wake_irq can only occur after the system has been placed into a hardware managed power management state. This prevents its use for waking from software managed suspend states like s2idle. By allowing the parent_irq to be enabled for wake enabled GPIO during suspend, these GPIO can now be used to wake from these states. The 'suspended' boolean is introduced to support wake event accounting. Signed-off-by: Doug Berger [florian: port changes after generic gpio chip conversion] Signed-off-by: Florian Fainelli Reviewed-by: Andy Shevchenko --- drivers/gpio/gpio-brcmstb.c | 90 +++++++++++++++++++++++++------------ 1 file changed, 62 insertions(+), 28 deletions(-) diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c index bf0192b82276..5489c3090aa1 100644 --- a/drivers/gpio/gpio-brcmstb.c +++ b/drivers/gpio/gpio-brcmstb.c @@ -54,6 +54,7 @@ struct brcmstb_gpio_priv { int parent_irq; int num_gpios; int parent_wake_irq; + bool suspended; }; =20 #define MAX_GPIO_PER_BANK 32 @@ -239,6 +240,9 @@ static int brcmstb_gpio_priv_set_wake(struct brcmstb_gp= io_priv *priv, { int ret =3D 0; =20 + if (priv->parent_wake_irq =3D=3D priv->parent_irq) + return ret; + if (enable) ret =3D enable_irq_wake(priv->parent_wake_irq); else @@ -289,6 +293,11 @@ static void brcmstb_gpio_irq_bank_handler(struct brcms= tb_gpio_bank *bank) while ((status =3D brcmstb_gpio_get_active_irqs(bank))) { unsigned int offset; =20 + if (priv->suspended && bank->wake_active & status) { + priv->suspended =3D false; + pm_wakeup_event(&priv->pdev->dev, 0); + } + for_each_set_bit(offset, &status, 32) { if (offset >=3D bank->width) dev_warn(&priv->pdev->dev, @@ -462,18 +471,18 @@ static int brcmstb_gpio_irq_setup(struct platform_dev= ice *pdev, } =20 if (of_property_read_bool(np, "wakeup-source")) { + /* + * Set wakeup capability so we can process boot-time + * "wakeups" (e.g., from S5 cold boot) + */ + device_set_wakeup_capable(dev, true); + device_wakeup_enable(dev); priv->parent_wake_irq =3D platform_get_irq(pdev, 1); if (priv->parent_wake_irq < 0) { - priv->parent_wake_irq =3D 0; + priv->parent_wake_irq =3D priv->parent_irq; dev_warn(dev, "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep"); } else { - /* - * Set wakeup capability so we can process boot-time - * "wakeups" (e.g., from S5 cold boot) - */ - device_set_wakeup_capable(dev, true); - device_wakeup_enable(dev); err =3D devm_request_irq(dev, priv->parent_wake_irq, brcmstb_gpio_wake_irq_handler, IRQF_SHARED, @@ -484,6 +493,7 @@ static int brcmstb_gpio_irq_setup(struct platform_devic= e *pdev, goto out_free_domain; } } + priv->irq_chip.irq_set_wake =3D brcmstb_gpio_irq_set_wake; } =20 priv->irq_chip.name =3D dev_name(dev); @@ -494,9 +504,6 @@ static int brcmstb_gpio_irq_setup(struct platform_devic= e *pdev, priv->irq_chip.irq_ack =3D brcmstb_gpio_irq_ack; priv->irq_chip.irq_set_type =3D brcmstb_gpio_irq_set_type; =20 - if (priv->parent_wake_irq) - priv->irq_chip.irq_set_wake =3D brcmstb_gpio_irq_set_wake; - irq_set_chained_handler_and_data(priv->parent_irq, brcmstb_gpio_irq_handler, priv); irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY); @@ -519,16 +526,11 @@ static void brcmstb_gpio_bank_save(struct brcmstb_gpi= o_priv *priv, priv->reg_base + GIO_BANK_OFF(bank->id, i)); } =20 -static void brcmstb_gpio_quiesce(struct device *dev, bool save) +static void brcmstb_gpio_quiesce(struct brcmstb_gpio_priv *priv, bool save) { - struct brcmstb_gpio_priv *priv =3D dev_get_drvdata(dev); struct brcmstb_gpio_bank *bank; u32 imask; =20 - /* disable non-wake interrupt */ - if (priv->parent_irq >=3D 0) - disable_irq(priv->parent_irq); - list_for_each_entry(bank, &priv->bank_list, node) { if (save) brcmstb_gpio_bank_save(priv, bank); @@ -546,8 +548,14 @@ static void brcmstb_gpio_quiesce(struct device *dev, b= ool save) =20 static void brcmstb_gpio_shutdown(struct platform_device *pdev) { + struct brcmstb_gpio_priv *priv =3D dev_get_drvdata(&pdev->dev); + + /* disable interrupts */ + if (priv->parent_irq > 0) + disable_irq(priv->parent_irq); + /* Enable GPIO for S5 cold boot */ - brcmstb_gpio_quiesce(&pdev->dev, false); + brcmstb_gpio_quiesce(priv, false); } =20 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv, @@ -563,7 +571,32 @@ static void brcmstb_gpio_bank_restore(struct brcmstb_g= pio_priv *priv, =20 static int brcmstb_gpio_suspend(struct device *dev) { - brcmstb_gpio_quiesce(dev, true); + struct brcmstb_gpio_priv *priv =3D dev_get_drvdata(dev); + + if (priv->parent_irq > 0) + priv->suspended =3D true; + + return 0; +} + +static int brcmstb_gpio_suspend_noirq(struct device *dev) +{ + struct brcmstb_gpio_priv *priv =3D dev_get_drvdata(dev); + + /* Catch any wakeup sources occurring between suspend and noirq */ + if (!priv->suspended) + return -EBUSY; + + /* disable interrupts while we save the masks */ + if (priv->parent_irq > 0) + disable_irq(priv->parent_irq); + + brcmstb_gpio_quiesce(priv, true); + + /* Now that the masks have been saved re-enable interrupts */ + if (priv->parent_wake_irq) + enable_irq(priv->parent_irq); + return 0; } =20 @@ -571,25 +604,26 @@ static int brcmstb_gpio_resume(struct device *dev) { struct brcmstb_gpio_priv *priv =3D dev_get_drvdata(dev); struct brcmstb_gpio_bank *bank; - bool need_wakeup_event =3D false; =20 - list_for_each_entry(bank, &priv->bank_list, node) { - need_wakeup_event |=3D !!__brcmstb_gpio_get_active_irqs(bank); - brcmstb_gpio_bank_restore(priv, bank); - } + /* disable interrupts while we restore the masks */ + if (priv->parent_wake_irq) + disable_irq(priv->parent_irq); =20 - if (priv->parent_wake_irq && need_wakeup_event) - pm_wakeup_event(dev, 0); + priv->suspended =3D false; + + list_for_each_entry(bank, &priv->bank_list, node) + brcmstb_gpio_bank_restore(priv, bank); =20 - /* enable non-wake interrupt */ - if (priv->parent_irq >=3D 0) + /* re-enable interrupts */ + if (priv->parent_irq > 0) enable_irq(priv->parent_irq); =20 return 0; } =20 static const struct dev_pm_ops brcmstb_gpio_pm_ops =3D { - .suspend_noirq =3D pm_sleep_ptr(brcmstb_gpio_suspend), + .suspend =3D pm_sleep_ptr(brcmstb_gpio_suspend), + .suspend_noirq =3D pm_sleep_ptr(brcmstb_gpio_suspend_noirq), .resume_noirq =3D pm_sleep_ptr(brcmstb_gpio_resume), }; =20 --=20 2.43.0