From nobody Sun Feb 8 19:30:30 2026 Received: from dilbert.mork.no (dilbert.mork.no [65.108.154.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A29B355811; Tue, 27 Jan 2026 12:56:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=65.108.154.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769518591; cv=none; b=qd2cEEib4LCgV17bzz4OdgakLz2Zts87LhSvwI4RyU4OaxCbh5NTa7UyGsPIxagG6AS4lMuBrkAmciQchzqbmgziB7jpisq7qcqovnkaHyMBvVETDYa5HjfiNC2x+HaRNcb6y6Z+JuTuJUkNWoRJj5VyySAt2s5/xjChsBV5dD0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769518591; c=relaxed/simple; bh=NjlUr8YbkYomUklK5X+zoXxx6QhhxpjaDQzOHwc+CNo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CvXdZIWCcegFtfjSH8j8vOwt6RxOZ4g4cb8efb0qcsij2mBaSwx8h+LCz5EGwo86lrb9wCc89/L0JwLejrQ8A8EpUBMQlsfm1qpn93UUdVQpHri8lhlorAxqlu+6FqNe56eBiSCPm24xDLduGDCwwOFcB/JT2qyFssDISD6eRuI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mork.no; spf=pass smtp.mailfrom=miraculix.mork.no; dkim=pass (1024-bit key) header.d=mork.no header.i=@mork.no header.b=AOUaY4MN; arc=none smtp.client-ip=65.108.154.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mork.no Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=miraculix.mork.no Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mork.no header.i=@mork.no header.b="AOUaY4MN" Authentication-Results: dilbert.mork.no; dkim=pass (1024-bit key; secure) header.d=mork.no header.i=@mork.no header.a=rsa-sha256 header.s=b header.b=AOUaY4MN; dkim-atps=neutral Received: from canardo.dyn.mork.no ([IPv6:2a01:799:10e2:d900:0:0:0:1]) (authenticated bits=0) by dilbert.mork.no (8.18.1/8.18.1) with ESMTPSA id 60RCtseW1881659 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=OK); Tue, 27 Jan 2026 12:55:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mork.no; s=b; t=1769518553; bh=BDZ1ZTsCnzg8RfIBIHFCXrzN5KG1B8Tq0jMUU+UYhh4=; h=From:To:Cc:Subject:Date:Message-ID:References:From; b=AOUaY4MNcDhRcBnUh7bQ9tGbpkAHGAHXW6zkKLT0CygAIt0uOogGOcr+ctvpw7BrX o8EUPxxNgkNQEYOvhC9cHhLgEZ7vqslkCi9svrkqUE3n6OmjNGwM3KoxaOfFaVRhdQ 1x9PjAzGutb5ijhgF6lf7/qO4aqC2o/nsBBzmqVc= Received: from miraculix.mork.no ([IPv6:2a01:799:10e2:d90a:6f50:7559:681d:630c]) (authenticated bits=0) by canardo.dyn.mork.no (8.18.1/8.18.1) with ESMTPSA id 60RCtro5908904 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=OK); Tue, 27 Jan 2026 13:55:53 +0100 Received: (nullmailer pid 1475185 invoked by uid 1000); Tue, 27 Jan 2026 12:55:52 -0000 From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= To: netdev@vger.kernel.org Cc: "Lucien.Jheng" , Daniel Golle , Vladimir Oltean , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org, =?UTF-8?q?Bj=C3=B8rn=20Mork?= Subject: [PATCH net-next v4 1/3] net: phy: air_en8811h: factor out shareable code Date: Tue, 27 Jan 2026 13:55:45 +0100 Message-ID: <20260127125547.1475164-2-bjorn@mork.no> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260127125547.1475164-1-bjorn@mork.no> References: <20260127125547.1475164-1-bjorn@mork.no> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: clamav-milter 1.4.3 at canardo.mork.no X-Virus-Status: Clean Create reusable helpers in preparation for the AN8811HB support. Signed-off-by: Bj=C3=B8rn Mork --- drivers/net/phy/air_en8811h.c | 59 +++++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 23 deletions(-) diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c index e890bb2c0aa8..392552692762 100644 --- a/drivers/net/phy/air_en8811h.c +++ b/drivers/net/phy/air_en8811h.c @@ -448,6 +448,11 @@ static int en8811h_wait_mcu_ready(struct phy_device *p= hydev) { int ret, reg_value; =20 + ret =3D air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_FINISH); + if (ret) + return ret; + /* Because of mdio-lock, may have to wait for multiple loads */ ret =3D phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, EN8811H_PHY_FW_STATUS, reg_value, @@ -461,9 +466,18 @@ static int en8811h_wait_mcu_ready(struct phy_device *p= hydev) return 0; } =20 -static int en8811h_load_firmware(struct phy_device *phydev) +static void en8811h_print_fw_version(struct phy_device *phydev) { struct en8811h_priv *priv =3D phydev->priv; + + air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, + &priv->firmware_version); + phydev_info(phydev, "MD32 firmware version: %08x\n", + priv->firmware_version); +} + +static int en8811h_load_firmware(struct phy_device *phydev) +{ struct device *dev =3D &phydev->mdio.dev; const struct firmware *fw1, *fw2; int ret; @@ -500,17 +514,11 @@ static int en8811h_load_firmware(struct phy_device *p= hydev) if (ret < 0) goto en8811h_load_firmware_out; =20 - ret =3D air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, - EN8811H_FW_CTRL_1_FINISH); + ret =3D en8811h_wait_mcu_ready(phydev); if (ret < 0) goto en8811h_load_firmware_out; =20 - ret =3D en8811h_wait_mcu_ready(phydev); - - air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, - &priv->firmware_version); - phydev_info(phydev, "MD32 firmware version: %08x\n", - priv->firmware_version); + en8811h_print_fw_version(phydev); =20 en8811h_load_firmware_out: release_firmware(fw2); @@ -533,11 +541,6 @@ static int en8811h_restart_mcu(struct phy_device *phyd= ev) if (ret < 0) return ret; =20 - ret =3D air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, - EN8811H_FW_CTRL_1_FINISH); - if (ret < 0) - return ret; - return en8811h_wait_mcu_ready(phydev); } =20 @@ -919,6 +922,23 @@ static int en8811h_clk_provider_setup(struct device *d= ev, struct clk_hw *hw) return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); } =20 +static int en8811h_leds_setup(struct phy_device *phydev) +{ + struct en8811h_priv *priv =3D phydev->priv; + int ret; + + priv->led[0].rules =3D AIR_DEFAULT_TRIGGER_LED0; + priv->led[1].rules =3D AIR_DEFAULT_TRIGGER_LED1; + priv->led[2].rules =3D AIR_DEFAULT_TRIGGER_LED2; + + ret =3D air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, + AIR_LED_MODE_DISABLE); + if (ret < 0) + phydev_err(phydev, "Failed to disable leds: %d\n", ret); + + return ret; +} + static int en8811h_probe(struct phy_device *phydev) { struct en8811h_priv *priv; @@ -937,19 +957,12 @@ static int en8811h_probe(struct phy_device *phydev) /* mcu has just restarted after firmware load */ priv->mcu_needs_restart =3D false; =20 - priv->led[0].rules =3D AIR_DEFAULT_TRIGGER_LED0; - priv->led[1].rules =3D AIR_DEFAULT_TRIGGER_LED1; - priv->led[2].rules =3D AIR_DEFAULT_TRIGGER_LED2; - /* MDIO_DEVS1/2 empty, so set mmds_present bits here */ phydev->c45_ids.mmds_present |=3D MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; =20 - ret =3D air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, - AIR_LED_MODE_DISABLE); - if (ret < 0) { - phydev_err(phydev, "Failed to disable leds: %d\n", ret); + ret =3D en8811h_leds_setup(phydev); + if (ret < 0) return ret; - } =20 priv->phydev =3D phydev; /* Co-Clock Output */ --=20 2.47.3 From nobody Sun Feb 8 19:30:30 2026 Received: from dilbert.mork.no (dilbert.mork.no [65.108.154.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 274753559CB; Tue, 27 Jan 2026 12:56:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=65.108.154.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769518592; cv=none; b=Ih6vfYZIi7JoTTO1FppLsCOArl5AlDQyOYQg1Soj9/dJxm1y3D0ZVjbCHSuUCCR/5ARmdmR4kLhS6DVfvPq3CbUsdwUC4PqkCd+dltJVA+Q/2fazFuWkUAD61dtQPZOAkptbm5Kv+NABVkvF+1Rr5/RTK3Vjf6vRThdzYYTlY2o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769518592; c=relaxed/simple; bh=XI3IIHTPYNeu4vR+1dNNZenaEjcb/V+x+yNP1OTAetM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VYA/TpXo55ndz9zJPC89cq33uYB04YBl1B9ATlO1Jil5FsbAF5/diOCxX5K7I+NwC5j+YBSo00WoMg0/uvNHni0g+IXHl0NOKt18GQIurk5R3LWN6jV8PjarTY/6NjeUhXrGtmBfpyjKkt0/UT26caic72WRuibeMinzk76ty2E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mork.no; spf=pass smtp.mailfrom=miraculix.mork.no; dkim=pass (1024-bit key) header.d=mork.no header.i=@mork.no header.b=cf+aJa7X; arc=none smtp.client-ip=65.108.154.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mork.no Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=miraculix.mork.no Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mork.no header.i=@mork.no header.b="cf+aJa7X" Authentication-Results: dilbert.mork.no; dkim=pass (1024-bit key; secure) header.d=mork.no header.i=@mork.no header.a=rsa-sha256 header.s=b header.b=cf+aJa7X; dkim-atps=neutral Received: from canardo.dyn.mork.no ([IPv6:2a01:799:10e2:d900:0:0:0:1]) (authenticated bits=0) by dilbert.mork.no (8.18.1/8.18.1) with ESMTPSA id 60RCtrrQ1881657 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=OK); Tue, 27 Jan 2026 12:55:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mork.no; s=b; t=1769518553; bh=tcCbKAJ8RAVc5JmtjvMD59tf+XABvL566cGxsIVQCBo=; h=From:To:Cc:Subject:Date:Message-ID:References:From; b=cf+aJa7XZ/sDoAusvTGwdprpKclRpK3ZeqyNkR94RNRVwN7sfmVBOBY6UwOFDjYyW e2uyeFEmpCHTZJjeaNegFIg3RK394pQ1AVSaBXkKzYWNEPuV0cDKpRgWNMkUYZIiPF stUb8P75sTlV90X9V4aXXcTET+pJsArKvtqkpqpQ= Received: from miraculix.mork.no ([IPv6:2a01:799:10e2:d90a:6f50:7559:681d:630c]) (authenticated bits=0) by canardo.dyn.mork.no (8.18.1/8.18.1) with ESMTPSA id 60RCtr6v908886 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=OK); Tue, 27 Jan 2026 13:55:53 +0100 Received: (nullmailer pid 1475188 invoked by uid 1000); Tue, 27 Jan 2026 12:55:52 -0000 From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= To: netdev@vger.kernel.org Cc: "Lucien.Jheng" , Daniel Golle , Vladimir Oltean , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org, =?UTF-8?q?Bj=C3=B8rn=20Mork?= Subject: [PATCH net-next v4 2/3] net: phy: air_en8811h: add Airoha AN8811HB support Date: Tue, 27 Jan 2026 13:55:46 +0100 Message-ID: <20260127125547.1475164-3-bjorn@mork.no> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260127125547.1475164-1-bjorn@mork.no> References: <20260127125547.1475164-1-bjorn@mork.no> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: clamav-milter 1.4.3 at canardo.mork.no X-Virus-Status: Clean The Airoha AN8811HB is mostly compatible with the EN8811H, adding 10Base-T support and reducing power consumption. This driver is based on the air_an8811hb v0.0.4 out-of-tree driver written by "Lucien.Jheng " Firmware is available in linux-firmware. The driver has been tested with firmware version 25110702 Signed-off-by: Bj=C3=B8rn Mork --- Cc: Lucien.Jheng Cc: Daniel Golle Cc: Vladimir Oltean --- drivers/net/phy/air_en8811h.c | 280 ++++++++++++++++++++++++++++++++-- 1 file changed, 269 insertions(+), 11 deletions(-) diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c index 392552692762..67a1bf60255f 100644 --- a/drivers/net/phy/air_en8811h.c +++ b/drivers/net/phy/air_en8811h.c @@ -1,14 +1,15 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Driver for the Airoha EN8811H 2.5 Gigabit PHY. + * Driver for the Airoha EN8811H and AN8811HB 2.5 Gigabit PHYs. * - * Limitations of the EN8811H: + * Limitations: * - Only full duplex supported * - Forced speed (AN off) is not supported by hardware (100Mbps) * * Source originated from airoha's en8811h.c and en8811h.h v1.2.1 + * with AN8811HB bits from air_an8811hb.c v0.0.4 * - * Copyright (C) 2023 Airoha Technology Corp. + * Copyright (C) 2023, 2026 Airoha Technology Corp. */ =20 #include @@ -21,9 +22,12 @@ #include =20 #define EN8811H_PHY_ID 0x03a2a411 +#define AN8811HB_PHY_ID 0xc0ff04a0 =20 #define EN8811H_MD32_DM "airoha/EthMD32.dm.bin" #define EN8811H_MD32_DSP "airoha/EthMD32.DSP.bin" +#define AN8811HB_MD32_DM "airoha/an8811hb/EthMD32_CRC.DM.bin" +#define AN8811HB_MD32_DSP "airoha/an8811hb/EthMD32_CRC.DSP.bin" =20 #define AIR_FW_ADDR_DM 0x00000000 #define AIR_FW_ADDR_DSP 0x00100000 @@ -31,6 +35,7 @@ /* MII Registers */ #define AIR_AUX_CTRL_STATUS 0x1d #define AIR_AUX_CTRL_STATUS_SPEED_MASK GENMASK(4, 2) +#define AIR_AUX_CTRL_STATUS_SPEED_10 0x0 #define AIR_AUX_CTRL_STATUS_SPEED_100 0x4 #define AIR_AUX_CTRL_STATUS_SPEED_1000 0x8 #define AIR_AUX_CTRL_STATUS_SPEED_2500 0xc @@ -56,6 +61,7 @@ #define EN8811H_PHY_FW_STATUS 0x8009 #define EN8811H_PHY_READY 0x02 =20 +#define AIR_PHY_MCU_CMD_0 0x800b #define AIR_PHY_MCU_CMD_1 0x800c #define AIR_PHY_MCU_CMD_1_MODE1 0x0 #define AIR_PHY_MCU_CMD_2 0x800d @@ -65,6 +71,10 @@ #define AIR_PHY_MCU_CMD_3_DOCMD 0x1100 #define AIR_PHY_MCU_CMD_4 0x800f #define AIR_PHY_MCU_CMD_4_MODE1 0x0002 +#define AIR_PHY_MCU_CMD_4_CABLE_PAIR_A 0x00d7 +#define AIR_PHY_MCU_CMD_4_CABLE_PAIR_B 0x00d8 +#define AIR_PHY_MCU_CMD_4_CABLE_PAIR_C 0x00d9 +#define AIR_PHY_MCU_CMD_4_CABLE_PAIR_D 0x00da #define AIR_PHY_MCU_CMD_4_INTCLR 0x00e4 =20 /* Registers on MDIO_MMD_VEND2 */ @@ -106,6 +116,9 @@ #define AIR_PHY_LED_BLINK_2500RX BIT(11) =20 /* Registers on BUCKPBUS */ +#define AIR_PHY_CONTROL 0x3a9c +#define AIR_PHY_CONTROL_INTERNAL BIT(11) + #define EN8811H_2P5G_LPA 0x3b30 #define EN8811H_2P5G_LPA_2P5G BIT(0) =20 @@ -129,6 +142,34 @@ #define EN8811H_FW_CTRL_2 0x800000 #define EN8811H_FW_CTRL_2_LOADING BIT(11) =20 +#define AN8811HB_CRC_PM_SET1 0xf020c +#define AN8811HB_CRC_PM_MON2 0xf0218 +#define AN8811HB_CRC_PM_MON3 0xf021c +#define AN8811HB_CRC_DM_SET1 0xf0224 +#define AN8811HB_CRC_DM_MON2 0xf0230 +#define AN8811HB_CRC_DM_MON3 0xf0234 +#define AN8811HB_CRC_RD_EN BIT(0) +#define AN8811HB_CRC_ST (BIT(0) | BIT(1)) +#define AN8811HB_CRC_CHECK_PASS BIT(0) + +#define AN8811HB_TX_POLARITY 0x5ce004 +#define AN8811HB_TX_POLARITY_NORMAL BIT(7) +#define AN8811HB_RX_POLARITY 0x5ce61c +#define AN8811HB_RX_POLARITY_NORMAL BIT(7) + +#define AN8811HB_GPIO_OUTPUT 0x5cf8b8 +#define AN8811HB_GPIO_OUTPUT_345 (BIT(3) | BIT(4) | BIT(5)) + +#define AN8811HB_HWTRAP1 0x5cf910 +#define AN8811HB_HWTRAP2 0x5cf914 +#define AN8811HB_HWTRAP2_CKO BIT(28) + +#define AN8811HB_CLK_DRV 0x5cf9e4 +#define AN8811HB_CLK_DRV_CKO_MASK GENMASK(14, 12) +#define AN8811HB_CLK_DRV_CKOPWD BIT(12) +#define AN8811HB_CLK_DRV_CKO_LDPWD BIT(13) +#define AN8811HB_CLK_DRV_CKO_LPPWD BIT(14) + /* Led definitions */ #define EN8811H_LED_COUNT 3 =20 @@ -466,6 +507,43 @@ static int en8811h_wait_mcu_ready(struct phy_device *p= hydev) return 0; } =20 +static int an8811hb_check_crc(struct phy_device *phydev, u32 set1, + u32 mon2, u32 mon3) +{ + u32 pbus_value; + int retry =3D 25; + int ret; + + /* Configure CRC */ + ret =3D air_buckpbus_reg_modify(phydev, set1, + AN8811HB_CRC_RD_EN, + AN8811HB_CRC_RD_EN); + if (ret < 0) + return ret; + air_buckpbus_reg_read(phydev, set1, &pbus_value); + + do { + msleep(300); + air_buckpbus_reg_read(phydev, mon2, &pbus_value); + + /* We do not know what errors this check is supposed + * catch or what to do about a failure. So print the + * result and continue like the vendor driver does. + */ + if (pbus_value & AN8811HB_CRC_ST) { + air_buckpbus_reg_read(phydev, mon3, &pbus_value); + phydev_dbg(phydev, "CRC Check %s!\n", + pbus_value & AN8811HB_CRC_CHECK_PASS ? + "PASS" : "FAIL"); + return air_buckpbus_reg_modify(phydev, set1, + AN8811HB_CRC_RD_EN, 0); + } + } while (--retry); + + phydev_err(phydev, "CRC Check is not ready (%u)\n", pbus_value); + return -ENODEV; +} + static void en8811h_print_fw_version(struct phy_device *phydev) { struct en8811h_priv *priv =3D phydev->priv; @@ -476,6 +554,54 @@ static void en8811h_print_fw_version(struct phy_device= *phydev) priv->firmware_version); } =20 +static int an8811hb_load_file(struct phy_device *phydev, const char *name, + u32 address) +{ + struct device *dev =3D &phydev->mdio.dev; + const struct firmware *fw; + int ret; + + ret =3D request_firmware_direct(&fw, name, dev); + if (ret < 0) + return ret; + + ret =3D air_write_buf(phydev, address, fw); + release_firmware(fw); + return ret; +} + +static int an8811hb_load_firmware(struct phy_device *phydev) +{ + int ret; + + ret =3D air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1, + EN8811H_FW_CTRL_1_START); + if (ret < 0) + return ret; + + ret =3D an8811hb_load_file(phydev, AN8811HB_MD32_DM, AIR_FW_ADDR_DM); + if (ret < 0) + return ret; + + ret =3D an8811hb_check_crc(phydev, AN8811HB_CRC_DM_SET1, + AN8811HB_CRC_DM_MON2, + AN8811HB_CRC_DM_MON3); + if (ret < 0) + return ret; + + ret =3D an8811hb_load_file(phydev, AN8811HB_MD32_DSP, AIR_FW_ADDR_DSP); + if (ret < 0) + return ret; + + ret =3D an8811hb_check_crc(phydev, AN8811HB_CRC_PM_SET1, + AN8811HB_CRC_PM_MON2, + AN8811HB_CRC_PM_MON3); + if (ret < 0) + return ret; + + return en8811h_wait_mcu_ready(phydev); +} + static int en8811h_load_firmware(struct phy_device *phydev) { struct device *dev =3D &phydev->mdio.dev; @@ -939,6 +1065,45 @@ static int en8811h_leds_setup(struct phy_device *phyd= ev) return ret; } =20 +static int an8811hb_probe(struct phy_device *phydev) +{ + struct en8811h_priv *priv; + int ret; + + priv =3D devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + phydev->priv =3D priv; + + ret =3D an8811hb_load_firmware(phydev); + if (ret < 0) { + phydev_err(phydev, "Load firmware failed: %d\n", ret); + return ret; + } + + en8811h_print_fw_version(phydev); + + /* mcu has just restarted after firmware load */ + priv->mcu_needs_restart =3D false; + + /* MDIO_DEVS1/2 empty, so set mmds_present bits here */ + phydev->c45_ids.mmds_present |=3D MDIO_DEVS_PMAPMD | MDIO_DEVS_AN; + + ret =3D en8811h_leds_setup(phydev); + if (ret < 0) + return ret; + + /* Configure led gpio pins as output */ + ret =3D air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, + AN8811HB_GPIO_OUTPUT_345, + AN8811HB_GPIO_OUTPUT_345); + if (ret < 0) + return ret; + + return 0; +} + static int en8811h_probe(struct phy_device *phydev) { struct en8811h_priv *priv; @@ -980,6 +1145,37 @@ static int en8811h_probe(struct phy_device *phydev) return 0; } =20 +static int an8811hb_config_serdes_polarity(struct phy_device *phydev) +{ + struct device *dev =3D &phydev->mdio.dev; + u32 pbus_value =3D 0; + unsigned int pol; + int ret; + + ret =3D phy_get_manual_rx_polarity(dev_fwnode(dev), + phy_modes(phydev->interface), &pol); + if (ret) + return ret; + if (pol =3D=3D PHY_POL_NORMAL) + pbus_value |=3D AN8811HB_RX_POLARITY_NORMAL; + ret =3D air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY, + AN8811HB_RX_POLARITY_NORMAL, + pbus_value); + if (ret < 0) + return ret; + + ret =3D phy_get_manual_tx_polarity(dev_fwnode(dev), + phy_modes(phydev->interface), &pol); + if (ret) + return ret; + pbus_value =3D 0; + if (pol =3D=3D PHY_POL_NORMAL) + pbus_value |=3D AN8811HB_TX_POLARITY_NORMAL; + return air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY, + AN8811HB_TX_POLARITY_NORMAL, + pbus_value); +} + static int en8811h_config_serdes_polarity(struct phy_device *phydev) { struct device *dev =3D &phydev->mdio.dev; @@ -1016,6 +1212,33 @@ static int en8811h_config_serdes_polarity(struct phy= _device *phydev) EN8811H_POLARITY_TX_NORMAL, pbus_value); } =20 +static int an8811hb_config_init(struct phy_device *phydev) +{ + struct en8811h_priv *priv =3D phydev->priv; + int ret; + + /* If restart happened in .probe(), no need to restart now */ + if (priv->mcu_needs_restart) { + ret =3D en8811h_restart_mcu(phydev); + if (ret < 0) + return ret; + } else { + /* Next calls to .config_init() mcu needs to restart */ + priv->mcu_needs_restart =3D true; + } + + ret =3D an8811hb_config_serdes_polarity(phydev); + if (ret < 0) + return ret; + + ret =3D air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR, + AIR_LED_MODE_USER_DEFINE); + if (ret < 0) + phydev_err(phydev, "Failed to initialize leds: %d\n", ret); + + return ret; +} + static int en8811h_config_init(struct phy_device *phydev) { struct en8811h_priv *priv =3D phydev->priv; @@ -1129,13 +1352,23 @@ static int en8811h_read_status(struct phy_device *p= hydev) if (ret < 0) return ret; =20 - /* Get link partner 2.5GBASE-T ability from vendor register */ - ret =3D air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value); - if (ret < 0) - return ret; - linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, - phydev->lp_advertising, - pbus_value & EN8811H_2P5G_LPA_2P5G); + if (phy_id_compare_model(phydev->phy_id, AN8811HB_PHY_ID)) { + val =3D phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); + if (val < 0) + return val; + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + phydev->lp_advertising, + val & MDIO_AN_10GBT_STAT_LP2_5G); + } else { + /* Get link partner 2.5GBASE-T ability from vendor register */ + ret =3D air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, + &pbus_value); + if (ret < 0) + return ret; + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + phydev->lp_advertising, + pbus_value & EN8811H_2P5G_LPA_2P5G); + } =20 if (phydev->autoneg_complete) phy_resolve_aneg_pause(phydev); @@ -1157,6 +1390,9 @@ static int en8811h_read_status(struct phy_device *phy= dev) case AIR_AUX_CTRL_STATUS_SPEED_100: phydev->speed =3D SPEED_100; break; + case AIR_AUX_CTRL_STATUS_SPEED_10: + phydev->speed =3D SPEED_10; + break; } =20 /* Firmware before version 24011202 has no vendor register 2P5G_LPA. @@ -1241,20 +1477,42 @@ static struct phy_driver en8811h_driver[] =3D { .led_brightness_set =3D air_led_brightness_set, .led_hw_control_set =3D air_led_hw_control_set, .led_hw_control_get =3D air_led_hw_control_get, +}, +{ + PHY_ID_MATCH_MODEL(AN8811HB_PHY_ID), + .name =3D "Airoha AN8811HB", + .probe =3D an8811hb_probe, + .get_features =3D en8811h_get_features, + .config_init =3D an8811hb_config_init, + .get_rate_matching =3D en8811h_get_rate_matching, + .config_aneg =3D en8811h_config_aneg, + .read_status =3D en8811h_read_status, + .config_intr =3D en8811h_clear_intr, + .handle_interrupt =3D en8811h_handle_interrupt, + .led_hw_is_supported =3D en8811h_led_hw_is_supported, + .read_page =3D air_phy_read_page, + .write_page =3D air_phy_write_page, + .led_blink_set =3D air_led_blink_set, + .led_brightness_set =3D air_led_brightness_set, + .led_hw_control_set =3D air_led_hw_control_set, + .led_hw_control_get =3D air_led_hw_control_get, } }; =20 module_phy_driver(en8811h_driver); =20 static const struct mdio_device_id __maybe_unused en8811h_tbl[] =3D { { PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) }, + { PHY_ID_MATCH_MODEL(AN8811HB_PHY_ID) }, { } }; =20 MODULE_DEVICE_TABLE(mdio, en8811h_tbl); MODULE_FIRMWARE(EN8811H_MD32_DM); MODULE_FIRMWARE(EN8811H_MD32_DSP); +MODULE_FIRMWARE(AN8811HB_MD32_DM); +MODULE_FIRMWARE(AN8811HB_MD32_DSP); =20 -MODULE_DESCRIPTION("Airoha EN8811H PHY drivers"); +MODULE_DESCRIPTION("Airoha EN8811H and AN8811HB PHY drivers"); MODULE_AUTHOR("Airoha"); MODULE_AUTHOR("Eric Woudstra "); MODULE_LICENSE("GPL"); --=20 2.47.3 From nobody Sun Feb 8 19:30:30 2026 Received: from dilbert.mork.no (dilbert.mork.no [65.108.154.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A322355816; Tue, 27 Jan 2026 12:56:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=65.108.154.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769518592; cv=none; b=O5sHjn2QVFrjBgMuThy0w1iArDhRF0GmJq9aOaozKA4sYZ4ulWsIm0ZTEHAqaaiL20BwwO+8T0e1BgGZi8EHvmwZmCfR+sv64Lnpg0Df0FpHbsUbUimDzlpELl3ZgA4Ej0IKLy4Wi8rv0pOW8ipjLoYIlS0fjc0UuKYVAY0ZGUU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769518592; c=relaxed/simple; bh=7q6n9P/VsWrFeGAC/iWRxdQO4ZpVwwUDs8T6d8XPmqs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XUlseLNUIHyYk1dUmJi4ddhtws6gcDbmnS0dSBlrUR5b80VT0aMeQKtv41bnsdyQJY93SWcLXoOV345JsrfjyiT+ZyaDVSHIQS53Ug1VhxhPj6HUrQ+4eNde3On0z7fjpXXS2/LufBD1powSPYde/tRFqU4xjvf1PbIvGj643/0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mork.no; spf=pass smtp.mailfrom=miraculix.mork.no; dkim=pass (1024-bit key) header.d=mork.no header.i=@mork.no header.b=NHm+9ynW; arc=none smtp.client-ip=65.108.154.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mork.no Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=miraculix.mork.no Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mork.no header.i=@mork.no header.b="NHm+9ynW" Authentication-Results: dilbert.mork.no; dkim=pass (1024-bit key; secure) header.d=mork.no header.i=@mork.no header.a=rsa-sha256 header.s=b header.b=NHm+9ynW; dkim-atps=neutral Received: from canardo.dyn.mork.no ([IPv6:2a01:799:10e2:d900:0:0:0:1]) (authenticated bits=0) by dilbert.mork.no (8.18.1/8.18.1) with ESMTPSA id 60RCtr331881658 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=OK); Tue, 27 Jan 2026 12:55:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mork.no; s=b; t=1769518553; bh=qT2SzI6DPeUnDnAQdGtCZKDKsWsV2Y1uoIX0LITzEK0=; h=From:To:Cc:Subject:Date:Message-ID:References:From; b=NHm+9ynWTtcV4lM53sESSs0yXzsJv/h0UyTQFqHuACNYmUBeQ5yKJQuwWHB9ceUN7 YHUKtjqbllZSRRmNmjIxJslKLZzACIC2JCOTW8SqHhDFgCehOpKUKUN6Yhr5I/vBVt wGVnwEkg4A8nnqywrdSYzmWS5/BhhIVZHW2teGtU= Received: from miraculix.mork.no ([IPv6:2a01:799:10e2:d90a:6f50:7559:681d:630c]) (authenticated bits=0) by canardo.dyn.mork.no (8.18.1/8.18.1) with ESMTPSA id 60RCtrm2908895 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=OK); Tue, 27 Jan 2026 13:55:53 +0100 Received: (nullmailer pid 1475191 invoked by uid 1000); Tue, 27 Jan 2026 12:55:53 -0000 From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= To: netdev@vger.kernel.org Cc: "Lucien.Jheng" , Daniel Golle , Vladimir Oltean , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org, =?UTF-8?q?Bj=C3=B8rn=20Mork?= Subject: [PATCH net-next v4 3/3] net: phy: air_en8811h: Add clk provider for an8811hb Date: Tue, 27 Jan 2026 13:55:47 +0100 Message-ID: <20260127125547.1475164-4-bjorn@mork.no> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260127125547.1475164-1-bjorn@mork.no> References: <20260127125547.1475164-1-bjorn@mork.no> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: clamav-milter 1.4.3 at canardo.mork.no X-Virus-Status: Clean Implement clk provider driver so we can disable the clock output when it isn't needed. This helps to reduce EMF noise Signed-off-by: Bj=C3=B8rn Mork --- drivers/net/phy/air_en8811h.c | 107 ++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/drivers/net/phy/air_en8811h.c b/drivers/net/phy/air_en8811h.c index 67a1bf60255f..29ae73e65caa 100644 --- a/drivers/net/phy/air_en8811h.c +++ b/drivers/net/phy/air_en8811h.c @@ -949,6 +949,105 @@ static int en8811h_led_hw_is_supported(struct phy_dev= ice *phydev, u8 index, return 0; }; =20 +static unsigned long an8811hb_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent) +{ + struct en8811h_priv *priv =3D clk_hw_to_en8811h_priv(hw); + struct phy_device *phydev =3D priv->phydev; + u32 pbus_value; + int ret; + + ret =3D air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value); + if (ret < 0) + return ret; + + return (pbus_value & AN8811HB_HWTRAP2_CKO) ? 50000000 : 25000000; +} + +static int an8811hb_clk_enable(struct clk_hw *hw) +{ + struct en8811h_priv *priv =3D clk_hw_to_en8811h_priv(hw); + struct phy_device *phydev =3D priv->phydev; + + return air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV, + AN8811HB_CLK_DRV_CKO_MASK, + AN8811HB_CLK_DRV_CKO_MASK); +} + +static void an8811hb_clk_disable(struct clk_hw *hw) +{ + struct en8811h_priv *priv =3D clk_hw_to_en8811h_priv(hw); + struct phy_device *phydev =3D priv->phydev; + + air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV, + AN8811HB_CLK_DRV_CKO_MASK, 0); +} + +static int an8811hb_clk_is_enabled(struct clk_hw *hw) +{ + struct en8811h_priv *priv =3D clk_hw_to_en8811h_priv(hw); + struct phy_device *phydev =3D priv->phydev; + u32 pbus_value; + int ret; + + ret =3D air_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value); + if (ret < 0) + return ret; + + return (pbus_value & AN8811HB_CLK_DRV_CKO_MASK); +} + +static int an8811hb_clk_save_context(struct clk_hw *hw) +{ + struct en8811h_priv *priv =3D clk_hw_to_en8811h_priv(hw); + + priv->cko_is_enabled =3D an8811hb_clk_is_enabled(hw); + + return 0; +} + +static void an8811hb_clk_restore_context(struct clk_hw *hw) +{ + struct en8811h_priv *priv =3D clk_hw_to_en8811h_priv(hw); + + if (!priv->cko_is_enabled) + an8811hb_clk_disable(hw); +} + +static const struct clk_ops an8811hb_clk_ops =3D { + .recalc_rate =3D an8811hb_clk_recalc_rate, + .enable =3D an8811hb_clk_enable, + .disable =3D an8811hb_clk_disable, + .is_enabled =3D an8811hb_clk_is_enabled, + .save_context =3D an8811hb_clk_save_context, + .restore_context =3D an8811hb_clk_restore_context, +}; + +static int an8811hb_clk_provider_setup(struct device *dev, struct clk_hw *= hw) +{ + struct clk_init_data init; + int ret; + + if (!IS_ENABLED(CONFIG_COMMON_CLK)) + return 0; + + init.name =3D devm_kasprintf(dev, GFP_KERNEL, "%s-cko", + fwnode_get_name(dev_fwnode(dev))); + if (!init.name) + return -ENOMEM; + + init.ops =3D &an8811hb_clk_ops; + init.flags =3D 0; + init.num_parents =3D 0; + hw->init =3D &init; + + ret =3D devm_clk_hw_register(dev, hw); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); +} + static unsigned long en8811h_clk_recalc_rate(struct clk_hw *hw, unsigned long parent) { @@ -1094,6 +1193,12 @@ static int an8811hb_probe(struct phy_device *phydev) if (ret < 0) return ret; =20 + priv->phydev =3D phydev; + /* Co-Clock Output */ + ret =3D an8811hb_clk_provider_setup(&phydev->mdio.dev, &priv->hw); + if (ret) + return ret; + /* Configure led gpio pins as output */ ret =3D air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT, AN8811HB_GPIO_OUTPUT_345, @@ -1487,6 +1592,8 @@ static struct phy_driver en8811h_driver[] =3D { .get_rate_matching =3D en8811h_get_rate_matching, .config_aneg =3D en8811h_config_aneg, .read_status =3D en8811h_read_status, + .resume =3D en8811h_resume, + .suspend =3D en8811h_suspend, .config_intr =3D en8811h_clear_intr, .handle_interrupt =3D en8811h_handle_interrupt, .led_hw_is_supported =3D en8811h_led_hw_is_supported, --=20 2.47.3