From nobody Sat Feb 7 05:01:13 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A680E2E7BB4; Tue, 27 Jan 2026 02:43:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769481794; cv=none; b=M0KpEkNTNiv0ZtOZdc2UHEVp3wYM4OqGWcZhqx+zgQ67sB9l7GzWVImIRH/AV8DQ7MKyZAN0FPAMUIY14/WqcPs8JpcimcLq5gh3HVpJ3EXBxYa6pETxgDSjjJlZGRYa3MBh2YCQDwOLpHE40KnYG7Cemk6QAuPbtuFbWxX4zL4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769481794; c=relaxed/simple; bh=s+fYGnA08QTeIzgiSM2+Kw5/k+uUaAOCCoUBmKF+exg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZyYBAW+e90BVfWuIF+TUT3LwIlFu7MisCI1GsDrFT3q5s+L/QIqCJHcPw3I3J5VR7Dd0G3MJQGQ52IHX4XjzkNV7VYJ0UzD3Y47+ir47W0wgdpDsrM3HRYvL4Dlo/fzKlTEzeU1KDAMmBVjXoZKKOC13tBsJGkoHG15KQntnS4I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=eXSxX0e+; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="eXSxX0e+" X-UUID: e6f62504fb2911f085319dbc3099e8fb-20260127 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mDYeX9hnxM609HsQNMFBzZYeMea5lku9+jD+ltF6O3E=; b=eXSxX0e+u4y6AJ3K3pmKn3j+p/JBSwgQA7Bj1MLGP37espcHC45hmMlGCuJEvBNWtXFJgmDjPH80hqroftrumhmCY29SaQnFFHoZppcwWfbaqvINT9LG8nsizqf6zKLzYCktO8DmuightphDCUimwvvTtxQ6Xl0n9v84Ir+W66I=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.11,REQID:eaaea2d2-adb0-4686-aa34-5c10a1e03856,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:89c9d04,CLOUDID:950c985a-a957-4259-bcca-d3af718d7034,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: e6f62504fb2911f085319dbc3099e8fb-20260127 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1999083699; Tue, 27 Jan 2026 10:43:03 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Tue, 27 Jan 2026 10:43:02 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Tue, 27 Jan 2026 10:43:01 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v7 01/10] dt-bindings: media: mediatek: decoder: Add MT8189 mediatek,vcodec-decoder Date: Tue, 27 Jan 2026 10:42:38 +0800 Message-ID: <20260127024248.18406-2-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260127024248.18406-1-kyrie.wu@mediatek.com> References: <20260127024248.18406-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add compatible for video decoder on MT8189 platform. Compared with former ICs, the MT8189 decoder use iommu to instead of smmu, and use scp architecture, the frequency is only 406MHZ, and cannot reach more than 700MHZ. It used only one clock. At the same time, the decoder supports the vp9 decoding protocol for the first time in single IC. Signed-off-by: Kyrie Wu Acked-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev= -decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-sub= dev-decoder.yaml index 74e1d88d3056..ee2bbbdb2d50 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decode= r.yaml @@ -75,6 +75,7 @@ properties: - mediatek,mt8192-vcodec-dec - mediatek,mt8186-vcodec-dec - mediatek,mt8188-vcodec-dec + - mediatek,mt8189-vcodec-dec - mediatek,mt8195-vcodec-dec - mediatek,mt8196-vcodec-dec =20 @@ -132,11 +133,11 @@ patternProperties: Refer to bindings/iommu/mediatek,iommu.yaml. =20 clocks: - minItems: 4 + minItems: 1 maxItems: 5 =20 clock-names: - minItems: 4 + minItems: 1 maxItems: 5 =20 assigned-clocks: --=20 2.45.2 From nobody Sat Feb 7 05:01:13 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F2892D8DB8; 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Tue, 27 Jan 2026 10:43:04 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Tue, 27 Jan 2026 10:43:03 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Tue, 27 Jan 2026 10:43:02 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v7 02/10] media: mediatek: decoder: Add a new platform data member Date: Tue, 27 Jan 2026 10:42:39 +0800 Message-ID: <20260127024248.18406-3-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260127024248.18406-1-kyrie.wu@mediatek.com> References: <20260127024248.18406-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" Add a new platform data member to indicate each decoder IC to avoid the chip name definition keep growing. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../mediatek/vcodec/decoder/mtk_vcodec_dec.h | 5 + .../vcodec/decoder/mtk_vcodec_dec_drv.c | 35 ++----- .../vcodec/decoder/mtk_vcodec_dec_drv.h | 15 +-- .../vcodec/decoder/mtk_vcodec_dec_hw.c | 2 +- .../vcodec/decoder/mtk_vcodec_dec_stateful.c | 1 + .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 92 ++++++++++++++----- 6 files changed, 86 insertions(+), 64 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.= h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h index 1af075fc0194..80cb46f1cded 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h @@ -69,6 +69,11 @@ extern const struct v4l2_m2m_ops mtk_vdec_m2m_ops; extern const struct media_device_ops mtk_vcodec_media_ops; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata; extern const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_single_core_pdata; =20 diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c index 7ed40936a0e8..c7af48f684c5 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c @@ -333,24 +333,7 @@ static const struct v4l2_file_operations mtk_vcodec_fo= ps =3D { =20 static void mtk_vcodec_dec_get_chip_name(struct mtk_vcodec_dec_dev *vdec_d= ev) { - struct device *dev =3D &vdec_dev->plat_dev->dev; - - if (of_device_is_compatible(dev->of_node, "mediatek,mt8173-vcodec-dec")) - vdec_dev->chip_name =3D MTK_VDEC_MT8173; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8183-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8183; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8192-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8192; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8195-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8195; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8186-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8186; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8188-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8188; - else if (of_device_is_compatible(dev->of_node, "mediatek,mt8196-vcodec-de= c")) - vdec_dev->chip_name =3D MTK_VDEC_MT8196; - else - vdec_dev->chip_name =3D MTK_VDEC_INVAL; + vdec_dev->chip_name =3D vdec_dev->vdec_pdata->chip_name; } =20 static int mtk_vcodec_probe(struct platform_device *pdev) @@ -369,10 +352,6 @@ static int mtk_vcodec_probe(struct platform_device *pd= ev) dev->plat_dev =3D pdev; =20 mtk_vcodec_dec_get_chip_name(dev); - if (dev->chip_name =3D=3D MTK_VDEC_INVAL) { - dev_err(&pdev->dev, "Failed to get decoder chip name"); - return -EINVAL; - } =20 dev->vdec_pdata =3D of_device_get_match_data(&pdev->dev); if (!of_property_read_u32(pdev->dev.of_node, "mediatek,vpu", @@ -389,7 +368,7 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) return -ENODEV; } dma_set_max_seg_size(&pdev->dev, UINT_MAX); - if (dev->chip_name =3D=3D MTK_VDEC_MT8196) { + if (dev->chip_name =3D=3D 8196) { ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36)); if (ret) { dev_err(&pdev->dev, "Failed to enable 36-bit DMA: %d\n", ret); @@ -558,23 +537,23 @@ static const struct of_device_id mtk_vcodec_match[] = =3D { }, { .compatible =3D "mediatek,mt8192-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8192_pdata, }, { .compatible =3D "mediatek,mt8186-vcodec-dec", - .data =3D &mtk_vdec_single_core_pdata, + .data =3D &mtk_vdec_8186_pdata, }, { .compatible =3D "mediatek,mt8195-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8195_pdata, }, { .compatible =3D "mediatek,mt8188-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8188_pdata, }, { .compatible =3D "mediatek,mt8196-vcodec-dec", - .data =3D &mtk_lat_sig_core_pdata, + .data =3D &mtk_vdec_8196_pdata, }, {}, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index 1cb77619add9..bb293ada6fb2 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -19,17 +19,6 @@ #define IS_VDEC_INNER_RACING(capability) ((capability) & MTK_VCODEC_INNER_= RACING) #define IS_VDEC_SUPPORT_EXT(capability) ((capability) & MTK_VDEC_IS_SUPPOR= T_EXT) =20 -enum mtk_vcodec_dec_chip_name { - MTK_VDEC_INVAL =3D 0, - MTK_VDEC_MT8173 =3D 8173, - MTK_VDEC_MT8183 =3D 8183, - MTK_VDEC_MT8186 =3D 8186, - MTK_VDEC_MT8188 =3D 8188, - MTK_VDEC_MT8192 =3D 8192, - MTK_VDEC_MT8195 =3D 8195, - MTK_VDEC_MT8196 =3D 8196, -}; - /* * enum mtk_vdec_format_types - Structure used to get supported * format types according to decoder capability @@ -106,6 +95,7 @@ struct vdec_pic_info { * * @is_subdev_supported: whether support parent-node architecture(subdev) * @uses_stateless_api: whether the decoder uses the stateless API with re= quests + * @chip_name: platforms configuration values */ struct mtk_vcodec_dec_pdata { void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx); @@ -127,6 +117,7 @@ struct mtk_vcodec_dec_pdata { =20 bool is_subdev_supported; bool uses_stateless_api; + unsigned int chip_name; }; =20 /** @@ -307,7 +298,7 @@ struct mtk_vcodec_dec_dev { struct mutex dec_racing_info_mutex; struct mtk_vcodec_dbgfs dbgfs; =20 - enum mtk_vcodec_dec_chip_name chip_name; + unsigned int chip_name; }; =20 static inline struct mtk_vcodec_dec_ctx *fh_to_dec_ctx(struct v4l2_fh *fh) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= hw.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c index e4e527fe54dc..a926dc14d39d 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_hw.c @@ -76,7 +76,7 @@ static void mtk_vdec_hw_clean_xpc(struct mtk_vdec_hw_dev = *dev) { u32 val, mask, addr =3D VDEC_XPC_CLEAN_ADDR; =20 - if (dev->main_dev->chip_name !=3D MTK_VDEC_MT8196) + if (dev->main_dev->chip_name !=3D 8196) return; =20 val =3D dev->hw_idx =3D=3D MTK_VDEC_LAT0 ? VDEC_XPC_LAT_VAL : VDEC_XPC_CO= RE_VAL; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c index aa9bdee7a96c..8ddb61670dc6 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c @@ -618,4 +618,5 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = =3D { .flush_decoder =3D mtk_vdec_flush_decoder, .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, + .chip_name =3D 8173, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index c1cef78471a9..0745bc3ee490 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -550,16 +550,16 @@ static void mtk_vcodec_dec_fill_h264_level(struct v4l= 2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8192: - case MTK_VDEC_MT8188: + case 8192: + case 8188: cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2; break; - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0; break; - case MTK_VDEC_MT8183: - case MTK_VDEC_MT8186: + case 8183: + case 8186: cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2; break; default: @@ -572,9 +572,9 @@ static void mtk_vcodec_dec_fill_h264_profile(struct v4l= 2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8188: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10; break; default: @@ -587,11 +587,11 @@ static void mtk_vcodec_dec_fill_h265_level(struct v4l= 2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: + case 8188: cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; break; - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2; break; default: @@ -604,9 +604,9 @@ static void mtk_vcodec_dec_fill_h265_profile(struct v4l= 2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8188: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10; break; default: @@ -619,15 +619,15 @@ static void mtk_vcodec_dec_fill_vp9_level(struct v4l2= _ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8192: - case MTK_VDEC_MT8188: + case 8192: + case 8188: cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1; break; - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2; break; - case MTK_VDEC_MT8186: + case 8186: cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1; break; default: @@ -640,9 +640,9 @@ static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2= _ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { switch (ctx->dev->chip_name) { - case MTK_VDEC_MT8188: - case MTK_VDEC_MT8195: - case MTK_VDEC_MT8196: + case 8188: + case 8195: + case 8196: cfg->max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2; break; default: @@ -886,6 +886,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { .get_cap_buffer =3D vdec_get_cap_buffer, .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, + .chip_name =3D 8183, }; =20 /* This platform data is used for one lat and one core architecture. */ @@ -906,6 +907,45 @@ const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pda= ta =3D { .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, }; =20 +#define MTK_STATELESS_DEC_DATA \ + .init_vdec_params =3D mtk_init_vdec_params, \ + .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, \ + .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, \ + .vdec_formats =3D mtk_video_formats, \ + .num_formats =3D &num_formats, \ + .default_out_fmt =3D &default_out_format, \ + .default_cap_fmt =3D &default_cap_format, \ + .uses_stateless_api =3D true, \ + .worker =3D mtk_vdec_worker, \ + .flush_decoder =3D mtk_vdec_flush_decoder, \ + .cap_to_disp =3D mtk_vdec_stateless_cap_to_disp, \ + .get_cap_buffer =3D vdec_get_cap_buffer, \ + .is_subdev_supported =3D true + +const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata =3D { + MTK_STATELESS_DEC_DATA, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_name =3D 8188, +}; + +const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata =3D { + MTK_STATELESS_DEC_DATA, + .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, + .chip_name =3D 8192, +}; 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Tue, 27 Jan 2026 10:43:06 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Tue, 27 Jan 2026 10:43:04 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Tue, 27 Jan 2026 10:43:03 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v7 03/10] media: mediatek: vcodec: add decoder compatible to support MT8189 Date: Tue, 27 Jan 2026 10:42:40 +0800 Message-ID: <20260127024248.18406-4-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260127024248.18406-1-kyrie.wu@mediatek.com> References: <20260127024248.18406-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" MT8189 is pure single core architecture. Add its compatible to initialize platform data. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../mediatek/vcodec/decoder/mtk_vcodec_dec.h | 1 + .../vcodec/decoder/mtk_vcodec_dec_drv.c | 4 ++++ .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 18 ++++++++++++++++++ 3 files changed, 23 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.= h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h index 80cb46f1cded..2bde871c0224 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec.h @@ -71,6 +71,7 @@ extern const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pd= ata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata; +extern const struct mtk_vcodec_dec_pdata mtk_vdec_8189_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata; extern const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c index c7af48f684c5..8f52e002a51e 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c @@ -555,6 +555,10 @@ static const struct of_device_id mtk_vcodec_match[] = =3D { .compatible =3D "mediatek,mt8196-vcodec-dec", .data =3D &mtk_vdec_8196_pdata, }, + { + .compatible =3D "mediatek,mt8189-vcodec-dec", + .data =3D &mtk_vdec_8189_pdata, + }, {}, }; =20 diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index 0745bc3ee490..aba28d276bdf 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -968,3 +968,21 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata = =3D { .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, .chip_name =3D 8186, }; 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charset="utf-8" This commit refactors the handling of decoder parameters for H264, H265, and VP9 codecs by introducing a new structure to standardize supported level and profile information. By leveraging this changes, chipset-specific conditional logic in the codec configuration functions is significantly reduced. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../vcodec/decoder/mtk_vcodec_dec_drv.h | 16 ++++ .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 93 ++++--------------- 2 files changed, 34 insertions(+), 75 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index bb293ada6fb2..f38b5dc4bb74 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -76,6 +76,16 @@ struct vdec_pic_info { unsigned int reserved; }; =20 +/** + * struct mtk_vcodec_dec_params - decoder supported parameters + * @level: decoder supported vcodec level + * @profile: decoder supported vcodec profile + */ +struct mtk_vcodec_dec_params { + s64 level; + s64 profile; +}; + /** * struct mtk_vcodec_dec_pdata - compatible data for each IC * @init_vdec_params: init vdec params @@ -96,6 +106,9 @@ struct vdec_pic_info { * @is_subdev_supported: whether support parent-node architecture(subdev) * @uses_stateless_api: whether the decoder uses the stateless API with re= quests * @chip_name: platforms configuration values + * @h264_params: H264 decoder default supported params + * @h265_params: H265 decoder default supported params + * @vp9_params: VP9 decoder default supported params */ struct mtk_vcodec_dec_pdata { void (*init_vdec_params)(struct mtk_vcodec_dec_ctx *ctx); @@ -118,6 +131,9 @@ struct mtk_vcodec_dec_pdata { bool is_subdev_supported; bool uses_stateless_api; unsigned int chip_name; + struct mtk_vcodec_dec_params h264_params; + struct mtk_vcodec_dec_params h265_params; + struct mtk_vcodec_dec_params vp9_params; }; =20 /** diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index aba28d276bdf..a1f419202a24 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -549,106 +549,49 @@ static const struct v4l2_ctrl_ops mtk_vcodec_dec_ctr= l_ops =3D { static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case 8192: - case 8188: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_2; - break; - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0; - break; - case 8183: - case 8186: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_2; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_H264_LEVEL_4_1; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h264_params.level; } =20 static void mtk_vcodec_dec_fill_h264_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case 8188: - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h264_params.profile; } =20 static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case 8188: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; - break; - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_4; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h265_params.level; } =20 static void mtk_vcodec_dec_fill_h265_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case 8188: - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->h265_params.profile; } =20 static void mtk_vcodec_dec_fill_vp9_level(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case 8192: - case 8188: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1; - break; - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2; - break; - case 8186: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->vp9_params.level; } =20 static void mtk_vcodec_dec_fill_vp9_profile(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { - switch (ctx->dev->chip_name) { - case 8188: - case 8195: - case 8196: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2; - break; - default: - cfg->max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1; - break; - } + struct mtk_vcodec_dec_dev *pdev =3D ctx->dev; + + cfg->max =3D pdev->vdec_pdata->vp9_params.profile; } =20 static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, --=20 2.45.2 From nobody Sat Feb 7 05:01:13 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 592792EC563; Tue, 27 Jan 2026 02:43:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 27 Jan 2026 10:43:08 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Tue, 27 Jan 2026 10:43:07 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Tue, 27 Jan 2026 10:43:06 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v7 05/10] media: mediatek: vcodec: Add Decoder profile & level Initialization Date: Tue, 27 Jan 2026 10:42:42 +0800 Message-ID: <20260127024248.18406-6-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260127024248.18406-1-kyrie.wu@mediatek.com> References: <20260127024248.18406-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" This commit initializes codec profile & level for VDEC. It sets default values for H264, H265, and VP9 codecs across multiple chipset configurations. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1279244671; Tue, 27 Jan 2026 10:43:09 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Tue, 27 Jan 2026 10:43:08 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Tue, 27 Jan 2026 10:43:07 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v7 06/10] media: mediatek: vcodec: Add VP9 Probability Size Configuration Date: Tue, 27 Jan 2026 10:42:43 +0800 Message-ID: <20260127024248.18406-7-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260127024248.18406-1-kyrie.wu@mediatek.com> References: <20260127024248.18406-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" This commit introduces support for configuring the VP9 decoder probability buffer size. It removes hard-coded values and ensures chipset-specific buffer sizes are handled dynamically, improving maintainability and alignment. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h | 2 ++ .../mediatek/vcodec/decoder/mtk_vcodec_dec_stateful.c | 1 + .../mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c | 10 ++++++++++ .../mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c | 4 ++-- 4 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.h b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h index f38b5dc4bb74..08cc65054de5 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.h @@ -80,10 +80,12 @@ struct vdec_pic_info { * struct mtk_vcodec_dec_params - decoder supported parameters * @level: decoder supported vcodec level * @profile: decoder supported vcodec profile + * @prob_size: vp9 decoder probability size */ struct mtk_vcodec_dec_params { s64 level; s64 profile; + size_t prob_size; }; =20 /** diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateful.c index a47906b9d717..99c252e0a2e1 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statefu= l.c @@ -630,5 +630,6 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + .prob_size =3D 2560, }, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec= _stateless.c index b571c4ed3f79..ca39ae3571a3 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_statele= ss.c @@ -10,6 +10,9 @@ #include "mtk_vcodec_dec_pm.h" #include "vdec_drv_if.h" =20 +#define VP9_PROB_BUF_SIZE 2560 +#define VP9_4K_PROB_BUF_SIZE 3840 + /** * struct mtk_stateless_control - CID control type * @cfg: control configuration @@ -841,6 +844,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_0, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + .prob_size =3D VP9_PROB_BUF_SIZE, }, }; =20 @@ -892,6 +896,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8188_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .prob_size =3D VP9_PROB_BUF_SIZE, }, }; =20 @@ -910,6 +915,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8192_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_1, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + .prob_size =3D VP9_PROB_BUF_SIZE, }, }; =20 @@ -928,6 +934,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8195_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .prob_size =3D VP9_PROB_BUF_SIZE, }, }; =20 @@ -946,6 +953,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8196_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .prob_size =3D VP9_4K_PROB_BUF_SIZE, }, }; =20 @@ -981,6 +989,7 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8186_pdata = =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_4_1, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_1, + .prob_size =3D VP9_PROB_BUF_SIZE, }, }; =20 @@ -1011,5 +1020,6 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8189_pdata= =3D { .vp9_params =3D { .level =3D V4L2_MPEG_VIDEO_VP9_LEVEL_5_2, .profile =3D V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .prob_size =3D VP9_4K_PROB_BUF_SIZE, }, }; diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_r= eq_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_= req_lat_if.c index 82e257bd059f..e8ba99d31e74 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c @@ -22,7 +22,6 @@ #define VP9_RESET_FRAME_CONTEXT_ALL 3 =20 #define VP9_TILE_BUF_SIZE 4096 -#define VP9_PROB_BUF_SIZE 2560 #define VP9_COUNTS_BUF_SIZE 16384 =20 #define HDR_FLAG(x) (!!((hdr)->flags & V4L2_VP9_FRAME_FLAG_##x)) @@ -546,6 +545,7 @@ static int vdec_vp9_slice_alloc_working_buffer(struct v= dec_vp9_slice_instance *i struct vdec_vp9_slice_vsi *vsi) { struct mtk_vcodec_dec_ctx *ctx =3D instance->ctx; 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Tue, 27 Jan 2026 10:43:11 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Tue, 27 Jan 2026 10:43:09 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Tue, 27 Jan 2026 10:43:08 +0800 From: Kyrie Wu To: Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , Hans Verkuil , Nicolas Dufresne , Nathan Hebert , Arnd Bergmann , Irui Wang , George Sun , , , , , CC: Neil Armstrong , Andrzej Pietrasiewicz , Yilong Zhou Subject: [PATCH v7 07/10] media: mediatek: vcodec: Fix vp9 4096x2176 fail for profile2 Date: Tue, 27 Jan 2026 10:42:44 +0800 Message-ID: <20260127024248.18406-8-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260127024248.18406-1-kyrie.wu@mediatek.com> References: <20260127024248.18406-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" The DRAM address of the VP9 decoder tile info buffers may require as much as 36bits for 4096x2176 resolution. Fold the 4 most significant bits into the lower (padding) four bits of address. Fixes: 5d418351ca8f1 ("media: mediatek: vcodec: support stateless VP9 decod= ing") Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nicolas Dufresne --- .../mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_if.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_r= eq_lat_if.c b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_= req_lat_if.c index e8ba99d31e74..a958e16eb380 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_vp9_req_lat_= if.c @@ -1133,9 +1133,17 @@ static int vdec_vp9_slice_setup_tile_buffer(struct v= dec_vp9_slice_instance *inst return -EINVAL; } tiles->size[i][j] =3D size; + /* + * If the system supports 64-bit DMA addresses, the upper 4 bits + * of the address are also encoded into the buffer entry. + * The buffer pointer (tb) is incremented after each entry is written. + */ if (tiles->mi_rows[i]) { *tb++ =3D (size << 3) + ((offset << 3) & 0x7f); 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charset="utf-8" change media register device node number to a correct value. The vfd minor is used to record the number of registered video device nodes. The mdev_dec.devnode minor counter is used to record the number of registered media device nodes. Fixes: 41f03c673cb7b ("media: mediatek: vcodec: replace pr_* with dev_* for= v4l2 debug message") Signed-off-by: Kyrie Wu Reviewed-by: Nicolas Dufresne Reviewed-by: AngeloGioacchino Del Regno --- .../platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_= drv.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c index 8f52e002a51e..d22ab42e22b6 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_drv.c @@ -495,7 +495,8 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) goto err_media_reg; } =20 - dev_dbg(&pdev->dev, "media registered as /dev/media%d", vfd_dec->minor); + dev_dbg(&pdev->dev, "media registered as /dev/media%d", + dev->mdev_dec.devnode->minor); } =20 mtk_vcodec_dbgfs_init(dev, false); --=20 2.45.2 From nobody Sat Feb 7 05:01:13 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F43D2DC32D; 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charset="utf-8" Add MT8189 encoder compatible string to distinguish former ICs MTK's. Compared with MT8196, the maximum resolution of MT8189 encoder is only 4K, and the fps is only 30, which cannot reach the highest parameter of MT8196: level6.2, 8K@60fps. Compared with MT8188, the level can only support 5.1, which is less than 5.2 of MT8188. But the maximum bitrate is 100Mbps, which is twice that of MT8188. And MT8189 could support NBM mode. Signed-off-by: Kyrie Wu Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/media/mediatek,vcodec-encoder.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encode= r.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.ya= ml index bb4dbf23ccc5..7f355470b63c 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt8173-vcodec-enc - mediatek,mt8183-vcodec-enc - mediatek,mt8188-vcodec-enc + - mediatek,mt8189-vcodec-enc - mediatek,mt8192-vcodec-enc - mediatek,mt8195-vcodec-enc - mediatek,mt8196-vcodec-enc @@ -100,6 +101,7 @@ allOf: enum: - mediatek,mt8183-vcodec-enc - mediatek,mt8188-vcodec-enc + - mediatek,mt8189-vcodec-enc - mediatek,mt8192-vcodec-enc - mediatek,mt8195-vcodec-enc =20 --=20 2.45.2 From nobody Sat Feb 7 05:01:13 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E905A2F1FEF; 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charset="utf-8" add MT8189 compatible data to initialize platform data for encoder. Signed-off-by: Kyrie Wu Reviewed-by: AngeloGioacchino Del Regno --- .../mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_= drv.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c index 86d0ab03f151..5e203caa47d4 100644 --- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_drv.c @@ -469,6 +469,19 @@ static const struct mtk_vcodec_enc_pdata mt8196_pdata = =3D { .set_dma_bit_mask =3D true, }; =20 +static const struct mtk_vcodec_enc_pdata mt8189_pdata =3D { + .venc_model_num =3D 8189, + .capture_formats =3D mtk_video_formats_capture_h264, + .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_h264), + .output_formats =3D mtk_video_formats_output, + .num_output_formats =3D ARRAY_SIZE(mtk_video_formats_output), + .min_bitrate =3D 64, + .max_bitrate =3D 100000000, + .core_id =3D VENC_SYS, + .uses_common_fw_iface =3D true, + .set_dma_bit_mask =3D true, +}; + static const struct of_device_id mtk_vcodec_enc_match[] =3D { {.compatible =3D "mediatek,mt8173-vcodec-enc", .data =3D &mt8173_avc_pdata}, @@ -479,6 +492,7 @@ static const struct of_device_id mtk_vcodec_enc_match[]= =3D { {.compatible =3D "mediatek,mt8192-vcodec-enc", .data =3D &mt8192_pdata}, {.compatible =3D "mediatek,mt8195-vcodec-enc", .data =3D &mt8195_pdata}, {.compatible =3D "mediatek,mt8196-vcodec-enc", .data =3D &mt8196_pdata}, + {.compatible =3D "mediatek,mt8189-vcodec-enc", .data =3D &mt8189_pdata}, {}, }; MODULE_DEVICE_TABLE(of, mtk_vcodec_enc_match); --=20 2.45.2