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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Russell King , linux-kernel@vger.kernel.org Subject: [PATCH net-next v4 4/4] net: dsa: yt921x: Add DCB/QoS support Date: Tue, 27 Jan 2026 10:08:01 +0800 Message-ID: <20260127020847.1482724-5-mmyangfl@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260127020847.1482724-1-mmyangfl@gmail.com> References: <20260127020847.1482724-1-mmyangfl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set up global DSCP/PCP priority mappings and add related DCB methods. Signed-off-by: David Yang --- drivers/net/dsa/Kconfig | 1 + drivers/net/dsa/yt921x.c | 249 ++++++++++++++++++++++++++++++++++++++- drivers/net/dsa/yt921x.h | 55 +++++++-- 3 files changed, 294 insertions(+), 11 deletions(-) diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig index 7eb301fd987d..24c37cbf70d7 100644 --- a/drivers/net/dsa/Kconfig +++ b/drivers/net/dsa/Kconfig @@ -158,6 +158,7 @@ config NET_DSA_VITESSE_VSC73XX_PLATFORM config NET_DSA_YT921X tristate "Motorcomm YT9215 ethernet switch chip support" select NET_DSA_TAG_YT921X + select NET_IEEE8021Q_HELPERS if DCB help This enables support for the Motorcomm YT9215 ethernet switch chip. diff --git a/drivers/net/dsa/yt921x.c b/drivers/net/dsa/yt921x.c index 9ac0e4e236c6..0383cc28ac67 100644 --- a/drivers/net/dsa/yt921x.c +++ b/drivers/net/dsa/yt921x.c @@ -8,6 +8,7 @@ * Copyright (c) 2025 David Yang */ =20 +#include #include #include #include @@ -18,8 +19,11 @@ #include #include #include +#include =20 #include +#include +#include =20 #include "yt921x.h" =20 @@ -1773,8 +1777,11 @@ yt921x_port_set_vlan_aware(struct yt921x_priv *priv,= int port, bool vlan_aware) { u32 ctrl; =20 + /* Abuse SVLAN for PCP parsing without polluting the FDB - it just works + * despite YT921X_VLAN_CTRL_SVLAN_EN never being set + */ if (!vlan_aware) - ctrl =3D 0; + ctrl =3D YT921X_PORT_IGR_TPIDn_STAG(0); else ctrl =3D YT921X_PORT_IGR_TPIDn_CTAG(0); return yt921x_reg_write(priv, YT921X_PORTn_IGR_TPID(port), ctrl); @@ -2396,6 +2403,122 @@ yt921x_dsa_port_stp_state_set(struct dsa_switch *ds= , int port, u8 state) port, res); } =20 +static int __maybe_unused +yt921x_dsa_port_get_default_prio(struct dsa_switch *ds, int port) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + u32 val; + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_reg_read(priv, YT921X_PORTn_QOS(port), &val); + mutex_unlock(&priv->reg_lock); + + if (res) + return res; + + return FIELD_GET(YT921X_PORT_QOS_PRIO_M, val); +} + +static int __maybe_unused +yt921x_dsa_port_set_default_prio(struct dsa_switch *ds, int port, u8 prio) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + u32 mask; + u32 ctrl; + int res; + + if (prio >=3D YT921X_PRIO_NUM) + return -EINVAL; + + mutex_lock(&priv->reg_lock); + mask =3D YT921X_PORT_QOS_PRIO_M | YT921X_PORT_QOS_PRIO_EN; + ctrl =3D YT921X_PORT_QOS_PRIO(prio) | YT921X_PORT_QOS_PRIO_EN; + res =3D yt921x_reg_update_bits(priv, YT921X_PORTn_QOS(port), mask, ctrl); + mutex_unlock(&priv->reg_lock); + + return res; +} + +static int __maybe_unused appprios_cmp(const void *a, const void *b) +{ + return ((const u8 *)b)[1] - ((const u8 *)a)[1]; +} + +static int __maybe_unused +yt921x_dsa_port_get_apptrust(struct dsa_switch *ds, int port, u8 *sel, + int *nselp) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + u8 appprios[2][2] =3D {}; + int nsel; + u32 val; + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_reg_read(priv, YT921X_PORTn_PRIO_ORD(port), &val); + mutex_unlock(&priv->reg_lock); + + if (res) + return res; + + appprios[0][0] =3D IEEE_8021QAZ_APP_SEL_DSCP; + appprios[0][1] =3D (val >> (3 * YT921X_APP_SEL_DSCP)) & 7; + appprios[1][0] =3D DCB_APP_SEL_PCP; + appprios[1][1] =3D (val >> (3 * YT921X_APP_SEL_CVLAN_PCP)) & 7; + sort(appprios, ARRAY_SIZE(appprios), sizeof(appprios[0]), appprios_cmp, + NULL); + + nsel =3D 0; + for (int i =3D 0; i < ARRAY_SIZE(appprios) && appprios[i][1]; i++) { + sel[nsel] =3D appprios[i][0]; + nsel++; + } + *nselp =3D nsel; + + return 0; +} + +static int __maybe_unused +yt921x_dsa_port_set_apptrust(struct dsa_switch *ds, int port, const u8 *se= l, + int nsel) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + struct device *dev =3D to_device(priv); + u32 ctrl; + int res; + + if (nsel > YT921X_APP_SEL_NUM) + return -EINVAL; + + ctrl =3D 0; + for (int i =3D 0; i < nsel; i++) { + switch (sel[i]) { + case IEEE_8021QAZ_APP_SEL_DSCP: + ctrl |=3D YT921X_PORT_PRIO_ORD_APPm(YT921X_APP_SEL_DSCP, + 7 - i); + break; + case DCB_APP_SEL_PCP: + ctrl |=3D YT921X_PORT_PRIO_ORD_APPm(YT921X_APP_SEL_CVLAN_PCP, + 7 - i); + ctrl |=3D YT921X_PORT_PRIO_ORD_APPm(YT921X_APP_SEL_SVLAN_PCP, + 7 - i); + break; + default: + dev_err(dev, + "Invalid apptrust selector (at %d-th). Supported: dscp, pcp\n", + i + 1); + return -EOPNOTSUPP; + } + } + + mutex_lock(&priv->reg_lock); + res =3D yt921x_reg_write(priv, YT921X_PORTn_PRIO_ORD(port), ctrl); + mutex_unlock(&priv->reg_lock); + + return res; +} + static int yt921x_port_down(struct yt921x_priv *priv, int port) { u32 mask; @@ -2721,6 +2844,13 @@ static int yt921x_port_setup(struct yt921x_priv *pri= v, int port) if (res) return res; =20 + /* Clear prio order (even if DCB is not enabled) to avoid unsolicited + * priorities + */ + res =3D yt921x_reg_write(priv, YT921X_PORTn_PRIO_ORD(port), 0); + if (res) + return res; + if (dsa_is_cpu_port(ds, port)) { /* Egress of CPU port is supposed to be completely controlled * via tagging, so set to oneway isolated (drop all packets @@ -2764,6 +2894,66 @@ static int yt921x_dsa_port_setup(struct dsa_switch *= ds, int port) return res; } =20 +/* Not "port" - DSCP mapping is global */ +static int __maybe_unused +yt921x_dsa_port_get_dscp_prio(struct dsa_switch *ds, int port, u8 dscp) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + u32 val; + int res; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_reg_read(priv, YT921X_IPM_DSCPn(dscp), &val); + mutex_unlock(&priv->reg_lock); + + if (res) + return res; + + return FIELD_GET(YT921X_IPM_PRIO_M, val); +} + +static int __maybe_unused +yt921x_dsa_port_del_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, u8= prio) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + u32 val; + int res; + + mutex_lock(&priv->reg_lock); + /* During a "dcb app replace" command, the new app table entry will be + * added first, then the old one will be deleted. But the hardware only + * supports one QoS class per DSCP value (duh), so if we blindly delete + * the app table entry for this DSCP value, we end up deleting the + * entry with the new priority. Avoid that by checking whether user + * space wants to delete the priority which is currently configured, or + * something else which is no longer current. + */ + res =3D yt921x_reg_read(priv, YT921X_IPM_DSCPn(dscp), &val); + if (!res && FIELD_GET(YT921X_IPM_PRIO_M, val) =3D=3D prio) + res =3D yt921x_reg_write(priv, YT921X_IPM_DSCPn(dscp), + YT921X_IPM_PRIO(IEEE8021Q_TT_BK)); + mutex_unlock(&priv->reg_lock); + + return res; +} + +static int __maybe_unused +yt921x_dsa_port_add_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, u8= prio) +{ + struct yt921x_priv *priv =3D to_yt921x_priv(ds); + int res; + + if (prio >=3D YT921X_PRIO_NUM) + return -EINVAL; + + mutex_lock(&priv->reg_lock); + res =3D yt921x_reg_write(priv, YT921X_IPM_DSCPn(dscp), + YT921X_IPM_PRIO(prio)); + mutex_unlock(&priv->reg_lock); + + return res; +} + static int yt921x_edata_wait(struct yt921x_priv *priv, u32 *valp) { u32 val =3D YT921X_EDATA_DATA_IDLE; @@ -2976,6 +3166,43 @@ static int yt921x_chip_setup_dsa(struct yt921x_priv = *priv) return 0; } =20 +static int __maybe_unused yt921x_chip_setup_qos(struct yt921x_priv *priv) +{ + u32 ctrl; + int res; + + /* 802.1Q QoS to internal priorities */ + for (u8 pcp =3D 0; pcp < 8; pcp++) + for (u8 dei =3D 0; dei < 2; dei++) { + ctrl =3D YT921X_IPM_PRIO(pcp); + if (dei) + ctrl |=3D YT921X_IPM_COLOR_RED; + + for (u8 svlan =3D 0; svlan < 2; svlan++) { + u32 reg =3D YT921X_IPM_PCPn(svlan, dei, pcp); + + res =3D yt921x_reg_write(priv, reg, ctrl); + if (res) + return res; + } + } + + /* DSCP to internal priorities */ + for (u8 dscp =3D 0; dscp < DSCP_MAX; dscp++) { + int prio =3D ietf_dscp_to_ieee8021q_tt(dscp); + + if (prio < 0) + return prio; + + res =3D yt921x_reg_write(priv, YT921X_IPM_DSCPn(dscp), + YT921X_IPM_PRIO(prio)); + if (res) + return res; + } + + return 0; +} + static int yt921x_chip_setup(struct yt921x_priv *priv) { u32 ctrl; @@ -2990,6 +3217,12 @@ static int yt921x_chip_setup(struct yt921x_priv *pri= v) if (res) return res; =20 +#if IS_ENABLED(CONFIG_DCB) + res =3D yt921x_chip_setup_qos(priv); + if (res) + return res; +#endif + /* Clear MIB */ ctrl =3D YT921X_MIB_CTRL_CLEAN | YT921X_MIB_CTRL_ALL_PORT; res =3D yt921x_reg_write(priv, YT921X_MIB_CTRL, ctrl); @@ -3105,10 +3338,23 @@ static const struct dsa_switch_ops yt921x_dsa_switc= h_ops =3D { .port_mst_state_set =3D yt921x_dsa_port_mst_state_set, .vlan_msti_set =3D yt921x_dsa_vlan_msti_set, .port_stp_state_set =3D yt921x_dsa_port_stp_state_set, +#if IS_ENABLED(CONFIG_DCB) + /* dcb */ + .port_get_default_prio =3D yt921x_dsa_port_get_default_prio, + .port_set_default_prio =3D yt921x_dsa_port_set_default_prio, + .port_get_apptrust =3D yt921x_dsa_port_get_apptrust, + .port_set_apptrust =3D yt921x_dsa_port_set_apptrust, +#endif /* port */ .get_tag_protocol =3D yt921x_dsa_get_tag_protocol, .phylink_get_caps =3D yt921x_dsa_phylink_get_caps, .port_setup =3D yt921x_dsa_port_setup, +#if IS_ENABLED(CONFIG_DCB) + /* dscp */ + .port_get_dscp_prio =3D yt921x_dsa_port_get_dscp_prio, + .port_del_dscp_prio =3D yt921x_dsa_port_del_dscp_prio, + .port_add_dscp_prio =3D yt921x_dsa_port_add_dscp_prio, +#endif /* chip */ .setup =3D yt921x_dsa_setup, }; @@ -3175,6 +3421,7 @@ static int yt921x_mdio_probe(struct mdio_device *mdio= dev) ds =3D &priv->ds; ds->dev =3D dev; ds->assisted_learning_on_cpu_port =3D true; + ds->dscp_prio_mapping_is_global =3D true; ds->priv =3D priv; ds->ops =3D &yt921x_dsa_switch_ops; ds->ageing_time_min =3D 1 * 5000; diff --git a/drivers/net/dsa/yt921x.h b/drivers/net/dsa/yt921x.h index bacd4ccaa8e5..3f129b8d403f 100644 --- a/drivers/net/dsa/yt921x.h +++ b/drivers/net/dsa/yt921x.h @@ -269,6 +269,38 @@ #define YT921X_TPID_EGRn(x) (0x100300 + 4 * (x)) /* [0, 3] */ #define YT921X_TPID_EGR_TPID_M GENMASK(15, 0) =20 +#define YT921X_IPM_DSCPn(n) (0x180000 + 4 * (n)) /* Internal Priority Map= */ +#define YT921X_IPM_PCPn(map, dei, pcp) (0x180100 + 4 * (16 * (map) + 8 * (= dei) + (pcp))) +#define YT921X_IPM_PRIO_M GENMASK(4, 2) +#define YT921X_IPM_PRIO(x) FIELD_PREP(YT921X_IPM_PRIO_M, (x)) +#define YT921X_IPM_COLOR_M GENMASK(1, 0) +#define YT921X_IPM_COLOR(x) FIELD_PREP(YT921X_IPM_COLOR_M, (x)) +#define YT921X_IPM_COLOR_GREEN YT921X_IPM_COLOR(0) +#define YT921X_IPM_COLOR_YELLOW YT921X_IPM_COLOR(1) +#define YT921X_IPM_COLOR_RED YT921X_IPM_COLOR(2) +#define YT921X_PORTn_QOS(port) (0x180180 + 4 * (port)) +#define YT921X_PORT_QOS_CVLAN_PRIO_MAP_ID BIT(5) +#define YT921X_PORT_QOS_SVLAN_PRIO_MAP_ID BIT(4) +#define YT921X_PORT_QOS_PRIO_M GENMASK(3, 1) +#define YT921X_PORT_QOS_PRIO(x) FIELD_PREP(YT921X_PORT_QOS_PRIO_M, (x)) +#define YT921X_PORT_QOS_PRIO_EN BIT(0) +#define YT921X_PORTn_PRIO_ORD(port) (0x180200 + 4 * (port)) +#define YT921X_PORT_PRIO_ORD_APPm_M(m) GENMASK(3 * (m) + 2, 3 * (m)) +#define YT921X_PORT_PRIO_ORD_APPm(m, x) ((x) << (3 * (m))) /* 0: disabl= ed, except PORT_QOS_PRIO */ + +enum yt921x_app_selector { + YT921X_APP_SEL_MAC_SA, + YT921X_APP_SEL_MAC_DA, + YT921X_APP_SEL_VID, + YT921X_APP_SEL_ACL, + YT921X_APP_SEL_DSCP, + YT921X_APP_SEL_CVLAN_PCP, + YT921X_APP_SEL_SVLAN_PCP, + /* The physical port, i.e. YT921X_PORT_QOS_PRIO */ + YT921X_APP_SEL_PORT, + YT921X_APP_SEL_NUM +}; + #define YT921X_VLAN_IGR_FILTER 0x180280 #define YT921X_VLAN_IGR_FILTER_PORTn_BYPASS_IGMP(port) BIT((port) + 11) #define YT921X_VLAN_IGR_FILTER_PORTn(port) BIT(port) @@ -337,7 +369,7 @@ #define YT921X_FDB_OUT0 0x1804b0 #define YT921X_FDB_IO0_ADDR_HI4_M GENMASK(31, 0) #define YT921X_FDB_OUT1 0x1804b4 -#define YT921X_FDB_IO1_EGR_INT_PRI_EN BIT(31) +#define YT921X_FDB_IO1_EGR_PRIO_EN BIT(31) #define YT921X_FDB_IO1_STATUS_M GENMASK(30, 28) #define YT921X_FDB_IO1_STATUS(x) FIELD_PREP(YT921X_FDB_IO1_STATUS_M, (= x)) #define YT921X_FDB_IO1_STATUS_INVALID YT921X_FDB_IO1_STATUS(0) @@ -356,9 +388,9 @@ #define YT921X_FDB_IO2_EGR_PORTS(x) FIELD_PREP(YT921X_FDB_IO2_EGR_PORT= S_M, (x)) #define YT921X_FDB_IO2_EGR_DROP BIT(17) #define YT921X_FDB_IO2_COPY_TO_CPU BIT(16) -#define YT921X_FDB_IO2_IGR_INT_PRI_EN BIT(15) -#define YT921X_FDB_IO2_INT_PRI_M GENMASK(14, 12) -#define YT921X_FDB_IO2_INT_PRI(x) FIELD_PREP(YT921X_FDB_IO2_INT_PRI_M,= (x)) +#define YT921X_FDB_IO2_IGR_PRIO_EN BIT(15) +#define YT921X_FDB_IO2_PRIO_M GENMASK(14, 12) +#define YT921X_FDB_IO2_PRIO(x) FIELD_PREP(YT921X_FDB_IO2_PRIO_M, (x)) #define YT921X_FDB_IO2_NEW_VID_M GENMASK(11, 0) #define YT921X_FDB_IO2_NEW_VID(x) FIELD_PREP(YT921X_FDB_IO2_NEW_VID_M,= (x)) #define YT921X_FILTER_UNK_UCAST 0x180508 @@ -406,8 +438,9 @@ #define YT921X_VLAN_CTRL_FID_M GENMASK_ULL(34, 23) #define YT921X_VLAN_CTRL_FID(x) FIELD_PREP(YT921X_VLAN_CTRL_FID_M, (x)) #define YT921X_VLAN_CTRL_LEARN_DIS BIT_ULL(22) -#define YT921X_VLAN_CTRL_INT_PRI_EN BIT_ULL(21) -#define YT921X_VLAN_CTRL_INT_PRI_M GENMASK_ULL(20, 18) +#define YT921X_VLAN_CTRL_PRIO_EN BIT_ULL(21) +#define YT921X_VLAN_CTRL_PRIO_M GENMASK_ULL(20, 18) +#define YT921X_VLAN_CTRL_PRIO(x) FIELD_PREP(YT921X_VLAN_CTRL_PRIO_M, (= x)) #define YT921X_VLAN_CTRL_PORTS_M GENMASK_ULL(17, 7) #define YT921X_VLAN_CTRL_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRL_PORTS_M,= (x)) #define YT921X_VLAN_CTRL_PORTn(port) BIT_ULL((port) + 7) @@ -433,14 +466,14 @@ #define YT921X_LAG_HASH_SRC_PORT BIT(0) =20 #define YT921X_PORTn_VLAN_CTRL(port) (0x230010 + 4 * (port)) -#define YT921X_PORT_VLAN_CTRL_SVLAN_PRI_EN BIT(31) -#define YT921X_PORT_VLAN_CTRL_CVLAN_PRI_EN BIT(30) +#define YT921X_PORT_VLAN_CTRL_SVLAN_PRIO_EN BIT(31) +#define YT921X_PORT_VLAN_CTRL_CVLAN_PRIO_EN BIT(30) #define YT921X_PORT_VLAN_CTRL_SVID_M GENMASK(29, 18) #define YT921X_PORT_VLAN_CTRL_SVID(x) FIELD_PREP(YT921X_PORT_VLAN_CTRL= _SVID_M, (x)) #define YT921X_PORT_VLAN_CTRL_CVID_M GENMASK(17, 6) #define YT921X_PORT_VLAN_CTRL_CVID(x) FIELD_PREP(YT921X_PORT_VLAN_CTRL= _CVID_M, (x)) -#define YT921X_PORT_VLAN_CTRL_SVLAN_PRI_M GENMASK(5, 3) -#define YT921X_PORT_VLAN_CTRL_CVLAN_PRI_M GENMASK(2, 0) +#define YT921X_PORT_VLAN_CTRL_SVLAN_PRIO_M GENMASK(5, 3) +#define YT921X_PORT_VLAN_CTRL_CVLAN_PRIO_M GENMASK(2, 0) #define YT921X_PORTn_VLAN_CTRL1(port) (0x230080 + 4 * (port)) #define YT921X_PORT_VLAN_CTRL1_VLAN_RANGE_EN BIT(8) #define YT921X_PORT_VLAN_CTRL1_VLAN_RANGE_PROFILE_ID_M GENMASK(7, 4) @@ -478,6 +511,8 @@ enum yt921x_fdb_entry_status { #define YT921X_LAG_NUM 2 #define YT921X_LAG_PORT_NUM 4 =20 +#define YT921X_PRIO_NUM 8 + #define YT9215_MAJOR 0x9002 #define YT9218_MAJOR 0x9001 =20 --=20 2.51.0