From nobody Tue Feb 10 05:09:47 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A72ED35E533 for ; Tue, 27 Jan 2026 14:41:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769524863; cv=none; b=D+/7ICjg7ZJ5QTMy9sBeG4ClcoJdtcshnYT0KiHYkvWzBXi2NT42qqObsnQ0PubCxjmye2n3ch5u3n2AXPi4PIyteZMS7tOZNTb9EGiRsk55Rbz6VislWkIZqgpL3KbroGP6OtyYzFvs3jCJTm/MDvwB3lO9Eik1mhhAL3B81tM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769524863; c=relaxed/simple; bh=+VsWsEg0rEmpODVt6AZotBpo6jkuzOnObDO7E1FP1PU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L1PT8OZScTv+qBOC1RNWyGdKt3eq4cLKGjXtud/H3O+7eAn5H4pDVcbjzo4ZqjvETvOIKhEOtYsq7Ayp9Q5FRID1DO2IOh+fjrQXDL0HTr7T3xmz6cav2RTndT7JwLVcvBcNX1E9z+z8BorDuyrT2mPRT3L9TO84Li8opdhuMCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from ptz.office.stw.pengutronix.de ([2a0a:edc0:0:900:1d::77] helo=peter.mobile.pengutronix.de) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1vkkFW-0007YT-TM; Tue, 27 Jan 2026 15:40:59 +0100 From: =?utf-8?q?Sven_P=C3=BCschel?= Date: Tue, 27 Jan 2026 15:39:36 +0100 Subject: [PATCH v3 27/27] arm64: dts: rockchip: add rga3 dt nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260127-spu-rga3-v3-27-77b273067beb@pengutronix.de> References: <20260127-spu-rga3-v3-0-77b273067beb@pengutronix.de> In-Reply-To: <20260127-spu-rga3-v3-0-77b273067beb@pengutronix.de> To: Jacob Chen , Ezequiel Garcia , Mauro Carvalho Chehab , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de, =?utf-8?q?Sven_P=C3=BCschel?= X-Mailer: b4 0.14.3 X-SA-Exim-Connect-IP: 2a0a:edc0:0:900:1d::77 X-SA-Exim-Mail-From: s.pueschel@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Add devicetree nodes for the RGA3 (Raster Graphics Acceleration 3) peripheral in the RK3588. The existing rga node refers to the RGA2 peripheral. The RK3588 contains one RGA2 core and two RGA3 cores. Both feature a similar functionality of scaling, cropping and rotating of up to two input images into one output image. Key differences of the RGA3 are: - supports 10bit YUV output formats - supports 8x8 tiles and FBCD as inputs and outputs - supports BT2020 color space conversion - max output resolution of (8192-64)x(8192-64) - MMU can map up to 32G DDR RAM - fully planar formats (3 planes) are not supported - max scale up/down factor of 8 (RGA2 allows up to 16) Signed-off-by: Sven P=C3=BCschel --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 44 +++++++++++++++++++++++= ++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk3588-base.dtsi index 2a79217930206..d1d44cf948e92 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1273,6 +1273,50 @@ rga: rga@fdb80000 { power-domains =3D <&power RK3588_PD_VDPU>; }; =20 + rga3_core0: rga@fdb60000 { + compatible =3D "rockchip,rk3588-rga3"; + reg =3D <0x0 0xfdb60000 0x0 0x200>; + interrupts =3D ; + clocks =3D <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE= >; + clock-names =3D "aclk", "hclk", "sclk"; + resets =3D <&cru SRST_RGA3_0_CORE>, <&cru SRST_A_RGA3_0>, <&cru SRST_H_R= GA3_0>; + reset-names =3D "core", "axi", "ahb"; + power-domains =3D <&power RK3588_PD_RGA30>; + iommus =3D <&rga3_0_mmu>; + }; + + rga3_0_mmu: iommu@fdb60f00 { + compatible =3D "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0xfdb60f00 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; + clock-names =3D "aclk", "iface"; + #iommu-cells =3D <0>; + power-domains =3D <&power RK3588_PD_RGA30>; + }; + + rga3_core1: rga@fdb70000 { + compatible =3D "rockchip,rk3588-rga3"; + reg =3D <0x0 0xfdb70000 0x0 0x200>; + interrupts =3D ; + clocks =3D <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>, <&cru CLK_RGA3_1_CORE= >; + clock-names =3D "aclk", "hclk", "sclk"; + resets =3D <&cru SRST_RGA3_1_CORE>, <&cru SRST_A_RGA3_1>, <&cru SRST_H_R= GA3_1>; + reset-names =3D "core", "axi", "ahb"; + power-domains =3D <&power RK3588_PD_RGA31>; + iommus =3D <&rga3_1_mmu>; + }; + + rga3_1_mmu: iommu@fdb70f00 { + compatible =3D "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg =3D <0x0 0xfdb70f00 0x0 0x100>; + interrupts =3D ; + clocks =3D <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; + clock-names =3D "aclk", "iface"; + #iommu-cells =3D <0>; + power-domains =3D <&power RK3588_PD_RGA31>; + }; + vepu121_0: video-codec@fdba0000 { compatible =3D "rockchip,rk3588-vepu121"; reg =3D <0x0 0xfdba0000 0x0 0x800>; --=20 2.52.0