From nobody Mon Feb 9 17:08:16 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3C8034C808 for ; Tue, 27 Jan 2026 12:12:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769515922; cv=none; b=d5nfFWNd626FiNbF9G9SQSLVot4/gcOuqPYH7wwuBHU3nAfTswgvKfah7agqHXGIsmQznLLTJ3/2M0hVBvASo+NUlNS8W8VVTmf2GnuYjedtPIcVko5KFSon+qQx6kFut0VcFVhEUHxQinBKxYTgcX8eIgXZcFJJBNkw6T1fdnM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769515922; c=relaxed/simple; bh=TeDy3t3Fs7sFv6et8Ck2qBnwLTCzre+JdzVVG14n6ew=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=WiT/tsGycYtHIedtIuAadctGsSVn2QHT/Y2Hy9LY65b7EzenfRuuIEckftImD6EIAsnmqEwuxKuqEDvrVktnLe9cH2tXOfFYX9jKZIwkn6vgacSR74H+vWnIS8mHxfZbHjYEYo11iMnOdT11t14tBxmndQNwCiA9XsV36QoYnCs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=NnoQkF2r; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ioW6rPs9; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="NnoQkF2r"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ioW6rPs9" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60RAAffr495963 for ; Tue, 27 Jan 2026 12:12:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=Ds2ZJGE2krsn4P3tEHEukV hMuBmMD5Z71E4XCCNGtXw=; b=NnoQkF2rmO4tVZEjiDNcK1ybXCDrgwGdusJNVW lBKCM+RTyjlJQNHAUzhIOY2COeOx/nNrcyJV+/zhVxPL6Y5BzRUsje0hVzQfzDhy rNwhVjlCjA3kkrkxKqOKiWjHmOkNHlEykoNE8ZotZMCE+6wZv3TgvYzD6ymHU0uI 5xtmQncwi0xJCyjP3Z84yDNXxswAVSuD6ar2X5Cy8WA+6vQK+oLWNVhRjHSRpr7G V+uppQdq0D3MP0DH2sWU3Mfj6ryj1wu8EojE+TPS9OP7ZP1inENOM3NFWbKX30k7 xdFIgpc4uSDX7u6db3GVdlVfHFdesB/J6bwpD6/5IlJtzBIA== Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bxf3bjp3a-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 27 Jan 2026 12:11:59 +0000 (GMT) Received: by mail-pj1-f71.google.com with SMTP id 98e67ed59e1d1-352e1a8603bso5773713a91.1 for ; Tue, 27 Jan 2026 04:11:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1769515919; x=1770120719; darn=vger.kernel.org; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:from:to:cc:subject:date:message-id:reply-to; bh=Ds2ZJGE2krsn4P3tEHEukVhMuBmMD5Z71E4XCCNGtXw=; b=ioW6rPs9d2/UgB/N2H+A0ZdJeInnwF5kNi5kvHTbrE+Esz6qpVjQ/xMvzAPITJrdH6 bQKhnE1TnXV975+sDm7nxfKV2OqAUkaZJ4zafEXzrasR/t7DSgWVNikbDL5GHbELI6IC YvsYq8cwgIBYzub6C5mFufSHxzCIh3QikrqerU71d6zSfmV91zqCoHQMalcxtcwMadZ3 EgdpgkfIr1K74KEdCUAtpHxN6Y3tiAwSPs8Ejdtu+7dCv4CDgN0w7sB/Hhq348GKb63u LTsqb1+UJrs4zXeqpYXtr+YVOAl+28WkgQQwV7yd/K8pzrWg14hxCQkeAyGDDmGurD0n Aorw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769515919; x=1770120719; h=cc:to:message-id:content-transfer-encoding:mime-version:subject :date:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=Ds2ZJGE2krsn4P3tEHEukVhMuBmMD5Z71E4XCCNGtXw=; b=uxTO8Rgud/wrXpAgKZmhVHzS+OulCExVb3Ym4rTnQT2l4xypJAlSy6Jr26EAJMXEyL M/Y2F8ryXX9cKYFoLurwOn51eM61WnUECEzoeSWUvea5spM8Oo3iOhEOW5cCOl6GtTq/ SwbrzG/GJ/mRv3cTmHQF6rkhZD5FWuf1vaQ1qMyePhlGqJAVvGg6taXSGgL7QJrOr8yN 5U40vkT22Ao64FkKRydQfEzUVMTUlzY5pKFs/2dG+9mVvZfuC6kV6JE7FyXbt1KnqxSR gH2vY9G0zwO5MgI2exP1cDoOak/72cLNmBZ3bi9bIp25U4EAMHi+Y2DIj8Y/rvuL08Xj ApKw== X-Forwarded-Encrypted: i=1; AJvYcCWpvqiSwL/qurIKzXzd7ZV/qgc8AyxZHi6hYWZTDNYbJWdsUG090JUGKaOTypJgwIiAerk5IrfDLr5KXWo=@vger.kernel.org X-Gm-Message-State: AOJu0Ywk+2YZJuTaJdKTOViZ5Qyv5gc/xQCE3GNlYDFFrIxyjpbtFX01 gShs8rR8yKwOsL/ZrJ6t1v2vDCqruXyR0dDkCLCOfO4afwSnaSbPMacuXEMyK+zOP3I7T4XPSvx JeqIOYvLdVO464xJMVfASItQwmnt9iWr7otaB4/8XCMYBgO0B97PVG+CJPn9XIOQdT3g= X-Gm-Gg: AZuq6aJwehJNZobgzBBrZPl0rl2kB7ymenSOu+0t3ZujDoUwztJEb8EQmSrF0Qs+cn2 RQpg8Crj8vyB8x1u8YIIRFnMRR4JeEkhk1lliM3enqWvp53XzzV3DFWVTI7RvmxtEt/42MKiZZ7 6VHgsv3J7MHIQVvQG6AoWrYO0wONqRxUh4UNGhU2uvSzDUU8Y6d9aXeHy3q+giI7nqcXgfSfnvv MaHBpm1wclZHVVyAaklME8pRJJCxwBEJa5B57secAfvFBpGlx6fAYqywIBN2bg5Kc2Z10YTPeeb maj2sVri1bDDlqZod3kw7FrHCYhBEr4vReAmvKjIlj1/ODrE2x0vKErwZE77/O5M8AL5ZA4xbRd M3J30Qh2Db4wHBdsO/Gb5mT1LNvmc0gA4DcWnXOwC X-Received: by 2002:a17:90b:28ce:b0:353:3977:a082 with SMTP id 98e67ed59e1d1-353fecc6684mr1373171a91.1.1769515919137; Tue, 27 Jan 2026 04:11:59 -0800 (PST) X-Received: by 2002:a17:90b:28ce:b0:353:3977:a082 with SMTP id 98e67ed59e1d1-353fecc6684mr1373156a91.1.1769515918627; Tue, 27 Jan 2026 04:11:58 -0800 (PST) Received: from hu-guptap-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-353f6159ad6sm2489474a91.14.2026.01.27.04.11.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jan 2026 04:11:58 -0800 (PST) From: Prakash Gupta Date: Tue, 27 Jan 2026 17:41:45 +0530 Subject: [PATCH] iommu/arm-smmu: Use pm_runtime in fault handlers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260127-smmu-rpm-v1-1-2ef2f4c85305@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAICreGkC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1NDIwML3eLc3FLdooJcXYukFDPzlCRL45TkRCWg8oKi1LTMCrBR0bG1tQB 3HEI/WgAAAA== X-Change-ID: 20251208-smmu-rpm-8bd67db93dca To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Clark , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Akhil P Oommen , Pratyush Brahma , Prakash Gupta X-Mailer: b4 0.15-dev-47773 X-Proofpoint-ORIG-GUID: XXYOdSWvdkAA7gkFQY0II_YtLfMriX6b X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI3MDA5OSBTYWx0ZWRfXwo63vRIWGOn6 DH0dcJnX5dZ6K0P2VZ0/T7UefquA74p2Em+oSXs6ugjvkWWt2kJ1WlTtIqaiz+2jSda/bfS54V2 tJycjKOXMoGPbf+dnRSb0x8BbmoCXuAtpsqFGZbrml4Dln5sp9c8Yx7o/1OGtHoOqA0/ruovjs1 QAoPSXqtpHMdu6Z5yXd2gMk1TH3nYIceAShfMtk16XH7EIDVFXdxAv6T5SOSaKcsz48DkLF5VJE KOJngIMKuSm8k6stxnRilz0D5dCg/uZARfpL0rAeBo6Y4zvVPxOKNanEh3J1yGZSK1hYDvVUhIH uGjk+sCevF4S+B4T7JC+auLUocs9VzHGXlAkfQElX4ShpUZkKrrXEXCaB+kUdifvhUTEmK1Ip4C yHF4linnqqLHZVBjQjqt0LeWYpUktM8zDLDYf4iNhvKyyEMZjcNxonXhhl6I0JeVeaBddY8BN5w Qi/oecLOYmP08A+iQyg== X-Proofpoint-GUID: XXYOdSWvdkAA7gkFQY0II_YtLfMriX6b X-Authority-Analysis: v=2.4 cv=AOFXvqQI c=1 sm=1 tr=0 ts=6978ab8f cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=-SalRf7IlQZ7Iv0L3QwA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-27_02,2026-01-27_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 suspectscore=0 phishscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 spamscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601270099 Commit d4a44f0750bb ("iommu/arm-smmu: Invoke pm_runtime across the driver") enabled pm_runtime for the arm-smmu device. On systems where the SMMU sits in a power domain, all register accesses must be done while the device is runtime-resumed to avoid unclocked register reads and potential NoC errors. So far, this has not been an issue for most SMMU clients because stall-on-fault is enabled by default. While a translation fault is being handled, the SMMU stalls further translations for that context bank, so the fault handler would not race with a powered-down SMMU. Adreno SMMU now disables stall-on-fault in the presence of fault storms to avoid saturating SMMU resources and hanging the GMU. With stall-on-fault disabled, the SMMU can generate faults while its power domain may no longer be enabled, which makes unclocked accesses to fault-status registers in the SMMU fault handlers possible. Guard the context and global fault handlers with arm_smmu_rpm_get() / arm_smmu_rpm_put() so that all SMMU fault register accesses are done with the SMMU powered. Fixes: b13044092c1e ("drm/msm: Temporarily disable stall-on-fault after a p= age fault") Co-developed-by: Pratyush Brahma Signed-off-by: Pratyush Brahma Signed-off-by: Prakash Gupta Acked-by: Akhil P Oommen --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 5 ++- drivers/iommu/arm/arm-smmu/arm-smmu.c | 53 ++++++++++++++++++++++----= ---- 2 files changed, 43 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm= /arm-smmu/arm-smmu-qcom.c index 573085349df3..2d03df72612d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -317,6 +317,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smm= u_domain *smmu_domain, struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct qcom_smmu *qsmmu =3D to_qcom_smmu(smmu); const struct of_device_id *client_match; + const struct arm_smmu_impl *impl =3D qsmmu->data->impl; int cbndx =3D smmu_domain->cfg.cbndx; struct adreno_smmu_priv *priv; =20 @@ -350,10 +351,12 @@ static int qcom_adreno_smmu_init_context(struct arm_s= mmu_domain *smmu_domain, priv->get_ttbr1_cfg =3D qcom_adreno_smmu_get_ttbr1_cfg; priv->set_ttbr0_cfg =3D qcom_adreno_smmu_set_ttbr0_cfg; priv->get_fault_info =3D qcom_adreno_smmu_get_fault_info; - priv->set_stall =3D qcom_adreno_smmu_set_stall; priv->set_prr_bit =3D NULL; priv->set_prr_addr =3D NULL; =20 + if (impl->context_fault_needs_threaded_irq) + priv->set_stall =3D qcom_adreno_smmu_set_stall; + if (of_device_is_compatible(np, "qcom,smmu-500") && !of_device_is_compatible(np, "qcom,sm8250-smmu-500") && of_device_is_compatible(np, "qcom,adreno-smmu")) { diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-= smmu/arm-smmu.c index 5e690cf85ec9..183f12e45b02 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -462,10 +462,23 @@ static irqreturn_t arm_smmu_context_fault(int irq, vo= id *dev) int idx =3D smmu_domain->cfg.cbndx; int ret; =20 + if (smmu->impl && smmu->impl->context_fault_needs_threaded_irq) { + ret =3D arm_smmu_rpm_get(smmu); + if (ret < 0) + return IRQ_NONE; + } + + if (smmu->impl && smmu->impl->context_fault) { + ret =3D smmu->impl->context_fault(irq, dev); + goto out_power_off; + } + arm_smmu_read_context_fault_info(smmu, idx, &cfi); =20 - if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT)) - return IRQ_NONE; + if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT)) { + ret =3D IRQ_NONE; + goto out_power_off; + } =20 ret =3D report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova, cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_REA= D); @@ -480,7 +493,14 @@ static irqreturn_t arm_smmu_context_fault(int irq, voi= d *dev) ret =3D=3D -EAGAIN ? 0 : ARM_SMMU_RESUME_TERMINATE); } =20 - return IRQ_HANDLED; + ret =3D IRQ_HANDLED; + +out_power_off: + + if (smmu->impl && smmu->impl->context_fault_needs_threaded_irq) + arm_smmu_rpm_put(smmu); + + return ret; } =20 static irqreturn_t arm_smmu_global_fault(int irq, void *dev) @@ -489,14 +509,21 @@ static irqreturn_t arm_smmu_global_fault(int irq, voi= d *dev) struct arm_smmu_device *smmu =3D dev; static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); + int ret; + + ret =3D arm_smmu_rpm_get(smmu); + if (ret < 0) + return IRQ_NONE; =20 gfsr =3D arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); gfsynr0 =3D arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR0); gfsynr1 =3D arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR1); gfsynr2 =3D arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR2); =20 - if (!gfsr) - return IRQ_NONE; + if (!gfsr) { + ret =3D IRQ_NONE; + goto out_power_off; + } =20 if (__ratelimit(&rs)) { if (IS_ENABLED(CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT) && @@ -513,7 +540,11 @@ static irqreturn_t arm_smmu_global_fault(int irq, void= *dev) } =20 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, gfsr); - return IRQ_HANDLED; + ret =3D IRQ_HANDLED; + +out_power_off: + arm_smmu_rpm_put(smmu); + return ret; } =20 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, @@ -683,7 +714,6 @@ static int arm_smmu_init_domain_context(struct arm_smmu= _domain *smmu_domain, enum io_pgtable_fmt fmt; struct iommu_domain *domain =3D &smmu_domain->domain; struct arm_smmu_cfg *cfg =3D &smmu_domain->cfg; - irqreturn_t (*context_fault)(int irq, void *dev); =20 mutex_lock(&smmu_domain->init_mutex); if (smmu_domain->smmu) @@ -850,19 +880,14 @@ static int arm_smmu_init_domain_context(struct arm_sm= mu_domain *smmu_domain, */ irq =3D smmu->irqs[cfg->irptndx]; =20 - if (smmu->impl && smmu->impl->context_fault) - context_fault =3D smmu->impl->context_fault; - else - context_fault =3D arm_smmu_context_fault; - if (smmu->impl && smmu->impl->context_fault_needs_threaded_irq) ret =3D devm_request_threaded_irq(smmu->dev, irq, NULL, - context_fault, + arm_smmu_context_fault, IRQF_ONESHOT | IRQF_SHARED, "arm-smmu-context-fault", smmu_domain); else - ret =3D devm_request_irq(smmu->dev, irq, context_fault, IRQF_SHARED, + ret =3D devm_request_irq(smmu->dev, irq, arm_smmu_context_fault, IRQF_SH= ARED, "arm-smmu-context-fault", smmu_domain); =20 if (ret < 0) { --- base-commit: fcb70a56f4d81450114034b2c61f48ce7444a0e2 change-id: 20251208-smmu-rpm-8bd67db93dca Best regards, -- =20 Prakash Gupta