From nobody Mon Feb 9 05:29:20 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41FA5301717 for ; Tue, 27 Jan 2026 03:22:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769484161; cv=none; b=e8r1Rka1ZsAh9Nq2vUMarrT3AZO4Eonnd4lmFWM/9T55rxburPOg7f8LCu6ko0hLEr+udIymZQGI80j4WDYuj+iZgVFXpQpcXYwNIfV9pHriAC0Lx6UL21USeuqJPR8yGtx+XzFU8aIBqMVtv8ru4JifpkBsi70VPmfEeqbmFLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769484161; c=relaxed/simple; bh=PGyU7zC1OgweTH7uihsfCjypZ9CAWazTXAAr3xoSfIM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HRXE4ZUzL7d9QR1Z88mNLhAX3HHIQQNyz7DMHCbZ/I+xiGbDelEJewp0NE4S/3vILI23jje3ezB2Z38nWuRQ4uFpfK8UZ7seleDqSKkVDABVfeEbgGhLY2mkOOx/b1Q1NqG7drWXdG/qJKtkn7XGxt7KAuAmleDeaC+GLvqsspM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=IEfLoWp7; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=jMhJBWSd; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="IEfLoWp7"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="jMhJBWSd" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60QKgClZ2880085 for ; Tue, 27 Jan 2026 03:22:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= SRWtTSxZKt9shz1rrr3v/9A8UR0BGn1xkHJq01jFs8o=; b=IEfLoWp7HbnQ7ce+ xVoxqzxmVyfb5yK4r2kavQBfvE1H/Rmap3ZpJaN8VS/8JtQ7ViAMpvoOmcGwHumy 65Y83DnQLm/93R72MeeyojWvhmXrMC5Hs8+YjlpNLx8ga5I/Ilb4skAuTZUp54F8 PWTCBBU/lPqobpmhZ4gRnpHs9fUqojvpI7yBk0cST618p+gJCeuLLqxYQPil86ud 4SlDEa37PErp+kUaotMIFTN1BuLwoaShu0gPZvJ5WoILsKwW7mrSjSjmWDDNNS69 Wx2NJq+r3jGNwNiF9piac4i086bRhXkwq+zOodFXqU8J3j6hEL3rfwNsy4SR5Wzo t7zBkw== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bxffs0wdt-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 27 Jan 2026 03:22:39 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2a0f47c0e60so109480955ad.3 for ; Mon, 26 Jan 2026 19:22:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1769484158; x=1770088958; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=SRWtTSxZKt9shz1rrr3v/9A8UR0BGn1xkHJq01jFs8o=; b=jMhJBWSdX7wldatwlUq6Dft9ToqJJqD/cyF/XJEhiNTRO48CCVlRLzAOLtJdzeV6tB sYEmlZUpAi2yPBBMGnFsmvTOA7iTJchFsJCbuV06yNW/cwX578UVeu9CjEsqMg7nXk3y scSJCMrtwlNoWRvFH9LJPWnq7RvyVfmKeEwjjA8VHZD4mKGJuS5H3bPVe3oyMmNB6mUs lawFnpOmDb6Rp5ocURZoosEViLHBfXSn0bFwYyqSjRX9E/EgoHCqbh+MDaYRYQ2k9/jS /Chw4WvOzJvFK7PGpt7aQcrhessBlXv1Z00cGDsIYGZxS6ZSGcU7Yl8GtXD8L19bA2uQ QMJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769484158; x=1770088958; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=SRWtTSxZKt9shz1rrr3v/9A8UR0BGn1xkHJq01jFs8o=; b=EVN944SVRtlzA67v5x9i+fK4vzunmR/klLoDEpTbfHQtsYKSZeRq1CsWBXycDBa/ql ccxpZRYPwXSbcTNuWmptDigC8eN6OeT1kACoS30/I1TNxMSsrdzW170M7yCesYTbWTiF MyIrqyKeej8+Yfbc8KtMPtsRFTV59n+BI0QydamC1kADIuD1nZgbjCeQqL0yCJ5Ph67D NdlaZQ6zeMsxTH9xXZiyyw+1Bm6Su5heQVtbgNXYxjiwIKiS00Nt82UMQnHlLY0I1ZrL 5RdUCEAv2iNUqhTcpJ8vgfpPKlQv/HRI9QU47VdMFJOrhWYdiAtRZGnDJ2UgsO4Kz4aV SLRg== X-Forwarded-Encrypted: i=1; AJvYcCXxUHbFSvOiviWMJ5oaK1ivk1+9WpvxHAUbsjcE64woljvmwEBRtCL5qGtdbXGF/QeXdng4no0Xr9zYc0M=@vger.kernel.org X-Gm-Message-State: AOJu0YxhJAd7xy4OyP5TBmwfXv8dXcnqeD+6zpjyvJ7u1gsNH475Xx12 aZKnSmDCunh4bxmmsiN78eBHBwCtU6FxBzKk/yYOOAKNoTuMOPz3MzzCwK7roz2gPkGkrb9E13S nbi2EkZmFuQdrWbEsUylshu4T1gHcDgZ0t9sUSsllaRjZ/7N4ox4CNThSDkhWES2/sew= X-Gm-Gg: AZuq6aIIVxvNrjC6UJOaAxrIxhzykttQBAbSQnls5MHeM3PXVisVFYDoiireX8MQkp3 8yrTC6chQB2h9AVlMZX0u+cLenUenx+hZn5nw1N0fzYQpfWpsqgcBAl7dy7OM+NlRglTOt+XmdZ q17DGy9baQtyIkbDINeDT6VopyiY5WBIwfWQ7ncko9CJuaVn+VA+O+XHA/PYgPv4zK18/ibs/qd HN/vH6r3ROp+uye1j4ELMp4/0j6OAXOEdvMcqbEc66F2m8xAo6x9RaSOtviq/R/xm2XbilTx5ae QUUaqklZyfiJi/pi4/9d4d0beP5zKCoCPbJhqlx21/UvPSLKTkWZuQGkG1ISCN4NqZJTlVFXeBQ N498fK2eE0aTzMRwFe0vsR2gmTc9oewGr X-Received: by 2002:a17:902:c942:b0:2a1:3ade:c351 with SMTP id d9443c01a7336-2a870d32b82mr3997035ad.2.1769484158216; Mon, 26 Jan 2026 19:22:38 -0800 (PST) X-Received: by 2002:a17:902:c942:b0:2a1:3ade:c351 with SMTP id d9443c01a7336-2a870d32b82mr3996805ad.2.1769484157710; Mon, 26 Jan 2026 19:22:37 -0800 (PST) Received: from [169.254.0.6] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a802daa874sm101341625ad.13.2026.01.26.19.22.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 19:22:37 -0800 (PST) From: Raviteja Laggyshetty Date: Tue, 27 Jan 2026 03:22:07 +0000 Subject: [PATCH v2 2/2] interconnect: qcom: glymur: Add Mahua SoC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260127-mahua_icc-v2-2-f0d8ddf7afca@oss.qualcomm.com> References: <20260127-mahua_icc-v2-0-f0d8ddf7afca@oss.qualcomm.com> In-Reply-To: <20260127-mahua_icc-v2-0-f0d8ddf7afca@oss.qualcomm.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Raviteja Laggyshetty , Mike Tipton Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Odelu Kukatla X-Mailer: b4 0.14.2 X-Proofpoint-GUID: 67Nzy8ko88t7RXKsF112l2teMRxYSKKh X-Authority-Analysis: v=2.4 cv=YpcChoYX c=1 sm=1 tr=0 ts=69782f7f cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=niA-Db4sJa1Ec6H3ubUA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: 67Nzy8ko88t7RXKsF112l2teMRxYSKKh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI3MDAyNSBTYWx0ZWRfXyXZ+gEcMUVE3 WofLp8K2avNVxxjDivrlNEjVbSiOSs2fcbBWRgcqGr9H+9LGzbAoehScEJ4ga6Xk3adgwXxRrj3 j45fBPao4faj5GQyV1Jrmj++v7B7ayMYrkTIf86vM6Q/1Jme6Yk1qCwPLiQgQ24dgbNkTAEOg+6 E783q0LAv7gJAqg4VWw65QLtCedqjMmhtkn6WdGcHJ50rhyT2qTEy+8xktjgZ8iGD5/AHqHKUwC akNTD+SR+cXzygQOU9N+8af1MdgKuFH2CCZskT52X7f+rYpHwI5x1hWThSUKFJ3GkSXdECl/kqb qDM+tr4ZSxbCY5nqrFeMSsilQfNcfnfraIZhWFm3qbDLHc1OIzaHXYZ1yujoqMnZ7ZRvRBpo+pR JOqRju+rxSqq1lYYydmv5ApxLcTwa2/QqZdrdWDDrsGIn+By/sJu7pKjWpdUbYShVbzro2AsFq0 IUZ+/Neyu9VH2Dto/gg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-27_01,2026-01-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 phishscore=0 impostorscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601270025 Mahua is a derivative of the Glymur SoC. Extend the Glymur driver to support Mahua by: 1. Adding new node definitions for interconnects that differ from Glymur (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC). 2. Reusing existing Glymur definitions for identical NoCs. 3. Overriding the channel and buswidth, with Mahua specific values for the differing NoCs Co-developed-by: Odelu Kukatla Signed-off-by: Odelu Kukatla Signed-off-by: Raviteja Laggyshetty Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/interconnect/qcom/glymur.c | 38 +++++++++++++++++++++++++++++++++-= ---- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/interconnect/qcom/glymur.c b/drivers/interconnect/qcom= /glymur.c index e5c07795a6c67ab8a59daf2fc4b8a5fa6dd014d6..cfe061c1a75a692c252c4a0d4ea= 63e71308223ba 100644 --- a/drivers/interconnect/qcom/glymur.c +++ b/drivers/interconnect/qcom/glymur.c @@ -9,6 +9,7 @@ #include #include #include +#include #include =20 #include "bcm-voter.h" @@ -1985,7 +1986,7 @@ static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = =3D { &bcm_cn1, }; =20 -static struct qcom_icc_node * const cnoc_cfg_nodes[] =3D { +static struct qcom_icc_node *cnoc_cfg_nodes[] =3D { [MASTER_CNOC_CFG] =3D &qsm_cfg, [SLAVE_AHB2PHY_SOUTH] =3D &qhs_ahb2phy0, [SLAVE_AHB2PHY_NORTH] =3D &qhs_ahb2phy1, @@ -2093,7 +2094,7 @@ static struct qcom_icc_bcm * const hscnoc_bcms[] =3D { &bcm_sh1, }; =20 -static struct qcom_icc_node * const hscnoc_nodes[] =3D { +static struct qcom_icc_node *hscnoc_nodes[] =3D { [MASTER_GPU_TCU] =3D &alm_gpu_tcu, [MASTER_PCIE_TCU] =3D &alm_pcie_qtc, [MASTER_SYS_TCU] =3D &alm_sys_tcu, @@ -2377,7 +2378,7 @@ static struct qcom_icc_bcm * const pcie_west_anoc_bcm= s[] =3D { &bcm_sn6, }; =20 -static struct qcom_icc_node * const pcie_west_anoc_nodes[] =3D { +static struct qcom_icc_node *pcie_west_anoc_nodes[] =3D { [MASTER_PCIE_WEST_ANOC_CFG] =3D &qsm_pcie_west_anoc_cfg, [MASTER_PCIE_2] =3D &xm_pcie_2, [MASTER_PCIE_3A] =3D &xm_pcie_3a, @@ -2409,7 +2410,7 @@ static struct qcom_icc_bcm * const pcie_west_slv_noc_= bcms[] =3D { &bcm_sn6, }; =20 -static struct qcom_icc_node * const pcie_west_slv_noc_nodes[] =3D { +static struct qcom_icc_node *pcie_west_slv_noc_nodes[] =3D { [MASTER_HSCNOC_PCIE_WEST] =3D &qnm_hscnoc_pcie_west, [MASTER_CNOC_PCIE_WEST_SLAVE_CFG] =3D &qsm_cnoc_pcie_west_slave_cfg, [SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] =3D &qhs_hscnoc_pcie_west_ms_mpu_cfg, @@ -2470,6 +2471,28 @@ static const struct qcom_icc_desc glymur_system_noc = =3D { .num_bcms =3D ARRAY_SIZE(system_noc_bcms), }; =20 +static int glymur_qnoc_probe(struct platform_device *pdev) +{ + if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) { + llcc_mc.channels =3D 8; + ebi.channels =3D 8; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) { + qns_llcc.channels =3D 8; + chm_apps.channels =3D 4; + qnm_pcie_west.buswidth =3D 32; + hscnoc_nodes[MASTER_WLAN_Q6] =3D NULL; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc"))= { + qns_pcie_west_mem_noc.buswidth =3D 32; + pcie_west_anoc_nodes[MASTER_PCIE_3A] =3D NULL; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-cnoc-cfg")) { + cnoc_cfg_nodes[SLAVE_PCIE_3A_CFG] =3D NULL; + } else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-slv-noc= ")) { + pcie_west_slv_noc_nodes[SLAVE_PCIE_3A] =3D NULL; + } + + return qcom_icc_rpmh_probe(pdev); +} + static const struct of_device_id qnoc_of_match[] =3D { { .compatible =3D "qcom,glymur-aggre1-noc", .data =3D &glymur_aggre1_noc}, { .compatible =3D "qcom,glymur-aggre2-noc", .data =3D &glymur_aggre2_noc}, @@ -2477,12 +2500,15 @@ static const struct of_device_id qnoc_of_match[] = =3D { { .compatible =3D "qcom,glymur-aggre4-noc", .data =3D &glymur_aggre4_noc}, { .compatible =3D "qcom,glymur-clk-virt", .data =3D &glymur_clk_virt}, { .compatible =3D "qcom,glymur-cnoc-cfg", .data =3D &glymur_cnoc_cfg}, + { .compatible =3D "qcom,mahua-cnoc-cfg", .data =3D &glymur_cnoc_cfg}, { .compatible =3D "qcom,glymur-cnoc-main", .data =3D &glymur_cnoc_main}, { .compatible =3D "qcom,glymur-hscnoc", .data =3D &glymur_hscnoc}, + { .compatible =3D "qcom,mahua-hscnoc", .data =3D &glymur_hscnoc}, { .compatible =3D "qcom,glymur-lpass-ag-noc", .data =3D &glymur_lpass_ag_= noc}, { .compatible =3D "qcom,glymur-lpass-lpiaon-noc", .data =3D &glymur_lpass= _lpiaon_noc}, { .compatible =3D "qcom,glymur-lpass-lpicx-noc", .data =3D &glymur_lpass_= lpicx_noc}, { .compatible =3D "qcom,glymur-mc-virt", .data =3D &glymur_mc_virt}, + { .compatible =3D "qcom,mahua-mc-virt", .data =3D &glymur_mc_virt}, { .compatible =3D "qcom,glymur-mmss-noc", .data =3D &glymur_mmss_noc}, { .compatible =3D "qcom,glymur-nsinoc", .data =3D &glymur_nsinoc}, { .compatible =3D "qcom,glymur-nsp-noc", .data =3D &glymur_nsp_noc}, @@ -2490,14 +2516,16 @@ static const struct of_device_id qnoc_of_match[] = =3D { { .compatible =3D "qcom,glymur-pcie-east-anoc", .data =3D &glymur_pcie_ea= st_anoc}, { .compatible =3D "qcom,glymur-pcie-east-slv-noc", .data =3D &glymur_pcie= _east_slv_noc}, { .compatible =3D "qcom,glymur-pcie-west-anoc", .data =3D &glymur_pcie_we= st_anoc}, + { .compatible =3D "qcom,mahua-pcie-west-anoc", .data =3D &glymur_pcie_wes= t_anoc}, { .compatible =3D "qcom,glymur-pcie-west-slv-noc", .data =3D &glymur_pcie= _west_slv_noc}, + { .compatible =3D "qcom,mahua-pcie-west-slv-noc", .data =3D &glymur_pcie_= west_slv_noc}, { .compatible =3D "qcom,glymur-system-noc", .data =3D &glymur_system_noc}, { } }; MODULE_DEVICE_TABLE(of, qnoc_of_match); =20 static struct platform_driver qnoc_driver =3D { - .probe =3D qcom_icc_rpmh_probe, + .probe =3D glymur_qnoc_probe, .remove =3D qcom_icc_rpmh_remove, .driver =3D { .name =3D "qnoc-glymur", --=20 2.43.0