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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1247d90cda6sm21064235c88.1.2026.01.27.00.34.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jan 2026 00:34:13 -0800 (PST) From: Jingyi Wang Date: Tue, 27 Jan 2026 00:34:02 -0800 Subject: [PATCH v4 05/10] arm64: dts: qcom: kaanapali: Add support for audio Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260127-knp-dts-misc-v4-5-02723207a450@oss.qualcomm.com> References: <20260127-knp-dts-misc-v4-0-02723207a450@oss.qualcomm.com> In-Reply-To: <20260127-knp-dts-misc-v4-0-02723207a450@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jingyi Wang , 20260114-knp-remoteproc-v4-0-fcf0b04d01af@oss.qualcomm.com, Prasad Kumpatla , Konrad Dybcio X-Mailer: b4 0.15-dev-3d134 X-Developer-Signature: v=1; a=ed25519-sha256; t=1769502846; l=13518; i=jingyi.wang@oss.qualcomm.com; s=20250911; h=from:subject:message-id; bh=mM6/Pdb0cyGMtp4tKPrPt12aQw9v62w/vSt6EMdglN0=; b=/5RnCjrNJ8ma9ejG9Yemt6/mdl8wsqfbV2J1blBPP3iffGK4IS0Q1mkLTZz9gkVfQrTPBGwPf 0Pf9erL11WLADFsqvVUjetZ1a8iWbFz32mB0fRSuED1IulGykf1CQE9 X-Developer-Key: i=jingyi.wang@oss.qualcomm.com; a=ed25519; pk=PSoHZ6KbUss3IW8FPRVMHMK0Jkkr/jV347mBYJO3iLo= X-Proofpoint-ORIG-GUID: pqbzPnHYgUmDRG9WkgfDtwPL1pAMWmJG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI3MDA2OSBTYWx0ZWRfX46bGQS9tYufj dTQOvvjfTUVWLoyMYADPLJhEJKZbpN5IshRXno5gsmlD2cVeZHfCmHNr4HqGYNHEzu8ABuUNd9n y6Zp+v/ToDIHd9kI1uvC0bDl43ESk1wme5ZcGRIpZtajIc/wcHsVSmbvAq1UcciZyAfamwRG6wm 19EutGaK7M2/ZkMcdBBiRK/TcTOqCibDH0s/4yif3BsvT9w8xD1SuHDT1rUt1WhJsdIvm1t6OCR RRnKi3r5IL0wX0mH7gwDtK6qwwuuyvx2CjjlO3ykZbsSt6xw3lqyQgZbZL0PZVHD0Llv0kDBuyi lbbQYSfcL5G+se/4UpZVhRV4AmuLr2/yW2NF8bXZmU/iZ3+iBqR2o1wvX2QzPqGiXXoySTidMp3 f67szCCvYLxWhVVAel73VY3oA4lj64r++MR4kIf6N6ObyHOltPwTVazG+QHFe83ygghi5wscGG5 4uu0lurlcYbodI0vAHg== X-Proofpoint-GUID: pqbzPnHYgUmDRG9WkgfDtwPL1pAMWmJG X-Authority-Analysis: v=2.4 cv=FsEIPmrq c=1 sm=1 tr=0 ts=69787888 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=fOvlSJoLLuNaJOMVFRMA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-27_01,2026-01-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 adultscore=0 malwarescore=0 suspectscore=0 impostorscore=0 bulkscore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601270069 From: Prasad Kumpatla Introduce audio support for Kaanapali SoC by adding LPASS macro codecs, TLMM pin controller and SoundWire controller with similar hardware implementation to SM8750 platform. Also add GPR (Generic Pack Router) node along with support for APM (Audio Process Manager) and PRM (Proxy Resource Manager) audio services. Reviewed-by: Konrad Dybcio Signed-off-by: Prasad Kumpatla Signed-off-by: Jingyi Wang Reviewed-by: Abel Vesa --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 367 ++++++++++++++++++++++++++++= ++++ 1 file changed, 367 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index c8f61200f261..050d47691f5c 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -16,7 +16,9 @@ #include #include #include +#include #include +#include =20 #include "kaanapali-ipcc.h" =20 @@ -2632,6 +2634,371 @@ compute-cb@7 { dma-coherent; }; }; + + gpr { + compatible =3D "qcom,gpr"; + qcom,glink-channels =3D "adsp_apps"; + qcom,domain =3D ; + qcom,intents =3D <512 20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + q6apm: service@1 { + compatible =3D "qcom,q6apm"; + reg =3D ; + #sound-dai-cells =3D <0>; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible =3D "qcom,q6apm-lpass-dais"; + #sound-dai-cells =3D <1>; + }; + + q6apmdai: dais { + compatible =3D "qcom,q6apm-dais"; + iommus =3D <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1041 0x20>; + }; + }; + + q6prm: service@2 { + compatible =3D "qcom,q6prm"; + reg =3D ; + qcom,protection-domain =3D "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible =3D "qcom,q6prm-lpass-clocks"; + #clock-cells =3D <2>; + }; + }; + }; + }; + }; + + lpass_wsa2macro: codec@6aa0000 { + compatible =3D "qcom,kaanapali-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg =3D <0x0 0x06aa0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "wsa2-mclk"; + #sound-dai-cells =3D <1>; + }; + + swr3: soundwire@6ab0000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06ab0000 0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_wsa2macro>; + clock-names =3D "iface"; + label =3D "WSA2"; + + pinctrl-0 =3D <&wsa2_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <9>; + + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18= f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_rxmacro: codec@6ac0000 { + compatible =3D "qcom,kaanapali-lpass-rx-macro", "qcom,sm8550-lpass-rx-m= acro"; + reg =3D <0x0 0x06ac0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + swr1: soundwire@6ad0000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06ad0000 0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_rxmacro>; + clock-names =3D "iface"; + label =3D "RX"; + + pinctrl-0 =3D <&rx_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <1>; + qcom,dout-ports =3D <11>; + + qcom,ports-sinterval =3D /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xf= f 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0x= ff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xf= f 0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff= 0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff= 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 = 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x0= 0 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xf= f 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_txmacro: codec@6ae0000 { + compatible =3D "qcom,kaanapali-lpass-tx-macro", "qcom,sm8550-lpass-tx-m= acro"; + reg =3D <0x0 0x06ae0000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + lpass_wsamacro: codec@6b00000 { + compatible =3D "qcom,kaanapali-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg =3D <0x0 0x06b00000 0x0 0x1000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names =3D "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + }; + + swr0: soundwire@6b10000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x06b10000 0 0x10000>; + interrupts =3D ; + clocks =3D <&lpass_wsamacro>; + clock-names =3D "iface"; + label =3D "WSA"; + + pinctrl-0 =3D <&wsa_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <9>; + + qcom,ports-sinterval =3D /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18= f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x= ff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0x= ff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xf= f 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff= 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08= 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 = 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xf= f 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + swr2: soundwire@7630000 { + compatible =3D "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg =3D <0 0x07630000 0 0x10000>; + interrupts-extended =3D <&intc GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "core", "wakeup"; + clocks =3D <&lpass_txmacro>; + clock-names =3D "iface"; + label =3D "TX"; + + pinctrl-0 =3D <&tx_swr_active>; + pinctrl-names =3D "default"; + + qcom,din-ports =3D <4>; + qcom,dout-ports =3D <0>; + qcom,ports-sinterval-low =3D /bits/ 8 <0x01 0x01 0x03 0x03>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x01 0x01>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x02 0x00 0x00>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + status =3D "disabled"; + }; + + lpass_vamacro: codec@7660000 { + compatible =3D "qcom,kaanapali-lpass-va-macro", "qcom,sm8550-lpass-va-m= acro"; + reg =3D <0 0x07660000 0 0x2000>; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUP= LE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "mclk", "macro", "dcodec"; + + #clock-cells =3D <0>; + clock-output-names =3D "fsgen"; + #sound-dai-cells =3D <1>; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible =3D "qcom,sm8750-lpass-lpi-pinctrl", + "qcom,sm8650-lpass-lpi-pinctrl"; + reg =3D <0 0x07760000 0 0x20000>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", "audio"; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio7"; + function =3D "dmic1_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + drive-strength =3D <8>; + output-high; + }; + + data-pins { + pins =3D "gpio9"; + function =3D "dmic2_data"; + drive-strength =3D <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins =3D "gpio15"; + function =3D "wsa2_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio16"; + function =3D "wsa2_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; }; }; =20 --=20 2.25.1