From nobody Sat Feb 7 08:06:52 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31B9235CBB0 for ; Tue, 27 Jan 2026 15:47:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769528869; cv=none; b=nFQ9IFWr/T69jDT/A596bRKDQ5C2o0gDA09z6MXMbL+2zKO0ZAd/aIS5aAJxnTUfD+uOxNADpY/HL/zJrRkbMmlWJDV+7E6IoH83HFpigAZqc7qJ5jXb8in8NFJdu2p3F1rf03dIuk4sO/KbAtdPHbLZAJhlG6dIbtS0eAMnvpk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769528869; c=relaxed/simple; bh=btLjZKbRLBmL6B22+eSZjzaQzdAIEk75myjZbhNfse4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=N0ANPWTCkrNsGVUz58is4qPli0rmlyNEIjqbuIcNu6lZFJng9GBvHOsSMXDQa+ZVpJ2HOV+UsZIoOxpHprEc1Z4fRlXFE0aF5XNGrENmph5oxVNxeMuBKWKPk/ReCqpTorkJ3bY9pGgPui4tq1kUlRkLnWvxJ0Q2aTMBpTSe+FY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=i/xoNqlK; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=TIoP8KCo; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="i/xoNqlK"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="TIoP8KCo" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60RBwROH1135564 for ; Tue, 27 Jan 2026 15:47:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= N6cshVERWzUvY/NIyt6rQ5hqeOfdBV7Vm5kV4VlEHFA=; b=i/xoNqlKPklwJmK9 BjnChEcLx0fpzZPm2MOPAevJtqygt60kF1bEoie5DKqgFBSZ3ZdBsDZLTFwmMXrq yNQmivqqz0dyR/MytYz3pgsej9ycyPWTkj0ekpCyD2u4gnT9+vIAzX6qnwgYwMhp rIal4EFTnb1egbh78st0yrsz8hsUplKB3mFeTl6udlf0Sz2MDbUul8EaSlG/YEBq D3lP9cSUEk95GSE1tgAPXLtY1dKbO7FcpOygcmLJxl4+4e5Gz16JNqb6nPHFjBsj c2sDQscGaKy5BPvle8EtDbjMVcY0CT5eNDYlu0pdwU/cVCOBzZ1z6aCuRTOGRfqy HURfog== Received: from mail-qk1-f197.google.com (mail-qk1-f197.google.com [209.85.222.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bxsjehek0-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 27 Jan 2026 15:47:46 +0000 (GMT) Received: by mail-qk1-f197.google.com with SMTP id af79cd13be357-8c70e610242so103268685a.2 for ; Tue, 27 Jan 2026 07:47:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1769528866; x=1770133666; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=N6cshVERWzUvY/NIyt6rQ5hqeOfdBV7Vm5kV4VlEHFA=; b=TIoP8KColQUSz4M5ALICk0lkvCi1a+S4aI1DbrtCdWqvDgiTCpRVlM2phl0TizrRMm P1og5Mr1fN0NZauytu5CKFiujjP5CmGnmQaV3msUjxqIYxngaZvLoQTMarww8Zm++6pi sFNlOCs1qgygGe+qhNTQH5AFjq8HQCiizUeYdUprHkuiJibQhsWewwG2jbnYNaPE+V0s n0VRBWNIZIdVzoTb9FSPls35agHi+qvVpJvL3pzdaOo2IuwLWpMpgontTQjD8fbqUzMV vDdVzis9r314HhxHK16iCGEvHFSDn70kFw6yhqgAjcPv+vNJCivFYld8oRbpj+J8vXSi Yzrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769528866; x=1770133666; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=N6cshVERWzUvY/NIyt6rQ5hqeOfdBV7Vm5kV4VlEHFA=; b=JFVReESAywrGxJptJivYpP9D2d1+WOlFSUWKSGpFjgAHymARZgCSE7YBJ4nutwjkvw lawU6xHqZMvOmr8Yd+zNUm4aCwnMPT05TDxFLMC4yTolkqRs3MWf2lKQ6Z2D1ZpuY9kd MPspujI9md/pIRgdya4Ykt8pr2JxZ9RLCN0ijcwpbi6Jhx3pj+L8i2Xy3pE17i7SZS+j Uh/cc8bLLwsVr/1tz7ktcIKxMfELmpQzJrl0G62umvoBu8/mHZ5aP4ZbezWj14wwUwPZ gpnlobgEfb5Z4QE0MsHf0m/9Bw1iJPaFS6yWxonO0O6CrXGFVMusvMR+oISgzYPQgrpt Ll9A== X-Forwarded-Encrypted: i=1; AJvYcCVNyMLZkSIL8qz1+QbsSfUlXzSq9Ktev2Fsaqg6vlaph8fvSREM7xtqMyRilGLR6VZ0rGmViol2mNzmF+o=@vger.kernel.org X-Gm-Message-State: AOJu0Yyjk05A4iieIBINtiuRcXHqi84Dw4O/Dz2EwSLX0r72IseLIBU0 JZMqunvFJmFc6FlH1JmB4OEC3BphNt8Bl+6AivNDvyUWbogHY/+OzBGontNXFgY6Cp+QUcdmuk6 Uk3iIIy6CXQ0X/h4ZGgzy2Q31K0X6unrxj7ajqV5WXyqLg3zswxWK2tXBp5YxIrHOc9w= X-Gm-Gg: AZuq6aKR4ZOhpkmM518hK1b9eWbq5Q14grT3MjHny4UCknQNqMX+zlSOTmX/s++SsOT mx1Uk4auh9/fkSDtqBOxZnBi3x9KYhmxeCL1/Jf4QoDCw6ls1LJNdie8L8ydsO8Og5XgYq41wxR XqlPuE+lRTy69UM/oBTyavr1Eh21nlOjrk0mCJ9+7rbgK15tl8dNcySO2pO/n7ryMfRl6BomuDK iXqI8ZE9+3FDDrEtO67A7VG0Vtrb23Nzips6BugoRNGjZNQ5Fq2QaoXCOolZ1vHUWvCK/abmcpF pbZ0yIxXjpB8hq8OAk8Seso9anSvPsfRHTpdflkWBkoj2raHs6oLdDiYQed3+rgzzV8THLSnmGt 2XF5NiqRzPgZ9h04tYA== X-Received: by 2002:a05:620a:1908:b0:8c5:2f70:c62b with SMTP id af79cd13be357-8c70b92d7cdmr249639785a.85.1769528866194; Tue, 27 Jan 2026 07:47:46 -0800 (PST) X-Received: by 2002:a05:620a:1908:b0:8c5:2f70:c62b with SMTP id af79cd13be357-8c70b92d7cdmr249635785a.85.1769528865507; Tue, 27 Jan 2026 07:47:45 -0800 (PST) Received: from hackbox.lan ([86.121.162.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435b1c24bf8sm38096465f8f.11.2026.01.27.07.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jan 2026 07:47:44 -0800 (PST) From: Abel Vesa Date: Tue, 27 Jan 2026 17:47:36 +0200 Subject: [PATCH v2 1/2] dt-bindings: pinctrl: document the Eliza Top Level Mode Multiplexer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260127-eliza-pinctrl-v2-1-1faf78efdc2e@oss.qualcomm.com> References: <20260127-eliza-pinctrl-v2-0-1faf78efdc2e@oss.qualcomm.com> In-Reply-To: <20260127-eliza-pinctrl-v2-0-1faf78efdc2e@oss.qualcomm.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=openpgp-sha256; l=5255; i=abel.vesa@oss.qualcomm.com; h=from:subject:message-id; bh=btLjZKbRLBmL6B22+eSZjzaQzdAIEk75myjZbhNfse4=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBpeN4cHcoLLxMKyq0/69Lkx9zC9v7VY44dAVY33 q2ABsy88kyJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaXjeHAAKCRAbX0TJAJUV VmBVD/wPgBJI1Sy28m1KNHnUhLLSp1nwgiIJQbT/7Bh7EzSVeZaW47jWsZMj9jxMJ5rkqduTyHx 208mCuceS55gFwQOIIcxq0Y40UUbuYmNzNiudRDGd7Ycnz0N4E1/vQAt5QAoWlmi5280E1Wuek5 MsL5o9e+J7NGJdt/DEq4C4rhPFflb16M/clme0FpGKFU5CK/0SlIp01+7ziMZSL1jIC/iofqMq0 vaZnQiLFkPW+HZPU1TNF9sqKf+S34vLweHVvOPVDQvsWzIrw92If664TM/dLP519Bts5Q9Vfzz6 ioFv1GoCWx5wp3+c0B/IuFu22UDT65XqLFOMBMwhJf2kLTZHu6du8NbzVkLrigrUTQ0Nz5OGSRk Cw1BpKgEhqCoZnFf4/EXkJwlCN48aUSDnFRQzSYithg8+N+xctqsniPv/8F4VV+dGoGYempUcx3 MxBVkMSf2aLZAiHEs7kWdQtr2xK3vEvsi7NyzM+fiuq7A5Hmn+SAxo6Pr2lEK1CY3oeKkWCaVrI CabXdWH8bfhHkzXtIpYJU3XfFK6Y2XvbzcDhFsyp5BI1dJicrTL+j/+K40LUHqT7EYtc8VgD4KA xiBtrN2SsNpK+zaRPj/QIsd2+HpSEnHVsoB8zqUilaDE3Bq2PfHcBN287VE9xAFdukak23mYPTw JrYwAQJpRVEAUuw== X-Developer-Key: i=abel.vesa@oss.qualcomm.com; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI3MDEyOSBTYWx0ZWRfX+awBu3RmQu69 ZDprS0rxeFp+67xKmUMTAYG0bI7P9L7nMs1gvzTOENSYC6440eocXmjAIz7wMvbxRp3+UWDbvFg 519JhIRl1srCip+snBMIYOCnWJqOl/Md0dHYR7aQpk4crmnjkWTn+hMeKsuBuWUH2nZcWDi4NYn kTk2fJduyPdflRLzj0tT0agS1yabA47HwQ1kTUrOjkgXVf9FrkiAdHi6WjT8YUR3sE0fHwmrfxW WbpOHfpZqT/eyZP8wSn125WPLCP121EBinqI2lR6bWxYn/3UxfZnWVdKevMSVVsQJFdBiR9zcUF cGyBhtiD7PtTf9kFjfG09ypYbB4U7HuDrv5IQxCB37oPM/0vJgkfPlMfrFjyD7DY86YCcCryF31 pGf37Upgf+VXrRyA+s2ZQz4KybCX2SiGStdzwSja2BK1o7SHjmEAqygnO10mAAel0S8Vre6AYav CWKaQuhsvNnP2lk7Ojw== X-Authority-Analysis: v=2.4 cv=Qelrf8bv c=1 sm=1 tr=0 ts=6978de23 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=oauzzCmhM186DRC0Y2yWPg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=RS--hHaVoNrYE_hnkMsA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: Gl20NXYCnoIZLG-d7JBlSYzCFuAvpSA_ X-Proofpoint-GUID: Gl20NXYCnoIZLG-d7JBlSYzCFuAvpSA_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-27_03,2026-01-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 adultscore=0 phishscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601270129 Document the Top Level Mode Multiplexer on the Eliza Platform. Signed-off-by: Abel Vesa Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,eliza-tlmm.yaml | 138 +++++++++++++++++= ++++ 1 file changed, 138 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml= b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml new file mode 100644 index 000000000000..d8b6591caf57 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,eliza-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Eliza TLMM block + +maintainers: + - Abel Vesa + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Eliza SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,eliza-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 84 + + gpio-line-names: + maxItems: 185 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-eliza-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-eliza-tlmm-state" + additionalProperties: false + +$defs: + qcom-eliza-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-5])$" + - enum: [ ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specif= ied + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, + audio_ref_clk, cam_mclk, cci_async_in, cci_i2c_scl, + cci_i2c_sda, cci_timer, coex_uart1_rx, coex_uart1_tx, + coex_uart2_rx, coex_uart2_tx, dbg_out_clk, + ddr_bist_complete, ddr_bist_fail, ddr_bist_start, + ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot, egpio, + gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1, + hdmi_ddc_scl, hdmi_ddc_sda, hdmi_dtest0, hdmi_dtest1, + hdmi_hot_plug, hdmi_pixel_clk, hdmi_rcv_det, hdmi_tx_cec, + host2wlan_sol, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, + ibi_i3c, jitter_bist, mdp_esync0_out, mdp_esync1_out, + mdp_vsync, mdp_vsync0_out, mdp_vsync11_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, + pcie0_clk_req_n, pcie1_clk_req_n, phase_flag, + pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio_traceclk, + qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable, + qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi_clk, + qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, + qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, + qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2, + sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0, + tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, + tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk, + uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, + uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1, + vsense_trigger_mirnat, wcn_sw_ctrl ] + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,eliza-tlmm"; + reg =3D <0x0f100000 0x300000>; + + interrupts =3D ; + + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + gpio-ranges =3D <&tlmm 0 0 186>; + + gpio-wo-state { + pins =3D "gpio1"; + function =3D "gpio"; + }; + + qup-uart14-default-state { + pins =3D "gpio18", "gpio19"; + function =3D "qup2_se5"; + drive-strength =3D <2>; + bias-disable; + }; + }; +... --=20 2.48.1 From nobody Sat Feb 7 08:06:52 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5490E35E533 for ; Tue, 27 Jan 2026 15:47:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769528874; cv=none; b=NN3SusDh94wc7Jo/pv4IwTBCoK+1kJotqaUOLLCHJnduqa1IIl8sOhU6DijfSqmU9JNprn6+btiwkN6ioRSoeW8hgFkICJv1N+vsH6SXc8nMsfZ4ONS6Njo3p9O9C1TVzhzi7l3eWx7ZZlxSB7b6CBsFEcAWnoFgtQ9TmpWJO24= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769528874; c=relaxed/simple; bh=nqWhrO1mvgPY4QY2+LAy5EvOfSe+0jlqRVK2OmYpi68=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZJh4V3qjIx6BVTwmGFfoH3vdr9QavxXEppwONAqjTjahHLQ8UvVjm/fO/yNykHzh2jsj6xxIPu4SaTksJ66iPtH1WHexA3wVzq8CD/KXaDsgtFYunNENgNqepQWX2FUcYTZuAzAgsVGYQ3lczNExyoEo7EP9qxUHJTTPSlatSaw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=TLAVIRCv; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=fuJs9RUh; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="TLAVIRCv"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="fuJs9RUh" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60R9t2SQ3857567 for ; Tue, 27 Jan 2026 15:47:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= gt+dZ0XP2jWa0lxeXFndFSXZY3ek5QuxIO1HicxQm9A=; b=TLAVIRCvV4rtRp06 +bfqCUzqD8gzMMnoxzaGSa6FVVdB1IQc4k/zMHwzL321cW+73pTh+Wh6XbAlFjvY ba6ees8lfyOUYhJlpPrxk/Kpd/g78aLOO8yqgn9BAK0IwLUKvhbUaX3eGvUtNgAQ fu+5n2rt1jhgkv01F/8mB8zl3iB+cKNqchd84LSZ2RCwUaybVqVkCZDXNa+IimX8 2VYhN+ubv+9MviqL4ElgBsq25as02a5Nb8iDW3Bkk8xBIsp1epy9vk/sL7JX/fy7 jOQkkbAOOJfs+tWBsESWufSgnP2JfEkZE2yzQiQs84VB9v7XAamOVLMq88jr4p4x VWp0zw== Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bxffs396d-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 27 Jan 2026 15:47:50 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-8c6a7fb4421so1461052085a.3 for ; Tue, 27 Jan 2026 07:47:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1769528869; x=1770133669; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gt+dZ0XP2jWa0lxeXFndFSXZY3ek5QuxIO1HicxQm9A=; b=fuJs9RUhB+K4tJt6Ttqw+aYU7B/uiYEElt1DG1F9NEoNr7rnmR+QGYXMqzN0RhT4oQ 0WsDoxFnRXvjshEXhmGJ9U6+t/gPnfgo/yV5cPGhlupT/yJVfTOXCEQXrOgO2TCzJLP/ u2AOYw2bGMzG6v7E+reqDnZOPo4SHwqO9F20ts00LfDVTM2VMyNImFcWedT4DRVBjd47 evEVCeA526nRE3A6LN9w5mARE57vtp/ON3VmEgm2cerxqk4lK/aAE3ezcXVHAPbbS8Zs vaj6KaQNeD6lpnbdrWB7rL13rdh0RNs1gLD5MfLgJn6uop2sZOfiSw+zLXeTMpPf92VZ hRNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769528869; x=1770133669; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=gt+dZ0XP2jWa0lxeXFndFSXZY3ek5QuxIO1HicxQm9A=; b=KPaQNMWc4qxbkIeU6NgUAJ3Bsehkmp2ydyb7mklbAD5X7p28fVqmZzxGYKgh0yUZl6 4hF7FdrWfstrE7Vko+Gj6kAji7/nQQP1sUwzEiGRRtVlfXvD6FzUErQjfkCuqjdd9/T5 aX/1XrmC1tB1/IccLIT5tFR/k1gyy8fftJODhQjywRiHdq7LyDLLJZ3JeRwFJS/+aiIr rWw09hLBfOcQetBKwsp7KAdxy/suG7WEiokLLo10jwciZbnrNlc6xJJ/7j7h4qS8zwvW FS0Z24JexYACD0zr7gC47udGULDWt90v0RQysmv93mDTJvHKw+pdADXuI25Tlu3OqQxv j/ag== X-Forwarded-Encrypted: i=1; AJvYcCWwnNjsiGw0YzfdzxLlTy+tAi5q6U6OOZbbF0/JsMRi2x0b6DFLKVDkOt/9hRXf/ydpqTEU7DeY5vJgNSE=@vger.kernel.org X-Gm-Message-State: AOJu0Yw3ciYb+Zq+vSGostxL4OYl8gocndFwfSIjwl88oSK5iIGlrOxi f+GYQUa71yQPNBdl/cZQ01SzG7nb1QpjNeeX6KnSxUjsh5pC4Lvjpzt5elvQxMwk/XrAsE33I// Sy2OVVnC1auxV3KwDiD0vBXaIFOJznVF+i5yWpdOnAjDpU50YVqGTCEH+LYZ53xQIhDM= X-Gm-Gg: AZuq6aKEkFCevcjtT0mtZHy+yY2aIekGJ5XfX+/Hd5oWmBbrGRGCxwGZCBC09PWNtan QDUq2jDyJVI7UkoXSkN9+YssA1Tj33MFgS1Mk+G07y2Sn8EXH2KNpww7gQ7NQnwG256Ld1NkIjk Cx4SGEfiDtMNVwAyOjEKoVXmezGqIBURcmeCtAQzXWXnCDl8rjJ0ITapleNjsDIlvsCvEZUqBdy 3wFdR1mHnH1oIwjWTLywobP6Jn6ZdnaHBcKI7GkmaIMyqbA+x66moG4/AFYB9n+j94AidE5cHb5 betrDmF8dDNgP3Kj/r6IfuiVZlgnKPHd68inhejQSFnndqaU/bJZS7o/iYauYzF1EuL2Lu6oLXa VdEvlX/rdFaDkS8HVEg== X-Received: by 2002:a05:620a:f04:b0:8c6:a70f:825d with SMTP id af79cd13be357-8c70b8f92e4mr256468685a.44.1769528868373; Tue, 27 Jan 2026 07:47:48 -0800 (PST) X-Received: by 2002:a05:620a:f04:b0:8c6:a70f:825d with SMTP id af79cd13be357-8c70b8f92e4mr256463085a.44.1769528867569; Tue, 27 Jan 2026 07:47:47 -0800 (PST) Received: from hackbox.lan ([86.121.162.109]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435b1c24bf8sm38096465f8f.11.2026.01.27.07.47.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jan 2026 07:47:46 -0800 (PST) From: Abel Vesa Date: Tue, 27 Jan 2026 17:47:37 +0200 Subject: [PATCH v2 2/2] pinctrl: qcom: Add Eliza pinctrl driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260127-eliza-pinctrl-v2-2-1faf78efdc2e@oss.qualcomm.com> References: <20260127-eliza-pinctrl-v2-0-1faf78efdc2e@oss.qualcomm.com> In-Reply-To: <20260127-eliza-pinctrl-v2-0-1faf78efdc2e@oss.qualcomm.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.15-dev-47773 X-Developer-Signature: v=1; a=openpgp-sha256; l=54483; i=abel.vesa@oss.qualcomm.com; h=from:subject:message-id; bh=nqWhrO1mvgPY4QY2+LAy5EvOfSe+0jlqRVK2OmYpi68=; b=owEBbQKS/ZANAwAKARtfRMkAlRVWAcsmYgBpeN4dtsump16+plLPm3rcEoT0DaifcNp5kbexL psa1x57GwmJAjMEAAEKAB0WIQRO8+4RTnqPKsqn0bgbX0TJAJUVVgUCaXjeHQAKCRAbX0TJAJUV VukBD/0Se+CmTFpIJkdUo++qL95IR9EpqBa6Hy6Jls5PeCxOwaJ7Eh3RVzkl0PwrUObWcx9EGOi 80izYkCD3FUgHqy1SZk3qnJfr/h0lKXVt6OKlj5AoQBZneJVldN2asryfquxLqU38CidmuYCNJL 8eQeHOkrwWdNiMhkaQofmdqgkDHbP2ht+cXSYrFWfAmU8X5Avmn4J3ohXkzpC0W8eW5HW5Nd5cV ICtQSNnyN8ikYXBBWUQ7zZoj5n3HvEIFTeGQup5cD2H7um9LjZsS3gAfqay0sOK20tBwB6K0fp+ dvPIGk8P+ZtrO7RfrMbXdq+6tjbFL8ne/oO14a8D7rGFD5KPliCdZa6nQYlQ+vOgOoz2Sk3zNNV BiUcZ/zZ+rQCmsEwf9oleHLIVEJdmYesaEeyfJhBzIU3sMA82G+wSvNPKv5mjUl4favU3cVjs6g FGKFv91pwiF+Y8acbccdYfPUKHaW5v5YXgES/z7XxoPANnl7MdtH+7BZnZOsxClA/dfuXVasujs zJnK/T7dfZLv3XIiFx1eRat3IOyyIggWQ4zhtkygg9eK5X8jWasKKENFUFf29W7jCUadKU+5Ib9 /+sEyG9KPw2ESnzptNgZ5hP5PWShCLabk9lPXAL1P7in9+DsnxKKSIJuPjn9kQ7HZCPxxzNiW11 zsXgKltTrL50nng== X-Developer-Key: i=abel.vesa@oss.qualcomm.com; a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-Proofpoint-GUID: 1ru3xUskD9M7SzbPgGeoznP_MeCmAD3G X-Authority-Analysis: v=2.4 cv=YpcChoYX c=1 sm=1 tr=0 ts=6978de26 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=oauzzCmhM186DRC0Y2yWPg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=tXnM-DOrMupGi_pzBnoA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-ORIG-GUID: 1ru3xUskD9M7SzbPgGeoznP_MeCmAD3G X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTI3MDEyOSBTYWx0ZWRfXyfM5+J4Bh+yG kGTRep1mE7mFWrhUe13PSYleYnHOlOG2ButnCF+MjI1JNT2SX4U5i5/xMM3eLUjpKY0nFfwDeo4 VxReGMd4xBmyOvRTt8vgFlU8Q48y+0xqBQj82Yx8Y0LeN7v5krPinSbA78DZ16GixANbVUS2/qu /K5Bw/tjnZvXHW7qheN/Bsi1BySptu2Y3npUtF8YU37DoefPbton6bI2lJOeymqxGCuq7MeiUIi z76DQ3lc8tl7UhUJEyFK7LrLQUtXSpcZX1wedCRhBr70w028fvbB5tGn9XUfZPQVfeys+ZoCYxq 50ntE0GnnS+T/f2iivtpiX0QKaiLITqRASe9zalJaETIiRfMhHwMh546Lt8weiupqFrAR6bTtCM 4Qm1Hw4RS20eknKKovBK4v+H2ECZjpdGh/5nd6n91prafYPTLYsk4MOYEfKCpxW8SkIICdVkO0Q SpwbSwI6MZgown8aF5g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-27_03,2026-01-27_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 phishscore=0 impostorscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601270129 Add pinctrl driver for TLMM block found in the Eliza SoC. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Reviewed-by: Bjorn Andersson --- drivers/pinctrl/qcom/Kconfig.msm | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-eliza.c | 1548 ++++++++++++++++++++++++++++++= ++++ 3 files changed, 1559 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfi= g.msm index 3e9e02774001..6df6159fa5f8 100644 --- a/drivers/pinctrl/qcom/Kconfig.msm +++ b/drivers/pinctrl/qcom/Kconfig.msm @@ -15,6 +15,16 @@ config PINCTRL_APQ8084 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm APQ8084 platform. =20 +config PINCTRL_ELIZA + tristate "Qualcomm Technologies Inc Eliza pin controller driver" + depends on ARM64 || COMPILE_TEST + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc Top Level Mode Multiplexer block (TLMM) + block found on the Qualcomm Technologies Inc Eliza platform. + Say Y here to compile statically, or M here to compile it as a module. + If unsure, say N. + config PINCTRL_GLYMUR tristate "Qualcomm Technologies Inc Glymur pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4269d1781015..831103b3827b 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_MSM) +=3D pinctrl-msm.o obj-$(CONFIG_PINCTRL_APQ8064) +=3D pinctrl-apq8064.o obj-$(CONFIG_PINCTRL_APQ8084) +=3D pinctrl-apq8084.o +obj-$(CONFIG_PINCTRL_ELIZA) +=3D pinctrl-eliza.o obj-$(CONFIG_PINCTRL_GLYMUR) +=3D pinctrl-glymur.o obj-$(CONFIG_PINCTRL_IPQ4019) +=3D pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ5018) +=3D pinctrl-ipq5018.o diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pi= nctrl-eliza.c new file mode 100644 index 000000000000..1a2e6461a69b --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c @@ -0,0 +1,1548 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "pinctrl-msm.h" + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ + { \ + .grp =3D PINCTRL_PINGROUP("gpio" #id, \ + gpio##id##_pins, \ + ARRAY_SIZE(gpio##id##_pins)), \ + .funcs =3D (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10, \ + msm_mux_##f11 /* egpio mode */ \ + }, \ + .nfuncs =3D 12, \ + .ctl_reg =3D REG_SIZE * id, \ + .io_reg =3D 0x4 + REG_SIZE * id, \ + .intr_cfg_reg =3D 0x8 + REG_SIZE * id, \ + .intr_status_reg =3D 0xc + REG_SIZE * id, \ + .intr_target_reg =3D 0x8 + REG_SIZE * id, \ + .mux_bit =3D 2, \ + .pull_bit =3D 0, \ + .drv_bit =3D 6, \ + .egpio_enable =3D 12, \ + .egpio_present =3D 11, \ + .oe_bit =3D 9, \ + .in_bit =3D 0, \ + .out_bit =3D 1, \ + .intr_enable_bit =3D 0, \ + .intr_status_bit =3D 0, \ + .intr_wakeup_present_bit =3D 6, \ + .intr_wakeup_enable_bit =3D 7, \ + .intr_target_bit =3D 5, \ + .intr_target_kpss_val =3D 3, \ + .intr_raw_status_bit =3D 4, \ + .intr_polarity_bit =3D 1, \ + .intr_detection_bit =3D 2, \ + .intr_detection_width =3D 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .grp =3D PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg =3D ctl, \ + .io_reg =3D 0, \ + .intr_cfg_reg =3D 0, \ + .intr_status_reg =3D 0, \ + .intr_target_reg =3D 0, \ + .mux_bit =3D -1, \ + .pull_bit =3D pull, \ + .drv_bit =3D drv, \ + .oe_bit =3D -1, \ + .in_bit =3D -1, \ + .out_bit =3D -1, \ + .intr_enable_bit =3D -1, \ + .intr_status_bit =3D -1, \ + .intr_target_bit =3D -1, \ + .intr_raw_status_bit =3D -1, \ + .intr_polarity_bit =3D -1, \ + .intr_detection_bit =3D -1, \ + .intr_detection_width =3D -1, \ + } + +#define UFS_RESET(pg_name, ctl, io) \ + { \ + .grp =3D PINCTRL_PINGROUP(#pg_name, \ + pg_name##_pins, \ + ARRAY_SIZE(pg_name##_pins)), \ + .ctl_reg =3D ctl, \ + .io_reg =3D io, \ + .intr_cfg_reg =3D 0, \ + .intr_status_reg =3D 0, \ + .intr_target_reg =3D 0, \ + .mux_bit =3D -1, \ + .pull_bit =3D 3, \ + .drv_bit =3D 0, \ + .oe_bit =3D -1, \ + .in_bit =3D -1, \ + .out_bit =3D 0, \ + .intr_enable_bit =3D -1, \ + .intr_status_bit =3D -1, \ + .intr_target_bit =3D -1, \ + .intr_raw_status_bit =3D -1, \ + .intr_polarity_bit =3D -1, \ + .intr_detection_bit =3D -1, \ + .intr_detection_width =3D -1, \ + } + +static const struct pinctrl_pin_desc eliza_pins[] =3D { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "UFS_RESET"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] =3D { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); + +static const unsigned int ufs_reset_pins[] =3D { 185 }; + +enum eliza_functions { + msm_mux_gpio, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ext_mclk0, + msm_mux_audio_ref_clk, + msm_mux_cam_mclk, + msm_mux_cci_async_in, + msm_mux_cci_i2c_scl, + msm_mux_cci_i2c_sda, + msm_mux_cci_timer, + msm_mux_coex_uart1_rx, + msm_mux_coex_uart1_tx, + msm_mux_coex_uart2_rx, + msm_mux_coex_uart2_tx, + msm_mux_dbg_out_clk, + msm_mux_ddr_bist_complete, + msm_mux_ddr_bist_fail, + msm_mux_ddr_bist_start, + msm_mux_ddr_bist_stop, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_dp0_hot, + msm_mux_egpio, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gnss_adc0, + msm_mux_gnss_adc1, + msm_mux_hdmi_ddc_scl, + msm_mux_hdmi_ddc_sda, + msm_mux_hdmi_dtest0, + msm_mux_hdmi_dtest1, + msm_mux_hdmi_hot_plug, + msm_mux_hdmi_pixel_clk, + msm_mux_hdmi_rcv_det, + msm_mux_hdmi_tx_cec, + msm_mux_host2wlan_sol, + msm_mux_i2s0_data0, + msm_mux_i2s0_data1, + msm_mux_i2s0_sck, + msm_mux_i2s0_ws, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_mdp_esync0_out, + msm_mux_mdp_esync1_out, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0_out, + msm_mux_mdp_vsync11_out, + msm_mux_mdp_vsync1_out, + msm_mux_mdp_vsync2_out, + msm_mux_mdp_vsync3_out, + msm_mux_mdp_vsync_e, + msm_mux_nav_gpio0, + msm_mux_nav_gpio1, + msm_mux_nav_gpio2, + msm_mux_nav_gpio3, + msm_mux_pcie0_clk_req_n, + msm_mux_pcie1_clk_req_n, + msm_mux_phase_flag, + msm_mux_pll_bist_sync, + msm_mux_pll_clk_aux, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio_traceclk, + msm_mux_qdss_gpio_tracectl, + msm_mux_qdss_gpio_tracedata, + msm_mux_qlink_big_enable, + msm_mux_qlink_big_request, + msm_mux_qlink_little_enable, + msm_mux_qlink_little_request, + msm_mux_qlink_wmss, + msm_mux_qspi0, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup1_se0, + msm_mux_qup1_se1, + msm_mux_qup1_se2, + msm_mux_qup1_se3, + msm_mux_qup1_se4, + msm_mux_qup1_se5, + msm_mux_qup1_se6, + msm_mux_qup1_se7, + msm_mux_qup2_se0, + msm_mux_qup2_se1, + msm_mux_qup2_se2, + msm_mux_qup2_se3, + msm_mux_qup2_se4, + msm_mux_qup2_se5, + msm_mux_qup2_se6, + msm_mux_qup2_se7, + msm_mux_resout_gpio, + msm_mux_sd_write_protect, + msm_mux_sdc1, + msm_mux_sdc2, + msm_mux_sdc2_fb_clk, + msm_mux_tb_trig_sdc1, + msm_mux_tb_trig_sdc2, + msm_mux_tmess_prng0, + msm_mux_tmess_prng1, + msm_mux_tmess_prng2, + msm_mux_tmess_prng3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsense_pwm3, + msm_mux_tsense_pwm4, + msm_mux_uim0_clk, + msm_mux_uim0_data, + msm_mux_uim0_present, + msm_mux_uim0_reset, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_usb0_hs, + msm_mux_usb_phy, + msm_mux_vfr_0, + msm_mux_vfr_1, + msm_mux_vsense_trigger_mirnat, + msm_mux_wcn_sw_ctrl, + msm_mux__, +}; + +static const char *const gpio_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", + "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", + "gpio40", "gpio42", "gpio44", "gpio45", "gpio46", "gpio47", + "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", + "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", + "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", + "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", + "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", + "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", + "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", + "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", + "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", + "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", + "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", + "gpio133", "gpio134", "gpio135", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio184", +}; + +static const char *const aoss_cti_groups[] =3D { + "gpio0", "gpio1", "gpio26", "gpio27", +}; + +static const char *const atest_char_groups[] =3D { + "gpio71", "gpio70", "gpio72", "gpio74", "gpio73", +}; + +static const char *const atest_usb_groups[] =3D { + "gpio55", "gpio54", +}; + +static const char *const audio_ext_mclk0_groups[] =3D { + "gpio69", +}; + +static const char *const audio_ref_clk_groups[] =3D { + "gpio32", +}; + +static const char *const cam_mclk_groups[] =3D { + "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", +}; + +static const char *const cci_async_in_groups[] =3D { + "gpio115", "gpio31", "gpio30", +}; + +static const char *const cci_i2c_scl_groups[] =3D { + "gpio71", "gpio73", "gpio75", "gpio77", +}; + +static const char *const cci_i2c_sda_groups[] =3D { + "gpio70", "gpio72", "gpio74", "gpio76", +}; + +static const char *const cci_timer_groups[] =3D { + "gpio76", "gpio63", "gpio125", "gpio126", "gpio127", +}; + +static const char *const coex_uart1_rx_groups[] =3D { + "gpio112", +}; + +static const char *const coex_uart1_tx_groups[] =3D { + "gpio111", +}; + +static const char *const coex_uart2_rx_groups[] =3D { + "gpio116", +}; + +static const char *const coex_uart2_tx_groups[] =3D { + "gpio100", +}; + +static const char *const dbg_out_clk_groups[] =3D { + "gpio81", +}; + +static const char *const ddr_bist_complete_groups[] =3D { + "gpio52", +}; + +static const char *const ddr_bist_fail_groups[] =3D { + "gpio147", +}; + +static const char *const ddr_bist_start_groups[] =3D { + "gpio34", +}; + +static const char *const ddr_bist_stop_groups[] =3D { + "gpio53", +}; + +static const char *const ddr_pxi0_groups[] =3D { + "gpio54", "gpio55", +}; + +static const char *const ddr_pxi1_groups[] =3D { + "gpio40", "gpio42", +}; + +static const char *const dp0_hot_groups[] =3D { + "gpio55", +}; + +static const char *const egpio_groups[] =3D { + "gpio28", "gpio29", "gpio30", "gpio31", "gpio138", "gpio139", + "gpio140", "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", + "gpio146", "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", + "gpio152", "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", + "gpio158", "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", + "gpio164", "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", + "gpio170", "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", + "gpio176", "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", + "gpio182", "gpio184", +}; + +static const char *const gcc_gp1_groups[] =3D { + "gpio27", "gpio53", +}; + +static const char *const gcc_gp2_groups[] =3D { + "gpio32", "gpio35", +}; + +static const char *const gcc_gp3_groups[] =3D { + "gpio30", "gpio33", +}; + +static const char *const gnss_adc0_groups[] =3D { + "gpio42", "gpio55", +}; + +static const char *const gnss_adc1_groups[] =3D { + "gpio40", "gpio54", +}; + +static const char *const hdmi_ddc_scl_groups[] =3D { + "gpio6", +}; + +static const char *const hdmi_ddc_sda_groups[] =3D { + "gpio7", +}; + +static const char *const hdmi_dtest0_groups[] =3D { + "gpio132", +}; + +static const char *const hdmi_dtest1_groups[] =3D { + "gpio133", +}; + +static const char *const hdmi_hot_plug_groups[] =3D { + "gpio47", +}; + +static const char *const hdmi_pixel_clk_groups[] =3D { + "gpio18", +}; + +static const char *const hdmi_rcv_det_groups[] =3D { + "gpio19", +}; + +static const char *const hdmi_tx_cec_groups[] =3D { + "gpio46", +}; + +static const char *const host2wlan_sol_groups[] =3D { + "gpio33", +}; + +static const char *const i2s0_data0_groups[] =3D { + "gpio64", +}; + +static const char *const i2s0_data1_groups[] =3D { + "gpio63", +}; + +static const char *const i2s0_sck_groups[] =3D { + "gpio60", +}; + +static const char *const i2s0_ws_groups[] =3D { + "gpio61", +}; + +static const char *const ibi_i3c_groups[] =3D { + "gpio0", "gpio1", "gpio4", "gpio5", "gpio12", "gpio13", + "gpio28", "gpio29", "gpio32", "gpio33", "gpio36", "gpio37", +}; + +static const char *const jitter_bist_groups[] =3D { + "gpio77", +}; + +static const char *const mdp_esync0_out_groups[] =3D { + "gpio13", +}; + +static const char *const mdp_esync1_out_groups[] =3D { + "gpio12", +}; + +static const char *const mdp_vsync_groups[] =3D { + "gpio16", "gpio17", "gpio79", "gpio100", "gpio120", "gpio121", +}; + +static const char *const mdp_vsync0_out_groups[] =3D { + "gpio17", +}; + +static const char *const mdp_vsync11_out_groups[] =3D { + "gpio27", +}; + +static const char *const mdp_vsync1_out_groups[] =3D { + "gpio17", +}; + +static const char *const mdp_vsync2_out_groups[] =3D { + "gpio16", +}; + +static const char *const mdp_vsync3_out_groups[] =3D { + "gpio16", +}; + +static const char *const mdp_vsync_e_groups[] =3D { + "gpio13", +}; + +static const char *const nav_gpio0_groups[] =3D { + "gpio119", +}; + +static const char *const nav_gpio1_groups[] =3D { + "gpio117", +}; + +static const char *const nav_gpio2_groups[] =3D { + "gpio118", +}; + +static const char *const nav_gpio3_groups[] =3D { + "gpio113", +}; + +static const char *const pcie0_clk_req_n_groups[] =3D { + "gpio80", +}; + +static const char *const pcie1_clk_req_n_groups[] =3D { + "gpio52", +}; + +static const char *const phase_flag_groups[] =3D { + "gpio71", "gpio70", "gpio174", "gpio175", "gpio172", "gpio171", + "gpio170", "gpio169", "gpio168", "gpio167", "gpio166", "gpio165", + "gpio182", "gpio164", "gpio163", "gpio162", "gpio161", "gpio160", + "gpio159", "gpio158", "gpio157", "gpio80", "gpio78", "gpio181", + "gpio76", "gpio75", "gpio180", "gpio179", "gpio178", "gpio177", + "gpio176", "gpio173", +}; + +static const char *const pll_bist_sync_groups[] =3D { + "gpio184", +}; + +static const char *const pll_clk_aux_groups[] =3D { + "gpio135", +}; + +static const char *const prng_rosc0_groups[] =3D { + "gpio67", +}; + +static const char *const prng_rosc1_groups[] =3D { + "gpio69", +}; + +static const char *const prng_rosc2_groups[] =3D { + "gpio76", +}; + +static const char *const prng_rosc3_groups[] =3D { + "gpio74", +}; + +static const char *const qdss_cti_groups[] =3D { + "gpio18", "gpio19", "gpio32", "gpio73", + "gpio74", "gpio154", "gpio176", "gpio184", +}; + +static const char *const qdss_gpio_traceclk_groups[] =3D { + "gpio54", "gpio147", +}; + +static const char *const qdss_gpio_tracectl_groups[] =3D { + "gpio72", "gpio144", +}; + +static const char *const qdss_gpio_tracedata_groups[] =3D { + "gpio30", "gpio31", "gpio34", "gpio35", "gpio40", "gpio42", + "gpio52", "gpio53", "gpio65", "gpio66", "gpio67", "gpio114", + "gpio132", "gpio133", "gpio134", "gpio135", "gpio145", "gpio146", + "gpio155", "gpio156", "gpio163", "gpio164", "gpio167", "gpio168", + "gpio169", "gpio170", "gpio178", "gpio179", "gpio180", "gpio181", + "gpio182", +}; + +static const char *const qlink_big_enable_groups[] =3D { + "gpio96", +}; + +static const char *const qlink_big_request_groups[] =3D { + "gpio95", +}; + +static const char *const qlink_little_enable_groups[] =3D { + "gpio93", +}; + +static const char *const qlink_little_request_groups[] =3D { + "gpio92", +}; + +static const char *const qlink_wmss_groups[] =3D { + "gpio94", +}; + +static const char *const qspi0_groups[] =3D { + "gpio79", "gpio116", "gpio115", "gpio97", "gpio98", +}; + +static const char *const qspi_clk_groups[] =3D { + "gpio99", +}; + +static const char *const qspi_cs_groups[] =3D { + "gpio100", +}; + +static const char *const qup1_se0_groups[] =3D { + "gpio28", "gpio29", "gpio30", "gpio31", +}; + +static const char *const qup1_se1_groups[] =3D { + "gpio32", "gpio33", "gpio34", "gpio35", +}; + +static const char *const qup1_se2_groups[] =3D { + "gpio52", "gpio53", "gpio54", "gpio52", "gpio55", "gpio53", "gpio40", "gp= io42", "gpio30", +}; + +static const char *const qup1_se3_groups[] =3D { + "gpio44", "gpio45", "gpio46", "gpio47", +}; + +static const char *const qup1_se4_groups[] =3D { + "gpio36", "gpio37", "gpio37", "gpio36", +}; + +static const char *const qup1_se5_groups[] =3D { + "gpio132", "gpio133", "gpio134", "gpio135", "gpio34", "gpio35", +}; + +static const char *const qup1_se6_groups[] =3D { + "gpio40", "gpio42", "gpio54", "gpio42", "gpio40", "gpio55", +}; + +static const char *const qup1_se7_groups[] =3D { + "gpio81", "gpio78", "gpio80", "gpio114", "gpio114", "gpio78", +}; + +static const char *const qup2_se0_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char *const qup2_se1_groups[] =3D { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char *const qup2_se2_groups[] =3D { + "gpio8", "gpio9", "gpio10", "gpio11", "gpio16", "gpio17", "gpio18", +}; + +static const char *const qup2_se3_groups[] =3D { + "gpio79", "gpio116", "gpio97", "gpio100", "gpio100", "gpio116", +}; + +static const char *const qup2_se4_groups[] =3D { + "gpio12", "gpio13", "gpio26", "gpio27", +}; + +static const char *const qup2_se5_groups[] =3D { + "gpio16", "gpio17", "gpio18", "gpio19", +}; + +static const char *const qup2_se6_groups[] =3D { + "gpio20", "gpio21", "gpio22", "gpio23", +}; + +static const char *const qup2_se7_groups[] =3D { + "gpio27", "gpio26", "gpio13", "gpio12", +}; + +static const char *const resout_gpio_groups[] =3D { + "gpio63", + "gpio69", + "gpio175", +}; + +static const char *const sd_write_protect_groups[] =3D { + "gpio57", +}; + +static const char *const sdc1_groups[] =3D { + "gpio121", "gpio123", "gpio124", "gpio125", + "gpio126", "gpio127", "gpio128", "gpio129", + "gpio130", "gpio131", "gpio120", +}; + +static const char *const sdc2_groups[] =3D { + "gpio38", "gpio39", "gpio48", "gpio49", + "gpio51", "gpio62", +}; + +static const char *const sdc2_fb_clk_groups[] =3D { + "gpio50", +}; + +static const char *const tb_trig_sdc1_groups[] =3D { + "gpio34", +}; + +static const char *const tb_trig_sdc2_groups[] =3D { + "gpio35", +}; + +static const char *const tmess_prng0_groups[] =3D { + "gpio73", +}; + +static const char *const tmess_prng1_groups[] =3D { + "gpio72", +}; + +static const char *const tmess_prng2_groups[] =3D { + "gpio70", +}; + +static const char *const tmess_prng3_groups[] =3D { + "gpio71", +}; + +static const char *const tsense_pwm1_groups[] =3D { + "gpio56", +}; + +static const char *const tsense_pwm2_groups[] =3D { + "gpio56", +}; + +static const char *const tsense_pwm3_groups[] =3D { + "gpio56", +}; + +static const char *const tsense_pwm4_groups[] =3D { + "gpio56", +}; + +static const char *const uim0_clk_groups[] =3D { + "gpio85", +}; + +static const char *const uim0_data_groups[] =3D { + "gpio84", +}; + +static const char *const uim0_present_groups[] =3D { + "gpio87", +}; + +static const char *const uim0_reset_groups[] =3D { + "gpio86", +}; + +static const char *const uim1_clk_groups[] =3D { + "gpio98", "gpio89", +}; + +static const char *const uim1_data_groups[] =3D { + "gpio97", "gpio88", +}; + +static const char *const uim1_present_groups[] =3D { + "gpio100", "gpio91", +}; + +static const char *const uim1_reset_groups[] =3D { + "gpio99", "gpio90", +}; + +static const char *const usb0_hs_groups[] =3D { + "gpio56", +}; + +static const char *const usb_phy_groups[] =3D { + "gpio122", +}; + +static const char *const vfr_0_groups[] =3D { + "gpio63", +}; + +static const char *const vfr_1_groups[] =3D { + "gpio117", +}; + +static const char *const vsense_trigger_mirnat_groups[] =3D { + "gpio52", +}; + +static const char *const wcn_sw_ctrl_groups[] =3D { + "gpio81", +}; + +static const struct pinfunction eliza_functions[] =3D { + MSM_GPIO_PIN_FUNCTION(gpio), + MSM_PIN_FUNCTION(aoss_cti), + MSM_PIN_FUNCTION(atest_char), + MSM_PIN_FUNCTION(atest_usb), + MSM_PIN_FUNCTION(audio_ext_mclk0), + MSM_PIN_FUNCTION(audio_ref_clk), + MSM_PIN_FUNCTION(cam_mclk), + MSM_PIN_FUNCTION(cci_async_in), + MSM_PIN_FUNCTION(cci_i2c_scl), + MSM_PIN_FUNCTION(cci_i2c_sda), + MSM_PIN_FUNCTION(cci_timer), + MSM_PIN_FUNCTION(coex_uart1_rx), + MSM_PIN_FUNCTION(coex_uart1_tx), + MSM_PIN_FUNCTION(coex_uart2_rx), + MSM_PIN_FUNCTION(coex_uart2_tx), + MSM_PIN_FUNCTION(dbg_out_clk), + MSM_PIN_FUNCTION(ddr_bist_complete), + MSM_PIN_FUNCTION(ddr_bist_fail), + MSM_PIN_FUNCTION(ddr_bist_start), + MSM_PIN_FUNCTION(ddr_bist_stop), + MSM_PIN_FUNCTION(ddr_pxi0), + MSM_PIN_FUNCTION(ddr_pxi1), + MSM_PIN_FUNCTION(dp0_hot), + MSM_PIN_FUNCTION(egpio), + MSM_PIN_FUNCTION(gcc_gp1), + MSM_PIN_FUNCTION(gcc_gp2), + MSM_PIN_FUNCTION(gcc_gp3), + MSM_PIN_FUNCTION(gnss_adc0), + MSM_PIN_FUNCTION(gnss_adc1), + MSM_PIN_FUNCTION(hdmi_ddc_scl), + MSM_PIN_FUNCTION(hdmi_ddc_sda), + MSM_PIN_FUNCTION(hdmi_dtest0), + MSM_PIN_FUNCTION(hdmi_dtest1), + MSM_PIN_FUNCTION(hdmi_hot_plug), + MSM_PIN_FUNCTION(hdmi_pixel_clk), + MSM_PIN_FUNCTION(hdmi_rcv_det), + MSM_PIN_FUNCTION(hdmi_tx_cec), + MSM_PIN_FUNCTION(host2wlan_sol), + MSM_PIN_FUNCTION(i2s0_data0), + MSM_PIN_FUNCTION(i2s0_data1), + MSM_PIN_FUNCTION(i2s0_sck), + MSM_PIN_FUNCTION(i2s0_ws), + MSM_PIN_FUNCTION(ibi_i3c), + MSM_PIN_FUNCTION(jitter_bist), + MSM_PIN_FUNCTION(mdp_esync0_out), + MSM_PIN_FUNCTION(mdp_esync1_out), + MSM_PIN_FUNCTION(mdp_vsync), + MSM_PIN_FUNCTION(mdp_vsync0_out), + MSM_PIN_FUNCTION(mdp_vsync11_out), + MSM_PIN_FUNCTION(mdp_vsync1_out), + MSM_PIN_FUNCTION(mdp_vsync2_out), + MSM_PIN_FUNCTION(mdp_vsync3_out), + MSM_PIN_FUNCTION(mdp_vsync_e), + MSM_PIN_FUNCTION(nav_gpio0), + MSM_PIN_FUNCTION(nav_gpio1), + MSM_PIN_FUNCTION(nav_gpio2), + MSM_PIN_FUNCTION(nav_gpio3), + MSM_PIN_FUNCTION(pcie0_clk_req_n), + MSM_PIN_FUNCTION(pcie1_clk_req_n), + MSM_PIN_FUNCTION(phase_flag), + MSM_PIN_FUNCTION(pll_bist_sync), + MSM_PIN_FUNCTION(pll_clk_aux), + MSM_PIN_FUNCTION(prng_rosc0), + MSM_PIN_FUNCTION(prng_rosc1), + MSM_PIN_FUNCTION(prng_rosc2), + MSM_PIN_FUNCTION(prng_rosc3), + MSM_PIN_FUNCTION(qdss_cti), + MSM_PIN_FUNCTION(qdss_gpio_traceclk), + MSM_PIN_FUNCTION(qdss_gpio_tracectl), + MSM_PIN_FUNCTION(qdss_gpio_tracedata), + MSM_PIN_FUNCTION(qlink_big_enable), + MSM_PIN_FUNCTION(qlink_big_request), + MSM_PIN_FUNCTION(qlink_little_enable), + MSM_PIN_FUNCTION(qlink_little_request), + MSM_PIN_FUNCTION(qlink_wmss), + MSM_PIN_FUNCTION(qspi0), + MSM_PIN_FUNCTION(qspi_clk), + MSM_PIN_FUNCTION(qspi_cs), + MSM_PIN_FUNCTION(qup1_se0), + MSM_PIN_FUNCTION(qup1_se1), + MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se3), + MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se5), + MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup2_se0), + MSM_PIN_FUNCTION(qup2_se1), + MSM_PIN_FUNCTION(qup2_se2), + MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se4), + MSM_PIN_FUNCTION(qup2_se5), + MSM_PIN_FUNCTION(qup2_se6), + MSM_PIN_FUNCTION(qup2_se7), + MSM_PIN_FUNCTION(resout_gpio), + MSM_PIN_FUNCTION(sd_write_protect), + MSM_PIN_FUNCTION(sdc1), + MSM_PIN_FUNCTION(sdc2), + MSM_PIN_FUNCTION(sdc2_fb_clk), + MSM_PIN_FUNCTION(tb_trig_sdc1), + MSM_PIN_FUNCTION(tb_trig_sdc2), + MSM_PIN_FUNCTION(tmess_prng0), + MSM_PIN_FUNCTION(tmess_prng1), + MSM_PIN_FUNCTION(tmess_prng2), + MSM_PIN_FUNCTION(tmess_prng3), + MSM_PIN_FUNCTION(tsense_pwm1), + MSM_PIN_FUNCTION(tsense_pwm2), + MSM_PIN_FUNCTION(tsense_pwm3), + MSM_PIN_FUNCTION(tsense_pwm4), + MSM_PIN_FUNCTION(uim0_clk), + MSM_PIN_FUNCTION(uim0_data), + MSM_PIN_FUNCTION(uim0_present), + MSM_PIN_FUNCTION(uim0_reset), + MSM_PIN_FUNCTION(uim1_clk), + MSM_PIN_FUNCTION(uim1_data), + MSM_PIN_FUNCTION(uim1_present), + MSM_PIN_FUNCTION(uim1_reset), + MSM_PIN_FUNCTION(usb0_hs), + MSM_PIN_FUNCTION(usb_phy), + MSM_PIN_FUNCTION(vfr_0), + MSM_PIN_FUNCTION(vfr_1), + MSM_PIN_FUNCTION(vsense_trigger_mirnat), + MSM_PIN_FUNCTION(wcn_sw_ctrl), +}; + +/* Every pin is maintained as a single group, and missing or non-existing = pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup eliza_groups[] =3D { + [0] =3D PINGROUP(0, qup2_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _), + [1] =3D PINGROUP(1, qup2_se0, ibi_i3c, aoss_cti, _, _, _, _, _, _, _, _), + [2] =3D PINGROUP(2, qup2_se0, _, _, _, _, _, _, _, _, _, _), + [3] =3D PINGROUP(3, qup2_se0, _, _, _, _, _, _, _, _, _, _), + [4] =3D PINGROUP(4, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [5] =3D PINGROUP(5, qup2_se1, ibi_i3c, _, _, _, _, _, _, _, _, _), + [6] =3D PINGROUP(6, qup2_se1, hdmi_ddc_scl, _, _, _, _, _, _, _, _, _), + [7] =3D PINGROUP(7, qup2_se1, hdmi_ddc_sda, _, _, _, _, _, _, _, _, _), + [8] =3D PINGROUP(8, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [9] =3D PINGROUP(9, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [10] =3D PINGROUP(10, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [11] =3D PINGROUP(11, qup2_se2, _, _, _, _, _, _, _, _, _, _), + [12] =3D PINGROUP(12, qup2_se4, ibi_i3c, mdp_esync1_out, qup2_se7, _, _, = _, _, _, _, _), + [13] =3D PINGROUP(13, qup2_se4, ibi_i3c, mdp_vsync_e, mdp_esync0_out, qup= 2_se7, _, _, _, _, _, _), + [14] =3D PINGROUP(14, _, _, _, _, _, _, _, _, _, _, _), + [15] =3D PINGROUP(15, _, _, _, _, _, _, _, _, _, _, _), + [16] =3D PINGROUP(16, qup2_se5, qup2_se2, mdp_vsync, mdp_vsync2_out, mdp_= vsync3_out, _, _, _, _, _, _), + [17] =3D PINGROUP(17, qup2_se5, qup2_se2, mdp_vsync, mdp_vsync0_out, mdp_= vsync1_out, _, _, _, _, _, _), + [18] =3D PINGROUP(18, qup2_se5, qup2_se2, hdmi_pixel_clk, _, qdss_cti, _,= _, _, _, _, _), + [19] =3D PINGROUP(19, qup2_se5, hdmi_rcv_det, _, qdss_cti, _, _, _, _, _,= _, _), + [20] =3D PINGROUP(20, qup2_se6, _, _, _, _, _, _, _, _, _, _), + [21] =3D PINGROUP(21, qup2_se6, _, _, _, _, _, _, _, _, _, _), + [22] =3D PINGROUP(22, qup2_se6, _, _, _, _, _, _, _, _, _, _), + [23] =3D PINGROUP(23, qup2_se6, _, _, _, _, _, _, _, _, _, _), + [24] =3D PINGROUP(24, _, _, _, _, _, _, _, _, _, _, _), + [25] =3D PINGROUP(25, _, _, _, _, _, _, _, _, _, _, _), + [26] =3D PINGROUP(26, qup2_se4, aoss_cti, qup2_se7, _, _, _, _, _, _, _, = _), + [27] =3D PINGROUP(27, qup2_se4, aoss_cti, mdp_vsync11_out, qup2_se7, gcc_= gp1, _, _, _, _, _, _), + [28] =3D PINGROUP(28, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [29] =3D PINGROUP(29, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), + [30] =3D PINGROUP(30, qup1_se0, qup1_se2, cci_async_in, gcc_gp3, qdss_gpi= o_tracedata, _, _, _, _, _, egpio), + [31] =3D PINGROUP(31, qup1_se0, cci_async_in, qdss_gpio_tracedata, _, _, = _, _, _, _, _, egpio), + [32] =3D PINGROUP(32, qup1_se1, ibi_i3c, audio_ref_clk, gcc_gp2, qdss_cti= , _, _, _, _, _, _), + [33] =3D PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _,= _, _, _, _), + [34] =3D PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, q= dss_gpio_tracedata, _, _, _, _, _, _), + [35] =3D PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpi= o_tracedata, _, _, _, _, _, _), + [36] =3D PINGROUP(36, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _= ), + [37] =3D PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _= ), + [38] =3D PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _), + [39] =3D PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _), + [40] =3D PINGROUP(40, qup1_se6, qup1_se2, qup1_se6, _, qdss_gpio_tracedat= a, gnss_adc1, ddr_pxi1, _, _, _, _), + [41] =3D PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _), + [42] =3D PINGROUP(42, qup1_se6, qup1_se2, qup1_se6, qdss_gpio_tracedata, = gnss_adc0, ddr_pxi1, _, _, _, _, _), + [43] =3D PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _), + [44] =3D PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _), + [45] =3D PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _), + [46] =3D PINGROUP(46, qup1_se3, hdmi_tx_cec, _, _, _, _, _, _, _, _, _), + [47] =3D PINGROUP(47, qup1_se3, hdmi_hot_plug, _, _, _, _, _, _, _, _, _), + [48] =3D PINGROUP(48, _, _, _, _, _, _, _, _, _, _, _), + [49] =3D PINGROUP(49, _, _, _, _, _, _, _, _, _, _, _), + [50] =3D PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _), + [51] =3D PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _), + [52] =3D PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_compl= ete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _), + [53] =3D PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss= _gpio_tracedata, _, _, _, _, _), + [54] =3D PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc1,= atest_usb, ddr_pxi0, _, _, _, _, _), + [55] =3D PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_us= b, ddr_pxi0, _, _, _, _), + [56] =3D PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tse= nse_pwm4, _, _, _, _, _, _), + [57] =3D PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _), + [58] =3D PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _), + [59] =3D PINGROUP(59, _, _, _, _, _, _, _, _, _, _, _), + [60] =3D PINGROUP(60, i2s0_sck, _, _, _, _, _, _, _, _, _, _), + [61] =3D PINGROUP(61, i2s0_ws, _, _, _, _, _, _, _, _, _, _), + [62] =3D PINGROUP(62, _, _, _, _, _, _, _, _, _, _, _), + [63] =3D PINGROUP(63, resout_gpio, i2s0_data1, cci_timer, vfr_0, _, _, _,= _, _, _, _), + [64] =3D PINGROUP(64, i2s0_data0, _, _, _, _, _, _, _, _, _, _), + [65] =3D PINGROUP(65, cam_mclk, _, qdss_gpio_tracedata, _, _, _, _, _, _,= _, _), + [66] =3D PINGROUP(66, cam_mclk, _, qdss_gpio_tracedata, _, _, _, _, _, _,= _, _), + [67] =3D PINGROUP(67, cam_mclk, prng_rosc0, _, qdss_gpio_tracedata, _, _,= _, _, _, _, _), + [68] =3D PINGROUP(68, cam_mclk, _, _, _, _, _, _, _, _, _, _), + [69] =3D PINGROUP(69, cam_mclk, audio_ext_mclk0, resout_gpio, prng_rosc1,= _, _, _, _, _, _, _), + [70] =3D PINGROUP(70, cci_i2c_sda, tmess_prng2, _, phase_flag, atest_char= , _, _, _, _, _, _), + [71] =3D PINGROUP(71, cci_i2c_scl, tmess_prng3, _, phase_flag, atest_char= , _, _, _, _, _, _), + [72] =3D PINGROUP(72, cci_i2c_sda, tmess_prng1, qdss_gpio_tracedata, ates= t_char, _, _, _, _, _, _, _), + [73] =3D PINGROUP(73, cci_i2c_scl, tmess_prng0, qdss_cti, atest_char, _, = _, _, _, _, _, _), + [74] =3D PINGROUP(74, cci_i2c_sda, prng_rosc3, qdss_cti, atest_char, _, _= , _, _, _, _, _), + [75] =3D PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _), + [76] =3D PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, = _, _, _, _, _, _), + [77] =3D PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _= ), + [78] =3D PINGROUP(78, qup1_se7, qup1_se7, _, phase_flag, _, _, _, _, _, _= , _), + [79] =3D PINGROUP(79, qspi0, mdp_vsync, qup2_se3, _, _, _, _, _, _, _, _), + [80] =3D PINGROUP(80, pcie0_clk_req_n, qup1_se7, _, phase_flag, _, _, _, = _, _, _, _), + [81] =3D PINGROUP(81, wcn_sw_ctrl, qup1_se7, dbg_out_clk, _, _, _, _, _, = _, _, _), + [82] =3D PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _), + [83] =3D PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _), + [84] =3D PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _), + [85] =3D PINGROUP(85, uim0_clk, _, _, _, _, _, _, _, _, _, _), + [86] =3D PINGROUP(86, uim0_reset, _, _, _, _, _, _, _, _, _, _), + [87] =3D PINGROUP(87, uim0_present, _, _, _, _, _, _, _, _, _, _), + [88] =3D PINGROUP(88, uim1_data, _, _, _, _, _, _, _, _, _, _), + [89] =3D PINGROUP(89, uim1_clk, _, _, _, _, _, _, _, _, _, _), + [90] =3D PINGROUP(90, uim1_reset, _, _, _, _, _, _, _, _, _, _), + [91] =3D PINGROUP(91, uim1_present, _, _, _, _, _, _, _, _, _, _), + [92] =3D PINGROUP(92, qlink_little_request, _, _, _, _, _, _, _, _, _, _), + [93] =3D PINGROUP(93, qlink_little_enable, _, _, _, _, _, _, _, _, _, _), + [94] =3D PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _), + [95] =3D PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _), + [96] =3D PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _), + [97] =3D PINGROUP(97, uim1_data, qspi0, qup2_se3, _, _, _, _, _, _, _, _), + [98] =3D PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _), + [99] =3D PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _), + [100] =3D PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup= 2_se3, mdp_vsync, _, _, _, _, _), + [101] =3D PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _), + [102] =3D PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _), + [103] =3D PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _), + [104] =3D PINGROUP(104, _, _, _, _, _, _, _, _, _, _, _), + [105] =3D PINGROUP(105, _, _, _, _, _, _, _, _, _, _, _), + [106] =3D PINGROUP(106, _, _, _, _, _, _, _, _, _, _, _), + [107] =3D PINGROUP(107, _, _, _, _, _, _, _, _, _, _, _), + [108] =3D PINGROUP(108, _, _, _, _, _, _, _, _, _, _, _), + [109] =3D PINGROUP(109, _, _, _, _, _, _, _, _, _, _, _), + [110] =3D PINGROUP(110, _, _, _, _, _, _, _, _, _, _, _), + [111] =3D PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _), + [112] =3D PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _), + [113] =3D PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _), + [114] =3D PINGROUP(114, qup1_se7, qup1_se7, _, qdss_gpio_tracedata, _, _,= _, _, _, _, _), + [115] =3D PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _), + [116] =3D PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3, _, _, _= , _, _, _, _), + [117] =3D PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _), + [118] =3D PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _), + [119] =3D PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _), + [120] =3D PINGROUP(120, sdc1, mdp_vsync, _, _, _, _, _, _, _, _, _), + [121] =3D PINGROUP(121, sdc1, mdp_vsync, _, _, _, _, _, _, _, _, _), + [122] =3D PINGROUP(122, usb_phy, _, _, _, _, _, _, _, _, _, _), + [123] =3D PINGROUP(123, sdc1, _, _, _, _, _, _, _, _, _, _), + [124] =3D PINGROUP(124, sdc1, _, _, _, _, _, _, _, _, _, _), + [125] =3D PINGROUP(125, sdc1, cci_timer, _, _, _, _, _, _, _, _, _), + [126] =3D PINGROUP(126, sdc1, cci_timer, _, _, _, _, _, _, _, _, _), + [127] =3D PINGROUP(127, sdc1, cci_timer, _, _, _, _, _, _, _, _, _), + [128] =3D PINGROUP(128, sdc1, _, _, _, _, _, _, _, _, _, _), + [129] =3D PINGROUP(129, sdc1, _, _, _, _, _, _, _, _, _, _), + [130] =3D PINGROUP(130, sdc1, _, _, _, _, _, _, _, _, _, _), + [131] =3D PINGROUP(131, sdc1, _, _, _, _, _, _, _, _, _, _), + [132] =3D PINGROUP(132, qup1_se5, _, qdss_gpio_tracedata, hdmi_dtest0, _,= _, _, _, _, _, _), + [133] =3D PINGROUP(133, qup1_se5, _, qdss_gpio_tracedata, hdmi_dtest1, _,= _, _, _, _, _, _), + [134] =3D PINGROUP(134, qup1_se5, qdss_gpio_tracedata, _, _, _, _, _, _, = _, _, _), + [135] =3D PINGROUP(135, qup1_se5, _, pll_clk_aux, qdss_gpio_tracedata, _,= _, _, _, _, _, _), + [136] =3D PINGROUP(136, _, _, _, _, _, _, _, _, _, _, _), + [137] =3D PINGROUP(137, _, _, _, _, _, _, _, _, _, _, _), + [138] =3D PINGROUP(138, _, _, _, _, _, _, _, _, _, _, egpio), + [139] =3D PINGROUP(139, _, _, _, _, _, _, _, _, _, _, egpio), + [140] =3D PINGROUP(140, _, _, _, _, _, _, _, _, _, _, egpio), + [141] =3D PINGROUP(141, _, _, _, _, _, _, _, _, _, _, egpio), + [142] =3D PINGROUP(142, _, _, _, _, _, _, _, _, _, _, egpio), + [143] =3D PINGROUP(143, _, _, _, _, _, _, _, _, _, _, egpio), + [144] =3D PINGROUP(144, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, e= gpio), + [145] =3D PINGROUP(145, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, _, e= gpio), + [146] =3D PINGROUP(146, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, e= gpio), + [147] =3D PINGROUP(147, ddr_bist_fail, _, qdss_gpio_tracedata, _, _, _, _= , _, _, _, egpio), + [148] =3D PINGROUP(148, _, _, _, _, _, _, _, _, _, _, egpio), + [149] =3D PINGROUP(149, _, _, _, _, _, _, _, _, _, _, egpio), + [150] =3D PINGROUP(150, _, _, _, _, _, _, _, _, _, _, egpio), + [151] =3D PINGROUP(151, _, _, _, _, _, _, _, _, _, _, egpio), + [152] =3D PINGROUP(152, _, _, _, _, _, _, _, _, _, _, egpio), + [153] =3D PINGROUP(153, _, _, _, _, _, _, _, _, _, _, egpio), + [154] =3D PINGROUP(154, qdss_cti, _, _, _, _, _, _, _, _, _, egpio), + [155] =3D PINGROUP(155, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, e= gpio), + [156] =3D PINGROUP(156, _, qdss_gpio_tracedata, _, _, _, _, _, _, _, _, e= gpio), + [157] =3D PINGROUP(157, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [158] =3D PINGROUP(158, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [159] =3D PINGROUP(159, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [160] =3D PINGROUP(160, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [161] =3D PINGROUP(161, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [162] =3D PINGROUP(162, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [163] =3D PINGROUP(163, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _= , _, _, egpio), + [164] =3D PINGROUP(164, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _= , _, _, egpio), + [165] =3D PINGROUP(165, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [166] =3D PINGROUP(166, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [167] =3D PINGROUP(167, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _= , _, _, egpio), + [168] =3D PINGROUP(168, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _= , _, _, egpio), + [169] =3D PINGROUP(169, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _= , _, _, egpio), + [170] =3D PINGROUP(170, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _= , _, _, egpio), + [171] =3D PINGROUP(171, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [172] =3D PINGROUP(172, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [173] =3D PINGROUP(173, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [174] =3D PINGROUP(174, _, phase_flag, _, _, _, _, _, _, _, _, egpio), + [175] =3D PINGROUP(175, resout_gpio, _, phase_flag, _, _, _, _, _, _, _, = egpio), + [176] =3D PINGROUP(176, _, phase_flag, qdss_cti, _, _, _, _, _, _, _, egp= io), + [177] =3D PINGROUP(177, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _= , _, _, egpio), + [178] =3D PINGROUP(178, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _= , _, _, egpio), + [179] =3D PINGROUP(179, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _= , _, _, egpio), + [180] =3D PINGROUP(180, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _= , _, _, egpio), + [181] =3D PINGROUP(181, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _= , _, _, egpio), + [182] =3D PINGROUP(182, _, phase_flag, qdss_gpio_tracedata, _, _, _, _, _= , _, _, egpio), + [183] =3D PINGROUP(183, _, _, _, _, _, _, _, _, _, _, _), + [184] =3D PINGROUP(184, pll_bist_sync, qdss_cti, _, _, _, _, _, _, _, _, = egpio), + [185] =3D UFS_RESET(ufs_reset, 0xc9004, 0xca000), +}; + +static const struct msm_gpio_wakeirq_map eliza_pdc_map[] =3D { + { 0, 82 }, { 3, 87 }, { 4, 90 }, { 6, 68 }, { 7, 153 }, + { 11, 85 }, { 12, 107 }, { 13, 106 }, { 16, 88 }, { 17, 70 }, + { 18, 134 }, { 19, 79 }, { 23, 80 }, { 26, 91 }, { 27, 74 }, + { 28, 137 }, { 29, 138 }, { 30, 139 }, { 31, 140 }, { 32, 117 }, + { 34, 100 }, { 35, 98 }, { 36, 141 }, { 39, 89 }, { 40, 142 }, + { 42, 143 }, { 44, 101 }, { 45, 144 }, { 46, 145 }, { 47, 146 }, + { 49, 75 }, { 51, 147 }, { 52, 148 }, { 53, 149 }, { 54, 150 }, + { 55, 151 }, { 56, 152 }, { 58, 71 }, { 59, 155 }, { 63, 99 }, + { 78, 156 }, { 79, 76 }, { 80, 157 }, { 81, 69 }, { 87, 158 }, + { 91, 67 }, { 92, 159 }, { 95, 160 }, { 98, 161 }, { 99, 162 }, + { 100, 83 }, { 108, 154 }, { 109, 84 }, { 112, 86 }, { 113, 92 }, + { 114, 93 }, { 115, 110 }, { 116, 94 }, { 117, 77 }, { 118, 108 }, + { 119, 95 }, { 120, 81 }, { 121, 96 }, { 122, 97 }, { 123, 102 }, + { 125, 103 }, { 127, 104 }, { 128, 105 }, { 129, 78 }, { 130, 112 }, + { 131, 113 }, { 133, 114 }, { 135, 115 }, { 139, 116 }, { 142, 118 }, + { 145, 109 }, { 147, 72 }, { 149, 111 }, { 154, 122 }, { 157, 119 }, + { 159, 120 }, { 161, 121 }, { 164, 123 }, { 165, 124 }, { 167, 125 }, + { 170, 126 }, { 171, 73 }, { 172, 127 }, { 173, 128 }, { 174, 129 }, + { 175, 130 }, { 176, 131 }, { 177, 132 }, { 179, 133 }, { 182, 135 }, + { 184, 136 }, +}; + +static const struct msm_pinctrl_soc_data eliza_tlmm =3D { + .pins =3D eliza_pins, + .npins =3D ARRAY_SIZE(eliza_pins), + .functions =3D eliza_functions, + .nfunctions =3D ARRAY_SIZE(eliza_functions), + .groups =3D eliza_groups, + .ngroups =3D ARRAY_SIZE(eliza_groups), + .ngpios =3D 186, + .wakeirq_map =3D eliza_pdc_map, + .nwakeirq_map =3D ARRAY_SIZE(eliza_pdc_map), + .egpio_func =3D 11, +}; + +static int eliza_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &eliza_tlmm); +} + +static const struct of_device_id eliza_tlmm_of_match[] =3D { + { .compatible =3D "qcom,eliza-tlmm", }, + {}, +}; + +static struct platform_driver eliza_tlmm_driver =3D { + .driver =3D { + .name =3D "eliza-tlmm", + .of_match_table =3D eliza_tlmm_of_match, + }, + .probe =3D eliza_tlmm_probe, +}; + +static int __init eliza_tlmm_init(void) +{ + return platform_driver_register(&eliza_tlmm_driver); +} +arch_initcall(eliza_tlmm_init); + +static void __exit eliza_tlmm_exit(void) +{ + platform_driver_unregister(&eliza_tlmm_driver); +} +module_exit(eliza_tlmm_exit); + +MODULE_DESCRIPTION("QTI Eliza TLMM driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, eliza_tlmm_of_match); --=20 2.48.1