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Mon, 26 Jan 2026 14:00:05 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [RFC 1/2] pci: Add fallible I/O methods to ConfigSpace Date: Mon, 26 Jan 2026 23:59:56 +0200 Message-ID: <20260126215957.541180-2-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260126215957.541180-1-zhiw@nvidia.com> References: <20260126215957.541180-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004681:EE_|DM4PR12MB8474:EE_ X-MS-Office365-Filtering-Correlation-Id: 18651b63-48fb-4ca9-e9db-08de5d2654d7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|7416014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?9KoqzpP4czZ8fLhBISKJ6D1nE5XIzn9pomlhB6K1tsEPoaJBWEs/RSPcfYcq?= =?us-ascii?Q?3ayvdj2b/ALB9Dh8E1vts7SWe8ME1fZ7dnHiSeeDkICAWXc9jhyioOgrDGe4?= =?us-ascii?Q?dZR9V+FXrIEAkHiW6Ccvvcfq0Fc986gEja/JsdEeRPjVCxx3MoDLkboWnQV/?= =?us-ascii?Q?1iDE7rQq9IcFfB2VsU6CMrAGiB/601aftn5av9MaOrkP0aWMPLAeufUoLP2Z?= =?us-ascii?Q?26wDvIvctgSOkTbZ95QIVJjkxX1JyHejCkikp+BUC96Sr65VB9o6jKE5YD/n?= =?us-ascii?Q?PjzKDxJrY7jkNWi+HyDYKjAWEiWhlv9W0neTeS8vKod9vDcsN9UCy38FnYc+?= =?us-ascii?Q?/ypPpfHB8jSpGKa6SDvfA+F3BwKF3z9B6SbJzLt/HP2VMcylNzGvEoV1ZUHk?= =?us-ascii?Q?gZ71D2n/RLFebofkh+aWmVsFpcounTBQMohmVd/tsFCfAuTnqYdKKAEDTei5?= =?us-ascii?Q?lZ7hoOrlqYmkEhm/uBLnlX66qjtCpgI1CMOEDsQdYxav0VBGRSxlPsnqGnCt?= =?us-ascii?Q?axf3BneadZjVTcgPMoBpLYRjMsTatffEhKowkBz78L2dnxU9bYzGK7w8NHZO?= =?us-ascii?Q?Bv0JQ+8K8rZqzOeCE8qecGvnhm7SLOgCorHqpWBQyq/eQgSO6FYlYCLL1roj?= =?us-ascii?Q?1I3YESqqygzvBKi0WSfFjQ9S1/Rr2mJiadRzYOO+NWSlSSz8B6WR/73flbk5?= =?us-ascii?Q?fG3jzfP41CNTRp2g5+EFhUPGvIc2b7OmliJGB9TjiGv+UH4LG3EByuYVOfyL?= =?us-ascii?Q?rkn6IxxXMAYTKOXNKl53xgUaA2jFJGqlqznLIuu96OhDn/MWuA4R0qT98eZq?= =?us-ascii?Q?+PF707UF8UbuQ2meoLK+OAt5mvq37jZbE03RIoT4xSuPpTYMqKUxL/TsScEq?= =?us-ascii?Q?gPoLtZ3adEB2E+JsHTYkC+gnbvhONO9FynTb96+pdcLSYcs43CYRXEgWiXtC?= =?us-ascii?Q?Iwq0zc4k214hU12V0vYORKKpUB21FLqS7vxIOImHPuHJFw1neKC4hMxRx9Rr?= =?us-ascii?Q?4SSkdWgp7iS52SdiDxHC3mlIcF9deJwty93S9ajBjOgKy2b9P3m8DESYWPk7?= =?us-ascii?Q?3emq9eaxFCzYZM3KIGHWZthMJxb0clrYic9O2G8M3K95rrcm5iV7XpcrA1uj?= =?us-ascii?Q?TaOxiqqDcxC4eyPTjI1k5cmO4dQOa8XDsPmxFc8+TQcdWhauwkDwrR2MH7Aj?= =?us-ascii?Q?1ZylNVn+p8OHkNHyHnvOdrU6baWZULUYYePp9kt9foudu25d1Wa/7MaDvXE2?= =?us-ascii?Q?9D1JmHmXxmF4HyqHBlWtPWyV1xK4FZEYUWHXW1SoYjeu/twxpIydkmmbDCtO?= =?us-ascii?Q?zEOeNvbXxCGjlAAdk1rQMBzwzWFFfIlIpFtfpVSB09YnbdJwwWIewSSAlDS4?= =?us-ascii?Q?1XQBZgeIoUmfp5oiRFIVSGACuLl1Nm+1Uv+JIPHSfJZ+/8qvofcilyh50UPu?= =?us-ascii?Q?LrT7H51RToPDnAmEUf6SMNklL+XcwAGa2sjHJmDa86sxp5t1Wyilq8fh7uIQ?= =?us-ascii?Q?VyyPjdfn48bFrOrKkQJD6lInfRQUUsCBaHwRyrcRVi3U5ra/AKEbfrFyBnNq?= =?us-ascii?Q?DGgyJTkXBVZMXvPY+vsw4RepjT2Qxf3TqHOl38MTGACuEszoGiB8GxOnym0U?= =?us-ascii?Q?bu7CafcHxWvx5XP1rkftm/SRlHH9DY1AQMDgvDGS3Q4eP/CepPJLVdCyrAUW?= =?us-ascii?Q?zhFGUg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2026 22:00:34.4965 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18651b63-48fb-4ca9-e9db-08de5d2654d7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004681.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8474 Content-Type: text/plain; charset="utf-8" Rust PCI drivers might need to access device configuration space with runtime bound check. The existing ConfigSpace abstraction only provides infallible methods (read8/16/32) that use compile-time bounds checking via io_addr_assert, which cannot handle dynamic offsets. Add fallible I/O methods to ConfigSpace. Signed-off-by: Zhi Wang --- rust/kernel/pci/io.rs | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs index 026e7a3b69bd..9fc9af0f9bfc 100644 --- a/rust/kernel/pci/io.rs +++ b/rust/kernel/pci/io.rs @@ -112,6 +112,17 @@ macro_rules! call_config_read { let _ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr a= s i32, &mut val) }; val }}; + + (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) =3D> {{ + let mut val: $ty =3D 0; + // SAFETY: By the type invariant `$self.pdev` is a valid address. + let ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as= i32, &mut val) }; + if ret !=3D 0 { + Err(EIO) + } else { + Ok(val) + } + }}; } =20 /// Internal helper macros used to invoke C PCI configuration space write = functions. @@ -140,6 +151,16 @@ macro_rules! call_config_write { // Return value from C function is ignored in infallible accessors. let _ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr a= s i32, $value) }; }; + + (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) = =3D> {{ + // SAFETY: By the type invariant `$self.pdev` is a valid address. + let ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as= i32, $value) }; + if ret !=3D 0 { + Err(EIO) + } else { + Ok(()) + } + }}; } =20 // PCI configuration space supports 8, 16, and 32-bit accesses. @@ -162,9 +183,7 @@ fn maxsize(&self) -> usize { self.pdev.cfg_size().into_raw() } =20 - // PCI configuration space does not support fallible operations. - // The default implementations from the Io trait are not used. - + // Infallible methods with compile-time bounds checking define_read!(infallible, read8, call_config_read(pci_read_config_byte)= -> u8); define_read!(infallible, read16, call_config_read(pci_read_config_word= ) -> u16); define_read!(infallible, read32, call_config_read(pci_read_config_dwor= d) -> u32); @@ -172,6 +191,15 @@ fn maxsize(&self) -> usize { define_write!(infallible, write8, call_config_write(pci_write_config_b= yte) <- u8); define_write!(infallible, write16, call_config_write(pci_write_config_= word) <- u16); define_write!(infallible, write32, call_config_write(pci_write_config_= dword) <- u32); + + // Fallible methods with runtime bounds checking + define_read!(fallible, try_read8, call_config_read(pci_read_config_byt= e) -> u8); + define_read!(fallible, try_read16, call_config_read(pci_read_config_wo= rd) -> u16); + define_read!(fallible, try_read32, call_config_read(pci_read_config_dw= ord) -> u32); + + define_write!(fallible, try_write8, call_config_write(pci_write_config= _byte) <- u8); + define_write!(fallible, try_write16, call_config_write(pci_write_confi= g_word) <- u16); + define_write!(fallible, try_write32, call_config_write(pci_write_confi= g_dword) <- u32); } =20 /// Marker trait indicating ConfigSpace has a known size at compile time. --=20 2.51.0