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Mon, 26 Jan 2026 14:00:05 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [RFC 1/2] pci: Add fallible I/O methods to ConfigSpace Date: Mon, 26 Jan 2026 23:59:56 +0200 Message-ID: <20260126215957.541180-2-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260126215957.541180-1-zhiw@nvidia.com> References: <20260126215957.541180-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004681:EE_|DM4PR12MB8474:EE_ X-MS-Office365-Filtering-Correlation-Id: 18651b63-48fb-4ca9-e9db-08de5d2654d7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|7416014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?9KoqzpP4czZ8fLhBISKJ6D1nE5XIzn9pomlhB6K1tsEPoaJBWEs/RSPcfYcq?= =?us-ascii?Q?3ayvdj2b/ALB9Dh8E1vts7SWe8ME1fZ7dnHiSeeDkICAWXc9jhyioOgrDGe4?= =?us-ascii?Q?dZR9V+FXrIEAkHiW6Ccvvcfq0Fc986gEja/JsdEeRPjVCxx3MoDLkboWnQV/?= =?us-ascii?Q?1iDE7rQq9IcFfB2VsU6CMrAGiB/601aftn5av9MaOrkP0aWMPLAeufUoLP2Z?= =?us-ascii?Q?26wDvIvctgSOkTbZ95QIVJjkxX1JyHejCkikp+BUC96Sr65VB9o6jKE5YD/n?= =?us-ascii?Q?PjzKDxJrY7jkNWi+HyDYKjAWEiWhlv9W0neTeS8vKod9vDcsN9UCy38FnYc+?= =?us-ascii?Q?/ypPpfHB8jSpGKa6SDvfA+F3BwKF3z9B6SbJzLt/HP2VMcylNzGvEoV1ZUHk?= =?us-ascii?Q?gZ71D2n/RLFebofkh+aWmVsFpcounTBQMohmVd/tsFCfAuTnqYdKKAEDTei5?= =?us-ascii?Q?lZ7hoOrlqYmkEhm/uBLnlX66qjtCpgI1CMOEDsQdYxav0VBGRSxlPsnqGnCt?= =?us-ascii?Q?axf3BneadZjVTcgPMoBpLYRjMsTatffEhKowkBz78L2dnxU9bYzGK7w8NHZO?= =?us-ascii?Q?Bv0JQ+8K8rZqzOeCE8qecGvnhm7SLOgCorHqpWBQyq/eQgSO6FYlYCLL1roj?= =?us-ascii?Q?1I3YESqqygzvBKi0WSfFjQ9S1/Rr2mJiadRzYOO+NWSlSSz8B6WR/73flbk5?= =?us-ascii?Q?fG3jzfP41CNTRp2g5+EFhUPGvIc2b7OmliJGB9TjiGv+UH4LG3EByuYVOfyL?= =?us-ascii?Q?rkn6IxxXMAYTKOXNKl53xgUaA2jFJGqlqznLIuu96OhDn/MWuA4R0qT98eZq?= =?us-ascii?Q?+PF707UF8UbuQ2meoLK+OAt5mvq37jZbE03RIoT4xSuPpTYMqKUxL/TsScEq?= =?us-ascii?Q?gPoLtZ3adEB2E+JsHTYkC+gnbvhONO9FynTb96+pdcLSYcs43CYRXEgWiXtC?= =?us-ascii?Q?Iwq0zc4k214hU12V0vYORKKpUB21FLqS7vxIOImHPuHJFw1neKC4hMxRx9Rr?= =?us-ascii?Q?4SSkdWgp7iS52SdiDxHC3mlIcF9deJwty93S9ajBjOgKy2b9P3m8DESYWPk7?= =?us-ascii?Q?3emq9eaxFCzYZM3KIGHWZthMJxb0clrYic9O2G8M3K95rrcm5iV7XpcrA1uj?= =?us-ascii?Q?TaOxiqqDcxC4eyPTjI1k5cmO4dQOa8XDsPmxFc8+TQcdWhauwkDwrR2MH7Aj?= =?us-ascii?Q?1ZylNVn+p8OHkNHyHnvOdrU6baWZULUYYePp9kt9foudu25d1Wa/7MaDvXE2?= =?us-ascii?Q?9D1JmHmXxmF4HyqHBlWtPWyV1xK4FZEYUWHXW1SoYjeu/twxpIydkmmbDCtO?= =?us-ascii?Q?zEOeNvbXxCGjlAAdk1rQMBzwzWFFfIlIpFtfpVSB09YnbdJwwWIewSSAlDS4?= =?us-ascii?Q?1XQBZgeIoUmfp5oiRFIVSGACuLl1Nm+1Uv+JIPHSfJZ+/8qvofcilyh50UPu?= =?us-ascii?Q?LrT7H51RToPDnAmEUf6SMNklL+XcwAGa2sjHJmDa86sxp5t1Wyilq8fh7uIQ?= =?us-ascii?Q?VyyPjdfn48bFrOrKkQJD6lInfRQUUsCBaHwRyrcRVi3U5ra/AKEbfrFyBnNq?= =?us-ascii?Q?DGgyJTkXBVZMXvPY+vsw4RepjT2Qxf3TqHOl38MTGACuEszoGiB8GxOnym0U?= =?us-ascii?Q?bu7CafcHxWvx5XP1rkftm/SRlHH9DY1AQMDgvDGS3Q4eP/CepPJLVdCyrAUW?= =?us-ascii?Q?zhFGUg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2026 22:00:34.4965 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18651b63-48fb-4ca9-e9db-08de5d2654d7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004681.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8474 Content-Type: text/plain; charset="utf-8" Rust PCI drivers might need to access device configuration space with runtime bound check. The existing ConfigSpace abstraction only provides infallible methods (read8/16/32) that use compile-time bounds checking via io_addr_assert, which cannot handle dynamic offsets. Add fallible I/O methods to ConfigSpace. Signed-off-by: Zhi Wang --- rust/kernel/pci/io.rs | 34 +++++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs index 026e7a3b69bd..9fc9af0f9bfc 100644 --- a/rust/kernel/pci/io.rs +++ b/rust/kernel/pci/io.rs @@ -112,6 +112,17 @@ macro_rules! call_config_read { let _ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr a= s i32, &mut val) }; val }}; + + (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) =3D> {{ + let mut val: $ty =3D 0; + // SAFETY: By the type invariant `$self.pdev` is a valid address. + let ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as= i32, &mut val) }; + if ret !=3D 0 { + Err(EIO) + } else { + Ok(val) + } + }}; } =20 /// Internal helper macros used to invoke C PCI configuration space write = functions. @@ -140,6 +151,16 @@ macro_rules! call_config_write { // Return value from C function is ignored in infallible accessors. let _ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr a= s i32, $value) }; }; + + (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) = =3D> {{ + // SAFETY: By the type invariant `$self.pdev` is a valid address. + let ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as= i32, $value) }; + if ret !=3D 0 { + Err(EIO) + } else { + Ok(()) + } + }}; } =20 // PCI configuration space supports 8, 16, and 32-bit accesses. @@ -162,9 +183,7 @@ fn maxsize(&self) -> usize { self.pdev.cfg_size().into_raw() } =20 - // PCI configuration space does not support fallible operations. - // The default implementations from the Io trait are not used. - + // Infallible methods with compile-time bounds checking define_read!(infallible, read8, call_config_read(pci_read_config_byte)= -> u8); define_read!(infallible, read16, call_config_read(pci_read_config_word= ) -> u16); define_read!(infallible, read32, call_config_read(pci_read_config_dwor= d) -> u32); @@ -172,6 +191,15 @@ fn maxsize(&self) -> usize { define_write!(infallible, write8, call_config_write(pci_write_config_b= yte) <- u8); define_write!(infallible, write16, call_config_write(pci_write_config_= word) <- u16); define_write!(infallible, write32, call_config_write(pci_write_config_= dword) <- u32); + + // Fallible methods with runtime bounds checking + define_read!(fallible, try_read8, call_config_read(pci_read_config_byt= e) -> u8); + define_read!(fallible, try_read16, call_config_read(pci_read_config_wo= rd) -> u16); + define_read!(fallible, try_read32, call_config_read(pci_read_config_dw= ord) -> u32); + + define_write!(fallible, try_write8, call_config_write(pci_write_config= _byte) <- u8); + define_write!(fallible, try_write16, call_config_write(pci_write_confi= g_word) <- u16); + define_write!(fallible, try_write32, call_config_write(pci_write_confi= g_dword) <- u32); } =20 /// Marker trait indicating ConfigSpace has a known size at compile time. --=20 2.51.0 From nobody Sun Feb 8 08:49:04 2026 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012006.outbound.protection.outlook.com [40.107.209.6]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3A952FC024; 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Mon, 26 Jan 2026 14:00:18 -0800 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Mon, 26 Jan 2026 14:00:18 -0800 Received: from inno-vm-xubuntu (10.127.8.9) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Mon, 26 Jan 2026 14:00:12 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [RFC 2/2] pci: Add PCI capability infrastructure and SR-IOV capability support Date: Mon, 26 Jan 2026 23:59:57 +0200 Message-ID: <20260126215957.541180-3-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260126215957.541180-1-zhiw@nvidia.com> References: <20260126215957.541180-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD7:EE_|DM4PR12MB5987:EE_ X-MS-Office365-Filtering-Correlation-Id: 537f8885-59b0-41cf-9cba-08de5d265aea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700013|1800799024; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2026 22:00:44.7454 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 537f8885-59b0-41cf-9cba-08de5d265aea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5987 Content-Type: text/plain; charset="utf-8" Rust drivers may need to access PCI capabilities (such as SR-IOV) to configure firmware metadata. Add a generic Capability structure that: - Wraps capability discovery via kernel's pci_find_ext_capability() - Dynamically calculates capability size by reading next capability pointers (using 0xffc mask per PCI_EXT_CAP_NEXT for extended caps) - Implements fallible I/O via the Io trait with runtime bounds checking Add SR-IOV (Single Root I/O Virtualization) capability support: - SriovCapability wraps Capability - read_vf_offset() reads PCI_SRIOV_VF_OFFSET register - read_vf_bar(n) reads PCI_SRIOV_BAR + n*4 (32-bit BAR) - read_vf_bar64(n) reads 64-bit BAR by combining two 32-bit reads Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 9 ++ rust/kernel/pci/cap.rs | 274 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 283 insertions(+) create mode 100644 rust/kernel/pci/cap.rs diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index cd46ac12812c..2deb26fb3775 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -31,6 +31,7 @@ }, }; =20 +mod cap; mod id; mod io; mod irq; @@ -42,6 +43,7 @@ }; pub use self::io::{ Bar, + ConfigSpace, ConfigSpaceKind, ConfigSpaceSize, Extended, @@ -52,6 +54,13 @@ IrqTypes, IrqVector, // }; +pub use self::cap::{ + Capability, + CapabilityId, + CapabilityKind, + ExtCapabilityId, + SriovCapability, // +}; =20 /// An adapter for the registration of PCI drivers. pub struct Adapter(T); diff --git a/rust/kernel/pci/cap.rs b/rust/kernel/pci/cap.rs new file mode 100644 index 000000000000..e3a903b79299 --- /dev/null +++ b/rust/kernel/pci/cap.rs @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! PCI Capability support. +//! +//! This module provides abstractions for discovering and accessing PCI ca= pabilities. + +use super::{ + ConfigSpace, + ConfigSpaceKind, + Extended, + Normal, // +}; +use crate::{ + bindings, + io::{ + define_read, + define_write, + Io, + IoCapable, // + }, + prelude::*, +}; + +/// Internal helper macro to call ConfigSpace fallible methods from Capabi= lity. +macro_rules! call_cap_read { + (fallible, $method:ident, $self:ident, $ty:ty, $addr:expr) =3D> { + $self.config_space.$method($self.offset() + $addr) + }; +} + +/// Internal helper macro to call ConfigSpace fallible write methods from = Capability. +macro_rules! call_cap_write { + (fallible, $method:ident, $self:ident, $ty:ty, $addr:expr, $value:expr= ) =3D> { + $self.config_space.$method($value, $self.offset() + $addr) + }; +} + +/// PCI Capability IDs for normal capabilities (in 256-byte config space). +/// +/// These are not currently implemented, but the enum is provided for API = completeness. +#[repr(u8)] +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum CapabilityId { + /// Power Management + PM =3D bindings::PCI_CAP_ID_PM as u8, + /// Message Signalled Interrupts + MSI =3D bindings::PCI_CAP_ID_MSI as u8, + /// MSI-X + MSIX =3D bindings::PCI_CAP_ID_MSIX as u8, + /// PCI Express + Express =3D bindings::PCI_CAP_ID_EXP as u8, + /// Vendor Specific + VendorSpecific =3D bindings::PCI_CAP_ID_VNDR as u8, +} + +/// PCI Extended Capability IDs (in 4096-byte config space). +/// +/// Currently only SR-IOV is implemented. +#[repr(u16)] +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum ExtCapabilityId { + /// Single Root I/O Virtualization + SRIOV =3D bindings::PCI_EXT_CAP_ID_SRIOV as u16, +} + +/// Trait for capability kinds (Normal or Extended). +pub trait CapabilityKind { + /// The capability ID type for this kind. + type IdType: Copy + PartialEq; + + /// Start offset for capability scanning. + const START_OFFSET: usize; +} + +/// Marker for normal (legacy) PCI capabilities. +impl CapabilityKind for Normal { + type IdType =3D u8; + const START_OFFSET: usize =3D bindings::PCI_CAPABILITY_LIST as usize; +} + +/// Marker for extended PCI capabilities. +impl CapabilityKind for Extended { + type IdType =3D u16; + const START_OFFSET: usize =3D bindings::PCI_CFG_SPACE_SIZE as usize; +} + +/// A PCI capability. +/// +/// This type represents a discovered PCI capability and provides safe acc= ess +/// to its registers. All I/O operations are relative to the capability's +/// base offset in configuration space. +pub struct Capability<'a, S: ConfigSpaceKind, K: CapabilityKind> { + config_space: &'a ConfigSpace<'a, S>, + offset: usize, + id: K::IdType, + size: usize, +} + +impl<'a, S: ConfigSpaceKind, K: CapabilityKind> Capability<'a, S, K> { + /// Creates a new capability handle. + fn new( + config_space: &'a ConfigSpace<'a, S>, + offset: usize, + id: K::IdType, + size: usize, + ) -> Self { + Self { + config_space, + offset, + id, + size, + } + } + + /// Returns the offset of this capability in configuration space. + pub fn offset(&self) -> usize { + self.offset + } + + /// Returns the capability ID. + pub fn id(&self) -> K::IdType { + self.id + } + + /// Returns the size of this capability in bytes. + pub fn size(&self) -> usize { + self.size + } +} + +// Implement IoCapable for Capability +impl<'a, S: ConfigSpaceKind, K: CapabilityKind> IoCapable for Capabili= ty<'a, S, K> {} +impl<'a, S: ConfigSpaceKind, K: CapabilityKind> IoCapable for Capabil= ity<'a, S, K> {} +impl<'a, S: ConfigSpaceKind, K: CapabilityKind> IoCapable for Capabil= ity<'a, S, K> {} + +// Implement Io trait for Capability using fallible methods (runtime check= s) +impl<'a, S: ConfigSpaceKind, K: CapabilityKind> Io for Capability<'a, S, K= > { + const MIN_SIZE: usize =3D S::SIZE; // Use config space size for fallib= le bounds checking + + #[inline] + fn addr(&self) -> usize { + 0 // Offsets are relative to capability base, not absolute + } + + #[inline] + fn maxsize(&self) -> usize { + self.size() + } + + // Only implement fallible methods (no IoKnownSize, so infallible meth= ods not available) + define_read!(fallible, try_read8, call_cap_read(try_read8) -> u8); + define_read!(fallible, try_read16, call_cap_read(try_read16) -> u16); + define_read!(fallible, try_read32, call_cap_read(try_read32) -> u32); + + define_write!(fallible, try_write8, call_cap_write(try_write8) <- u8); + define_write!(fallible, try_write16, call_cap_write(try_write16) <- u1= 6); + define_write!(fallible, try_write32, call_cap_write(try_write32) <- u3= 2); +} + +impl<'a> ConfigSpace<'a, Extended> { + /// Finds a specific extended capability by ID using the kernel's `pci= _find_ext_capability`. + pub fn find_ext_capability(&self, id: u16) -> Option> { + // SAFETY: pdev is valid by ConfigSpace invariants + let offset =3D unsafe { bindings::pci_find_ext_capability(self.pde= v.as_raw(), id as i32) }; + + if offset =3D=3D 0 { + return None; + } + + let size =3D self.calculate_ext_cap_size(offset as usize); + Some(Capability::new(self, offset as usize, id, size)) + } + + fn calculate_ext_cap_size(&self, offset: usize) -> usize { + // Extended capability header: [31:20] =3D next capability offset + // Use 0xffc mask (not 0xfff) to match kernel's PCI_EXT_CAP_NEXT m= acro + let header =3D self.try_read32(offset).unwrap_or(0); + let next_ptr =3D ((header >> 20) & 0xffc) as usize; + + if next_ptr =3D=3D 0 { + // Last capability, size goes to end of config space + self.pdev.cfg_size().into_raw() - offset + } else { + // Size is distance to next capability + next_ptr - offset + } + } + + /// Finds the next occurrence of a specific extended capability starti= ng from a given position. + pub fn find_next_ext_capability( + &self, + start_pos: u16, + id: u16, + ) -> Option> { + // SAFETY: pdev is valid by ConfigSpace invariants + let offset =3D unsafe { + bindings::pci_find_next_ext_capability(self.pdev.as_raw(), sta= rt_pos, id as i32) + }; + + if offset =3D=3D 0 { + return None; + } + + // Calculate real capability size + let size =3D self.calculate_ext_cap_size(offset as usize); + Some(Capability::new(self, offset as usize, id, size)) + } +} + +/// SR-IOV register offsets (relative to the capability base). +mod sriov_offsets { + use crate::bindings; + + /// First VF Offset register offset + pub(super) const VF_OFFSET: usize =3D bindings::PCI_SRIOV_VF_OFFSET as= usize; + /// VF BAR0 register offset (first of 6 VF BARs) + pub(super) const VF_BAR0: usize =3D bindings::PCI_SRIOV_BAR as usize; +} + +/// SR-IOV capability structure. +/// +/// This structure provides typed access to the SR-IOV extended capability +/// registers using the PCI configuration space backend. +pub struct SriovCapability<'a> { + cap: Capability<'a, Extended, Extended>, +} + +impl<'a> SriovCapability<'a> { + /// Creates a new SR-IOV capability from an extended capability. + pub fn new(cap: Capability<'a, Extended, Extended>) -> Result { + if cap.id() !=3D ExtCapabilityId::SRIOV as u16 { + return Err(EINVAL); + } + Ok(Self { cap }) + } + + /// Tries to find and create an SR-IOV capability from a config space. + pub fn from_config_space(config_space: &'a ConfigSpace<'a, Extended>) = -> Result { + let cap =3D config_space + .find_ext_capability(ExtCapabilityId::SRIOV as u16) + .ok_or(ENODEV)?; + Self::new(cap) + } + + /// Returns the offset of this capability in configuration space. + pub fn offset(&self) -> usize { + self.cap.offset() + } + + /// Reads the First VF Offset register. + pub fn read_vf_offset(&self) -> Result { + self.cap.try_read16(sriov_offsets::VF_OFFSET) + } + + /// Reads a VF BAR register (32-bit). + /// Returns the 32-bit value of the specified VF BAR register. + pub fn read_vf_bar(&self, bar_index: usize) -> Result { + if bar_index >=3D 6 { + return Err(EINVAL); + } + self.cap.try_read32(sriov_offsets::VF_BAR0 + bar_index * 4) + } + + /// Reads a 64-bit VF BAR register. + /// Returns the 64-bit address combining BAR[n] (low) and BAR[n+1] (hi= gh). + pub fn read_vf_bar64(&self, bar_index: usize) -> Result { + if bar_index >=3D 5 { + return Err(EINVAL); + } + let low =3D self.read_vf_bar(bar_index)?; + let high =3D self.read_vf_bar(bar_index + 1)?; + Ok((u64::from(high) << 32) | u64::from(low)) + } +} --=20 2.51.0