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Mon, 26 Jan 2026 11:15:47 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel , Mikko Perttunen Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/5] ARM: tegra: Add ACTMON node to Tegra114 device tree Date: Mon, 26 Jan 2026 21:15:32 +0200 Message-ID: <20260126191536.78829-2-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260126191536.78829-1-clamor95@gmail.com> References: <20260126191536.78829-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for ACTMON on Tegra114. This is used to monitor activity from different components. Based on the collected statistics, the rate at which the external memory needs to be clocked can be derived. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- arch/arm/boot/dts/nvidia/tegra114.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvi= dia/tegra114.dtsi index 02d2c40dd79a..ef0618e9eec1 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -312,6 +312,18 @@ ahb: ahb@6000c000 { reg =3D <0x6000c000 0x150>; }; =20 + actmon: actmon@6000c800 { + compatible =3D "nvidia,tegra114-actmon"; + reg =3D <0x6000c800 0x400>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA114_CLK_ACTMON>, + <&tegra_car TEGRA114_CLK_EMC>; + clock-names =3D "actmon", "emc"; + resets =3D <&tegra_car TEGRA114_CLK_ACTMON>; + reset-names =3D "actmon"; + #cooling-cells =3D <2>; + }; + gpio: gpio@6000d000 { compatible =3D "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; reg =3D <0x6000d000 0x1000>; --=20 2.51.0 From nobody Sat Feb 7 08:13:56 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA416254849 for ; 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Mon, 26 Jan 2026 11:15:49 -0800 (PST) Received: from xeon ([188.163.112.49]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435b1c02d0dsm30958219f8f.4.2026.01.26.11.15.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 11:15:48 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel , Mikko Perttunen Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/5] ARM: tegra: Add External Memory Controller node on Tegra114 Date: Mon, 26 Jan 2026 21:15:33 +0200 Message-ID: <20260126191536.78829-3-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260126191536.78829-1-clamor95@gmail.com> References: <20260126191536.78829-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add External Memory Controller node to the device-tree. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- arch/arm/boot/dts/nvidia/tegra114.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvi= dia/tegra114.dtsi index ef0618e9eec1..77ab17f397f6 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -259,6 +259,8 @@ tegra_car: clock@60006000 { reg =3D <0x60006000 0x1000>; #clock-cells =3D <1>; #reset-cells =3D <1>; + + nvidia,external-memory-controller =3D <&emc>; }; =20 flow-controller@60007000 { @@ -655,6 +657,16 @@ mc: memory-controller@70019000 { #iommu-cells =3D <1>; }; =20 + emc: external-memory-controller@7001b000 { + compatible =3D "nvidia,tegra114-emc"; + reg =3D <0x7001b000 0x800>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA114_CLK_EMC>; + clock-names =3D "emc"; + + nvidia,memory-controller =3D <&mc>; + }; + hda@70030000 { compatible =3D "nvidia,tegra114-hda", "nvidia,tegra30-hda"; reg =3D <0x70030000 0x10000>; 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Mon, 26 Jan 2026 11:15:49 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel , Mikko Perttunen Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/5] ARM: tegra: Add EMC OPP and ICC properties to Tegra114 EMC and ACTMON device-tree nodes Date: Mon, 26 Jan 2026 21:15:34 +0200 Message-ID: <20260126191536.78829-4-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260126191536.78829-1-clamor95@gmail.com> References: <20260126191536.78829-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add EMC OPP tables and interconnect paths that will be used for dynamic memory bandwidth scaling based on memory utilization statistics. Signed-off-by: Svyatoslav Ryhel --- .../dts/nvidia/tegra114-peripherals-opp.dtsi | 164 ++++++++++++++++++ arch/arm/boot/dts/nvidia/tegra114.dtsi | 9 + 2 files changed, 173 insertions(+) create mode 100644 arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi b/arch/= arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi new file mode 100644 index 000000000000..b40a1c24abab --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + emc_icc_dvfs_opp_table: opp-table-emc { + compatible =3D "operating-points-v2"; + + opp-12750000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <12750000>; + opp-supported-hw =3D <0x000F>; + }; + + opp-20400000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <20400000>; + opp-supported-hw =3D <0x000F>; + }; + + opp-40800000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <40800000>; + opp-supported-hw =3D <0x000F>; + }; + + opp-68000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <68000000>; + opp-supported-hw =3D <0x000F>; + }; + + opp-102000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <102000000>; + opp-supported-hw =3D <0x000F>; + }; + + opp-204000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <204000000>; + opp-supported-hw =3D <0x000F>; + opp-suspend; + }; + + opp-312000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <312000000>; + opp-supported-hw =3D <0x000F>; + }; + + opp-408000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <408000000>; + opp-supported-hw =3D <0x000F>; + }; + + /* + * T40X can work with 1050mV for 528MHz but T40T which is + * in the same group as T40X requires 1100mV. If there will + * be enough data that T40T can work reliably with 1050mV + * for 528MHz then voltage for 528MHz opp can be lowered. + * T40S should remain with 1100mV for 528MHz opp. + */ + opp-528000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <528000000>; + opp-supported-hw =3D <0x000F>; + }; + + opp-624000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <624000000>; + opp-supported-hw =3D <0x000F>; + }; + + opp-792000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <792000000>; + opp-supported-hw =3D <0x000F>; + }; + + opp-900000000-1200 { + opp-microvolt =3D <1200000 1200000 1390000>; + opp-hz =3D /bits/ 64 <900000000>; + opp-supported-hw =3D <0x000E>; + }; + }; + + emc_bw_dfs_opp_table: opp-table-actmon { + compatible =3D "operating-points-v2"; + + opp-12750000 { + opp-hz =3D /bits/ 64 <12750000>; + opp-supported-hw =3D <0x000F>; + opp-peak-kBps =3D <204000>; + }; + + opp-20400000 { + opp-hz =3D /bits/ 64 <20400000>; + opp-supported-hw =3D <0x000F>; + opp-peak-kBps =3D <326400>; + }; + + opp-40800000 { + opp-hz =3D /bits/ 64 <40800000>; + opp-supported-hw =3D <0x000F>; + opp-peak-kBps =3D <652800>; + }; + + opp-68000000 { + opp-hz =3D /bits/ 64 <68000000>; + opp-supported-hw =3D <0x000F>; + opp-peak-kBps =3D <1088000>; + }; + + opp-102000000 { + opp-hz =3D /bits/ 64 <102000000>; + opp-supported-hw =3D <0x000F>; + opp-peak-kBps =3D <1632000>; + }; + + opp-204000000 { + opp-hz =3D /bits/ 64 <204000000>; + opp-supported-hw =3D <0x000F>; + opp-peak-kBps =3D <3264000>; + opp-suspend; + }; + + opp-312000000 { + opp-hz =3D /bits/ 64 <312000000>; + opp-supported-hw =3D <0x000F>; + opp-peak-kBps =3D <4992000>; + }; + + opp-408000000 { + opp-hz =3D /bits/ 64 <408000000>; + opp-supported-hw =3D <0x000F>; + opp-peak-kBps =3D <6528000>; + }; + + opp-528000000 { + opp-hz =3D /bits/ 64 <528000000>; + opp-supported-hw =3D <0x000F>; + opp-peak-kBps =3D <8448000>; + }; + + opp-624000000 { + opp-hz =3D /bits/ 64 <624000000>; + opp-supported-hw =3D <0x000F>; + opp-peak-kBps =3D <9984000>; + }; + + opp-792000000 { + opp-hz =3D /bits/ 64 <792000000>; + opp-supported-hw =3D <0x000F>; + opp-peak-kBps =3D <12672000>; + }; + + opp-900000000 { + opp-hz =3D /bits/ 64 <900000000>; + opp-supported-hw =3D <0x000E>; + opp-peak-kBps =3D <14400000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvi= dia/tegra114.dtsi index 77ab17f397f6..9acba15fba25 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -8,6 +8,8 @@ #include #include =20 +#include "tegra114-peripherals-opp.dtsi" + / { compatible =3D "nvidia,tegra114"; interrupt-parent =3D <&lic>; @@ -323,6 +325,9 @@ actmon: actmon@6000c800 { clock-names =3D "actmon", "emc"; resets =3D <&tegra_car TEGRA114_CLK_ACTMON>; reset-names =3D "actmon"; + operating-points-v2 =3D <&emc_bw_dfs_opp_table>; + interconnects =3D <&mc TEGRA114_MC_MPCORER &emc>; + interconnect-names =3D "cpu-read"; #cooling-cells =3D <2>; }; =20 @@ -655,6 +660,7 @@ mc: memory-controller@70019000 { =20 #reset-cells =3D <1>; #iommu-cells =3D <1>; + #interconnect-cells =3D <1>; }; =20 emc: external-memory-controller@7001b000 { @@ -665,6 +671,9 @@ emc: external-memory-controller@7001b000 { clock-names =3D "emc"; =20 nvidia,memory-controller =3D <&mc>; + operating-points-v2 =3D <&emc_icc_dvfs_opp_table>; + + #interconnect-cells =3D <0>; }; =20 hda@70030000 { --=20 2.51.0 From nobody Sat Feb 7 08:13:56 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD88F28002B for ; Mon, 26 Jan 2026 19:15:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769454954; cv=none; b=IVQkPenUNFMZGh7zjp9VUEN91GItmrTE8VBfcrLrRjv5bPLFi+xYKerIPYubO4pxFl55vWK+jhz7jUofdsPCgxHkM5VR/emhF+qBzr8MRYl+f8COKjmfEhP6RckyGpfG1lPIqyrjIGasEK7J6VY2VWNSFhqJDqKGfzBp/FhRqSE= ARC-Message-Signature: i=1; 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Mon, 26 Jan 2026 11:15:50 -0800 (PST) Received: from xeon ([188.163.112.49]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435b1c02d0dsm30958219f8f.4.2026.01.26.11.15.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 11:15:50 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel , Mikko Perttunen Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/5] ARM: tegra: add DC interconnections for Tegra114 Date: Mon, 26 Jan 2026 21:15:35 +0200 Message-ID: <20260126191536.78829-5-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260126191536.78829-1-clamor95@gmail.com> References: <20260126191536.78829-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add DC interconnections to Tegra114 device tree to reflect connections between MC, EMC and DC. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- arch/arm/boot/dts/nvidia/tegra114.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvi= dia/tegra114.dtsi index 9acba15fba25..f1af206f50ee 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -125,6 +125,17 @@ dc@54200000 { =20 nvidia,head =3D <0>; =20 + interconnects =3D <&mc TEGRA114_MC_DISPLAY0A &emc>, + <&mc TEGRA114_MC_DISPLAY0B &emc>, + <&mc TEGRA114_MC_DISPLAY1B &emc>, + <&mc TEGRA114_MC_DISPLAY0C &emc>, + <&mc TEGRA114_MC_DISPLAYHC &emc>; + interconnect-names =3D "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status =3D "disabled"; }; @@ -144,6 +155,17 @@ dc@54240000 { =20 nvidia,head =3D <1>; =20 + interconnects =3D <&mc TEGRA114_MC_DISPLAY0AB &emc>, + <&mc TEGRA114_MC_DISPLAY0BB &emc>, + <&mc TEGRA114_MC_DISPLAY1BB &emc>, + <&mc TEGRA114_MC_DISPLAY0CB &emc>, + <&mc TEGRA114_MC_DISPLAYHCB &emc>; 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Mon, 26 Jan 2026 11:15:51 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel , Mikko Perttunen Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/5] ARM: tegra: configure Tegra114 power domains Date: Mon, 26 Jan 2026 21:15:36 +0200 Message-ID: <20260126191536.78829-6-clamor95@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260126191536.78829-1-clamor95@gmail.com> References: <20260126191536.78829-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add power domains found in Tegra114 and configure operating-points-v2 for supported devices accordingly. Signed-off-by: Svyatoslav Ryhel --- .../dts/nvidia/tegra114-peripherals-opp.dtsi | 1275 +++++++++++++++++ arch/arm/boot/dts/nvidia/tegra114.dtsi | 126 ++ 2 files changed, 1401 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi b/arch/= arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi index b40a1c24abab..5e66c1dc8fb7 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi @@ -1,6 +1,76 @@ // SPDX-License-Identifier: GPL-2.0 =20 / { + core_opp_table: opp-table-core { + compatible =3D "operating-points-v2"; + opp-shared; + + core_opp_900: opp-900000 { + opp-microvolt =3D <900000 900000 1390000>; + opp-level =3D <900000>; + }; + + core_opp_950: opp-950000 { + opp-microvolt =3D <950000 950000 1390000>; + opp-level =3D <950000>; + }; + + core_opp_1000: opp-1000000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-level =3D <1000000>; + }; + + core_opp_1050: opp-1050000 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-level =3D <1050000>; + }; + + core_opp_1100: opp-1100000 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-level =3D <1100000>; + }; + + core_opp_1120: opp-1120000 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-level =3D <1120000>; + }; + + core_opp_1150: opp-1150000 { + opp-microvolt =3D <1150000 1150000 1390000>; + opp-level =3D <1150000>; + }; + + core_opp_1170: opp-1170000 { + opp-microvolt =3D <1170000 1170000 1390000>; + opp-level =3D <1170000>; + }; + + core_opp_1200: opp-1200000 { + opp-microvolt =3D <1200000 1200000 1390000>; + opp-level =3D <1200000>; + }; + + core_opp_1250: opp-1250000 { + opp-microvolt =3D <1250000 1250000 1390000>; + opp-level =3D <1250000>; + }; + + core_opp_1300: opp-1300000 { + opp-microvolt =3D <1300000 1300000 1390000>; + opp-level =3D <1300000>; + }; + + core_opp_1350: opp-1350000 { + opp-microvolt =3D <1350000 1350000 1390000>; + opp-level =3D <1350000>; + }; + + core_opp_1390: opp-1390000 { + opp-microvolt =3D <1390000 1390000 1390000>; + opp-level =3D <1390000>; + }; + }; + emc_icc_dvfs_opp_table: opp-table-emc { compatible =3D "operating-points-v2"; =20 @@ -8,36 +78,42 @@ opp-12750000-900 { opp-microvolt =3D <900000 900000 1390000>; opp-hz =3D /bits/ 64 <12750000>; opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; }; =20 opp-20400000-900 { opp-microvolt =3D <900000 900000 1390000>; opp-hz =3D /bits/ 64 <20400000>; opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; }; =20 opp-40800000-900 { opp-microvolt =3D <900000 900000 1390000>; opp-hz =3D /bits/ 64 <40800000>; opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; }; =20 opp-68000000-900 { opp-microvolt =3D <900000 900000 1390000>; opp-hz =3D /bits/ 64 <68000000>; opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; }; =20 opp-102000000-900 { opp-microvolt =3D <900000 900000 1390000>; opp-hz =3D /bits/ 64 <102000000>; opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; }; =20 opp-204000000-900 { opp-microvolt =3D <900000 900000 1390000>; opp-hz =3D /bits/ 64 <204000000>; opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; opp-suspend; }; =20 @@ -45,12 +121,14 @@ opp-312000000-1000 { opp-microvolt =3D <1000000 1000000 1390000>; opp-hz =3D /bits/ 64 <312000000>; opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1000>; }; =20 opp-408000000-1000 { opp-microvolt =3D <1000000 1000000 1390000>; opp-hz =3D /bits/ 64 <408000000>; opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1000>; }; =20 /* @@ -64,24 +142,28 @@ opp-528000000-1100 { opp-microvolt =3D <1100000 1100000 1390000>; opp-hz =3D /bits/ 64 <528000000>; opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1100>; }; =20 opp-624000000-1100 { opp-microvolt =3D <1100000 1100000 1390000>; opp-hz =3D /bits/ 64 <624000000>; opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1100>; }; =20 opp-792000000-1100 { opp-microvolt =3D <1100000 1100000 1390000>; opp-hz =3D /bits/ 64 <792000000>; opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1100>; }; =20 opp-900000000-1200 { opp-microvolt =3D <1200000 1200000 1390000>; opp-hz =3D /bits/ 64 <900000000>; opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1200>; }; }; =20 @@ -161,4 +243,1197 @@ opp-900000000 { opp-peak-kBps =3D <14400000>; }; }; + + vi_dvfs_opp_table: opp-table-vi { + compatible =3D "operating-points-v2"; + + opp-114000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <114000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-216000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <216000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_950>; + }; + + opp-240000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <240000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1000>; + }; + + opp-312000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <312000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1050>; + }; + + opp-372000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <372000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1100>; + }; + + opp-408000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <408000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1050>; + }; + + opp-408000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <408000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1120>; + }; + }; + + epp_dvfs_opp_table: opp-table-epp { + compatible =3D "operating-points-v2"; + + opp-192000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <192000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_900>; + }; + + opp-240000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <240000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_900>; + }; + + opp-228000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <228000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_950>; + }; + + opp-300000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <300000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_950>; + }; + + opp-300000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <300000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1000>; + }; + + opp-384000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <384000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1000>; + }; + + opp-396000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <396000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1050>; + }; + + opp-468000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <468000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1050>; + }; + + opp-492000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <492000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1100>; + }; + + opp-528000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <528000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1100>; + }; + + opp-516000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <516000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1120>; + }; + + opp-564000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <564000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1120>; + }; + + opp-552000000-1170 { + opp-microvolt =3D <1170000 1170000 1390000>; + opp-hz =3D /bits/ 64 <552000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1170>; + }; + + opp-600000000-1170 { + opp-microvolt =3D <1170000 1170000 1390000>; + opp-hz =3D /bits/ 64 <600000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1170>; + }; + + opp-600000000-1250 { + opp-microvolt =3D <1250000 1250000 1390000>; + opp-hz =3D /bits/ 64 <600000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1250>; + }; + + opp-636000000-1200 { + opp-microvolt =3D <1200000 1200000 1390000>; + opp-hz =3D /bits/ 64 <636000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1200>; + }; + + opp-672000000-1250 { + opp-microvolt =3D <1250000 1250000 1390000>; + opp-hz =3D /bits/ 64 <672000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1250>; + }; + + opp-828000000-1390 { + opp-microvolt =3D <1390000 1390000 1390000>; + opp-hz =3D /bits/ 64 <828000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1390>; + }; + }; + + gr2d_dvfs_opp_table: opp-table-gr2d { + compatible =3D "operating-points-v2"; + + opp-192000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <192000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_900>; + }; + + opp-240000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <240000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_900>; + }; + + opp-228000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <228000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_950>; + }; + + opp-300000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <300000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_950>; + }; + + opp-300000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <300000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1000>; + }; + + opp-384000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <384000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1000>; + }; + + opp-396000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <396000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1050>; + }; + + opp-468000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <468000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1050>; + }; + + opp-492000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <492000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1100>; + }; + + opp-528000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <528000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1100>; + }; + + opp-516000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <516000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1120>; + }; + + opp-564000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <564000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1120>; + }; + + opp-552000000-1170 { + opp-microvolt =3D <1170000 1170000 1390000>; + opp-hz =3D /bits/ 64 <552000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1170>; + }; + + opp-600000000-1170 { + opp-microvolt =3D <1170000 1170000 1390000>; + opp-hz =3D /bits/ 64 <600000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1170>; + }; + + opp-600000000-1250 { + opp-microvolt =3D <1250000 1250000 1390000>; + opp-hz =3D /bits/ 64 <600000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1250>; + }; + + opp-636000000-1200 { + opp-microvolt =3D <1200000 1200000 1390000>; + opp-hz =3D /bits/ 64 <636000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1200>; + }; + + opp-672000000-1250 { + opp-microvolt =3D <1250000 1250000 1390000>; + opp-hz =3D /bits/ 64 <672000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1250>; + }; + + opp-828000000-1390 { + opp-microvolt =3D <1390000 1390000 1390000>; + opp-hz =3D /bits/ 64 <828000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1390>; + }; + }; + + gr3d_dvfs_opp_table: opp-table-gr3d { + compatible =3D "operating-points-v2"; + + opp-192000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <192000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_900>; + }; + + opp-240000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <240000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_900>; + }; + + opp-228000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <228000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_950>; + }; + + opp-300000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <300000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_950>; + }; + + opp-300000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <300000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1000>; + }; + + opp-384000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <384000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1000>; + }; + + opp-396000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <396000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1050>; + }; + + opp-468000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <468000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1050>; + }; + + opp-492000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <492000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1100>; + }; + + opp-528000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <528000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1100>; + }; + + opp-516000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <516000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1120>; + }; + + opp-564000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <564000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1120>; + }; + + opp-552000000-1170 { + opp-microvolt =3D <1170000 1170000 1390000>; + opp-hz =3D /bits/ 64 <552000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1170>; + }; + + opp-600000000-1170 { + opp-microvolt =3D <1170000 1170000 1390000>; + opp-hz =3D /bits/ 64 <600000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1170>; + }; + + opp-600000000-1250 { + opp-microvolt =3D <1250000 1250000 1390000>; + opp-hz =3D /bits/ 64 <600000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1250>; + }; + + opp-636000000-1200 { + opp-microvolt =3D <1200000 1200000 1390000>; + opp-hz =3D /bits/ 64 <636000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1200>; + }; + + opp-672000000-1250 { + opp-microvolt =3D <1250000 1250000 1390000>; + opp-hz =3D /bits/ 64 <672000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1250>; + }; + + opp-828000000-1390 { + opp-microvolt =3D <1390000 1390000 1390000>; + opp-hz =3D /bits/ 64 <828000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1390>; + }; + }; + + msenc_dvfs_opp_table: opp-table-msenc { + compatible =3D "operating-points-v2"; + + opp-144000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <144000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_900>; + }; + + opp-182000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <182000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_950>; + }; + + opp-204000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <204000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_900>; + }; + + opp-240000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <240000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1000>; + }; + + opp-252000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <252000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_950>; + }; + + opp-312000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <312000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1050>; + }; + + opp-324000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <324000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1000>; + }; + + opp-384000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <384000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1100>; + }; + + opp-408000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <408000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1050>; + }; + + opp-432000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <432000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1120>; + }; + + opp-456000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <456000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1100>; + }; + + opp-480000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <480000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1120>; + }; + + opp-480000000-1170 { + opp-microvolt =3D <1170000 1170000 1390000>; + opp-hz =3D /bits/ 64 <480000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1170>; + }; + }; + + tsec_dvfs_opp_table: opp-table-tsec { + compatible =3D "operating-points-v2"; + + opp-144000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <144000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_900>; + }; + + opp-182000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <182000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_950>; + }; + + opp-204000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <204000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_900>; + }; + + opp-240000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <240000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1000>; + }; + + opp-252000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <252000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_950>; + }; + + opp-312000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <312000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1050>; + }; + + opp-324000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <324000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1000>; + }; + + opp-384000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <384000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1100>; + }; + + opp-408000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <408000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1050>; + }; + + opp-432000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <432000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1120>; + }; + + opp-456000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <456000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1100>; + }; + + opp-480000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <480000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1120>; + }; + + opp-480000000-1170 { + opp-microvolt =3D <1170000 1170000 1390000>; + opp-hz =3D /bits/ 64 <480000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1170>; + }; + }; + + vde_dvfs_opp_table: opp-table-vde { + compatible =3D "operating-points-v2"; + + opp-144000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <144000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_900>; + }; + + opp-182000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <182000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_950>; + }; + + opp-204000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <204000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_900>; + }; + + opp-240000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <240000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1000>; + }; + + opp-252000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <252000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_950>; + }; + + opp-312000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <312000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1050>; + }; + + opp-324000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <324000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1000>; + }; + + opp-384000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <384000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1100>; + }; + + opp-408000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <408000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1050>; + }; + + opp-432000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <432000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1120>; + }; + + opp-456000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <456000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1100>; + }; + + opp-480000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <480000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1120>; + }; + + opp-480000000-1170 { + opp-microvolt =3D <1170000 1170000 1390000>; + opp-hz =3D /bits/ 64 <480000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1170>; + }; + }; + + host1x_dvfs_opp_table: opp-table-host1x { + compatible =3D "operating-points-v2"; + + opp-144000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <144000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_900>; + }; + + opp-180000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <180000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_900>; + }; + + opp-188000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <188000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_950>; + }; + + opp-228000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <228000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_950>; + }; + + opp-240000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <240000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1000>; + }; + + opp-276000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <276000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1000>; + }; + + opp-276000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <276000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1050>; + }; + + opp-324000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <324000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1100>; + }; + + opp-336000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <336000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1050>; + }; + + opp-336000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <336000000>; + opp-supported-hw =3D <0x0001>; + required-opps =3D <&core_opp_1120>; + }; + + opp-372000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <372000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1100>; + }; + + opp-384000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <384000000>; + opp-supported-hw =3D <0x000E>; + required-opps =3D <&core_opp_1120>; + }; + }; + + pll_m_dvfs_opp_table: opp-table-pllm { + compatible =3D "operating-points-v2"; + + opp-800000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <800000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-1066000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <1066000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1000>; + }; + }; + + pll_c_dvfs_opp_table: opp-table-pllc { + compatible =3D "operating-points-v2"; + + opp-800000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <800000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-1066000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <1066000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1000>; + }; + }; + + pll_c2_dvfs_opp_table: opp-table-pllc2 { + compatible =3D "operating-points-v2"; + + opp-800000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <800000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-1066000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <1066000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1000>; + }; + }; + + pll_c3_dvfs_opp_table: opp-table-pllc3 { + compatible =3D "operating-points-v2"; + + opp-800000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <800000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-1066000000-1000 { + opp-microvolt =3D <1000000 1000000 1390000>; + opp-hz =3D /bits/ 64 <1066000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1000>; + }; + }; + + sbc1_dvfs_opp_table: opp-table-sbc1 { + compatible =3D "operating-points-v2"; + + opp-48000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <48000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-52000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <52000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1100>; + }; + }; + + sbc2_dvfs_opp_table: opp-table-sbc2 { + compatible =3D "operating-points-v2"; + + opp-48000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <48000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-52000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <52000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1100>; + }; + }; + + sbc3_dvfs_opp_table: opp-table-sbc3 { + compatible =3D "operating-points-v2"; + + opp-48000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <48000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-52000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <52000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1100>; + }; + }; + + sbc4_dvfs_opp_table: opp-table-sbc4 { + compatible =3D "operating-points-v2"; + + opp-48000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <48000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-52000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <52000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1100>; + }; + }; + + sbc5_dvfs_opp_table: opp-table-sbc5 { + compatible =3D "operating-points-v2"; + + opp-48000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <48000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-52000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <52000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1100>; + }; + }; + + sbc6_dvfs_opp_table: opp-table-sbc6 { + compatible =3D "operating-points-v2"; + + opp-48000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <48000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-52000000-1100 { + opp-microvolt =3D <1100000 1100000 1390000>; + opp-hz =3D /bits/ 64 <52000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1100>; + }; + }; + + sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { + compatible =3D "operating-points-v2"; + + opp-81600000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <81600000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_950>; + }; + + opp-156000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <156000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1120>; + }; + + opp-204000000-1250 { + opp-microvolt =3D <1250000 1250000 1390000>; + opp-hz =3D /bits/ 64 <204000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1250>; + }; + }; + + sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { + compatible =3D "operating-points-v2"; + + opp-81600000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <81600000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_950>; + }; + + opp-156000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <156000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1120>; + }; + + opp-204000000-1250 { + opp-microvolt =3D <1250000 1250000 1390000>; + opp-hz =3D /bits/ 64 <204000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1250>; + }; + }; + + sdmmc4_dvfs_opp_table: opp-table-sdmmc4 { + compatible =3D "operating-points-v2"; + + opp-81600000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <81600000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_950>; + }; + + opp-156000000-1120 { + opp-microvolt =3D <1120000 1120000 1390000>; + opp-hz =3D /bits/ 64 <156000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1120>; + }; + + opp-200000000-1250 { + opp-microvolt =3D <1250000 1250000 1390000>; + opp-hz =3D /bits/ 64 <200000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1250>; + }; + }; + + hdmi_dvfs_opp_table: opp-table-hdmi { + compatible =3D "operating-points-v2"; + + opp-148500000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <148500000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-297000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <297000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1050>; + }; + }; + + disp1_dvfs_opp_table: opp-table-disp1 { + compatible =3D "operating-points-v2"; + + opp-166000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <166000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-297000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <297000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1050>; + }; + }; + + disp2_dvfs_opp_table: opp-table-disp2 { + compatible =3D "operating-points-v2"; + + opp-166000000-900 { + opp-microvolt =3D <900000 900000 1390000>; + opp-hz =3D /bits/ 64 <166000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_900>; + }; + + opp-297000000-1050 { + opp-microvolt =3D <1050000 1050000 1390000>; + opp-hz =3D /bits/ 64 <297000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_1050>; + }; + }; + + xusb_falcon_dvfs_opp_table: opp-table-xusb-falcon { + compatible =3D "operating-points-v2"; + + opp-336000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <336000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_950>; + }; + }; + + xusb_host_dvfs_opp_table: opp-table-xusb-host { + compatible =3D "operating-points-v2"; + + opp-112000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <112000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_950>; + }; + }; + + xusb_dev_dvfs_opp_table: opp-table-xusb-dev { + compatible =3D "operating-points-v2"; + + opp-58300000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <58300000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_950>; + }; + }; + + xusb_ss_dvfs_opp_table: opp-table-xusb-ss { + compatible =3D "operating-points-v2"; + + opp-122400000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <122400000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_950>; + }; + }; + + xusb_fs_dvfs_opp_table: opp-table-xusb-fs { + compatible =3D "operating-points-v2"; + + opp-48000000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <48000000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_950>; + }; + }; + + xusb_hs_dvfs_opp_table: opp-table-xusb-hs { + compatible =3D "operating-points-v2"; + + opp-61200000-950 { + opp-microvolt =3D <950000 950000 1390000>; + opp-hz =3D /bits/ 64 <61200000>; + opp-supported-hw =3D <0x000F>; + required-opps =3D <&core_opp_950>; + }; + }; + + /* Add usbd, usb2 and usb3 opps if needed */ }; diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvi= dia/tegra114.dtsi index f1af206f50ee..143aa45a9791 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -58,6 +58,8 @@ vi@54080000 { clocks =3D <&tegra_car TEGRA114_CLK_VI>; resets =3D <&tegra_car 20>; reset-names =3D "vi"; + power-domains =3D <&pd_venc>; + operating-points-v2 =3D <&vi_dvfs_opp_table>; =20 iommus =3D <&mc TEGRA_SWGROUP_VI>; =20 @@ -71,6 +73,8 @@ epp@540c0000 { clocks =3D <&tegra_car TEGRA114_CLK_EPP>; resets =3D <&tegra_car TEGRA114_CLK_EPP>; reset-names =3D "epp"; + power-domains =3D <&pd_heg>; + operating-points-v2 =3D <&epp_dvfs_opp_table>; =20 iommus =3D <&mc TEGRA_SWGROUP_EPP>; =20 @@ -84,6 +88,7 @@ isp@54100000 { clocks =3D <&tegra_car TEGRA114_CLK_ISP>; resets =3D <&tegra_car TEGRA114_CLK_ISP>; reset-names =3D "isp"; + power-domains =3D <&pd_venc>; =20 iommus =3D <&mc TEGRA_SWGROUP_ISP>; =20 @@ -97,6 +102,8 @@ gr2d@54140000 { clocks =3D <&tegra_car TEGRA114_CLK_GR2D>; resets =3D <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; reset-names =3D "2d", "mc"; + power-domains =3D <&pd_heg>; + operating-points-v2 =3D <&gr2d_dvfs_opp_table>; =20 iommus =3D <&mc TEGRA_SWGROUP_G2>; }; @@ -107,6 +114,8 @@ gr3d@54180000 { clocks =3D <&tegra_car TEGRA114_CLK_GR3D>; resets =3D <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; reset-names =3D "3d", "mc"; + power-domains =3D <&pd_3d>; + operating-points-v2 =3D <&gr3d_dvfs_opp_table>; =20 iommus =3D <&mc TEGRA_SWGROUP_NV>; }; @@ -120,6 +129,8 @@ dc@54200000 { clock-names =3D "dc", "parent"; resets =3D <&tegra_car 27>; reset-names =3D "dc"; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&disp1_dvfs_opp_table>; =20 iommus =3D <&mc TEGRA_SWGROUP_DC>; =20 @@ -150,6 +161,8 @@ dc@54240000 { clock-names =3D "dc", "parent"; resets =3D <&tegra_car 26>; reset-names =3D "dc"; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&disp2_dvfs_opp_table>; =20 iommus =3D <&mc TEGRA_SWGROUP_DCB>; =20 @@ -180,6 +193,8 @@ hdmi@54280000 { clock-names =3D "hdmi", "parent"; resets =3D <&tegra_car 51>; reset-names =3D "hdmi"; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&hdmi_dvfs_opp_table>; status =3D "disabled"; }; =20 @@ -193,6 +208,7 @@ dsia: dsi@54300000 { resets =3D <&tegra_car 48>; reset-names =3D "dsi"; nvidia,mipi-calibrate =3D <&mipi 0x060>; /* DSIA & DSIB pads */ + power-domains =3D <&pd_core>; status =3D "disabled"; =20 #address-cells =3D <1>; @@ -209,6 +225,7 @@ dsib: dsi@54400000 { resets =3D <&tegra_car 82>; reset-names =3D "dsi"; nvidia,mipi-calibrate =3D <&mipi 0x180>; /* DSIC & DSID pads */ + power-domains =3D <&pd_core>; status =3D "disabled"; =20 #address-cells =3D <1>; @@ -222,6 +239,8 @@ msenc@544c0000 { clocks =3D <&tegra_car TEGRA114_CLK_MSENC>; resets =3D <&tegra_car TEGRA114_CLK_MSENC>; reset-names =3D "mpe"; + power-domains =3D <&pd_mpe>; + operating-points-v2 =3D <&msenc_dvfs_opp_table>; =20 iommus =3D <&mc TEGRA_SWGROUP_MSENC>; =20 @@ -234,6 +253,8 @@ tsec@54500000 { interrupts =3D ; clocks =3D <&tegra_car TEGRA114_CLK_TSEC>; resets =3D <&tegra_car TEGRA114_CLK_TSEC>; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&tsec_dvfs_opp_table>; =20 iommus =3D <&mc TEGRA_SWGROUP_TSEC>; =20 @@ -393,6 +414,8 @@ vde@6001a000 { reset-names =3D "vde", "mc"; resets =3D <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; iommus =3D <&mc TEGRA_SWGROUP_VDE>; + power-domains =3D <&pd_vde>; + operating-points-v2 =3D <&vde_dvfs_opp_table>; }; =20 apbmisc@70000800 { @@ -470,6 +493,7 @@ pwm: pwm@7000a000 { clocks =3D <&tegra_car TEGRA114_CLK_PWM>; resets =3D <&tegra_car 17>; reset-names =3D "pwm"; + power-domains =3D <&pd_core>; status =3D "disabled"; }; =20 @@ -560,6 +584,8 @@ spi@7000d400 { reset-names =3D "spi"; dmas =3D <&apbdma 15>, <&apbdma 15>; dma-names =3D "rx", "tx"; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&sbc1_dvfs_opp_table>; status =3D "disabled"; }; =20 @@ -575,6 +601,8 @@ spi@7000d600 { reset-names =3D "spi"; dmas =3D <&apbdma 16>, <&apbdma 16>; dma-names =3D "rx", "tx"; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&sbc2_dvfs_opp_table>; status =3D "disabled"; }; =20 @@ -590,6 +618,8 @@ spi@7000d800 { reset-names =3D "spi"; dmas =3D <&apbdma 17>, <&apbdma 17>; dma-names =3D "rx", "tx"; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&sbc3_dvfs_opp_table>; status =3D "disabled"; }; =20 @@ -605,6 +635,8 @@ spi@7000da00 { reset-names =3D "spi"; dmas =3D <&apbdma 18>, <&apbdma 18>; dma-names =3D "rx", "tx"; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&sbc4_dvfs_opp_table>; status =3D "disabled"; }; =20 @@ -620,6 +652,8 @@ spi@7000dc00 { reset-names =3D "spi"; dmas =3D <&apbdma 27>, <&apbdma 27>; dma-names =3D "rx", "tx"; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&sbc5_dvfs_opp_table>; status =3D "disabled"; }; =20 @@ -635,6 +669,8 @@ spi@7000de00 { reset-names =3D "spi"; dmas =3D <&apbdma 28>, <&apbdma 28>; dma-names =3D "rx", "tx"; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&sbc6_dvfs_opp_table>; status =3D "disabled"; }; =20 @@ -661,6 +697,86 @@ tegra_pmc: pmc@7000e400 { clocks =3D <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; clock-names =3D "pclk", "clk32k_in"; #clock-cells =3D <1>; + + pd_core: core-domain { + #power-domain-cells =3D <0>; + operating-points-v2 =3D <&core_opp_table>; + }; + + powergates { + /* + * TODO: Add DIS and DISB domains once DC is able + * to handle them properly. VENC and DISB should + * set DIS as their source power domain due to + * internal dependency. + */ + + pd_heg: heg { + clocks =3D <&tegra_car TEGRA114_CLK_GR2D>, + <&tegra_car TEGRA114_CLK_EPP>; + resets =3D <&mc TEGRA114_MC_RESET_2D>, + <&mc TEGRA114_MC_RESET_EPP>, + <&tegra_car TEGRA114_CLK_GR2D>, + <&tegra_car TEGRA114_CLK_EPP>; + power-domains =3D <&pd_core>; + #power-domain-cells =3D <0>; + }; + + pd_mpe: mpe { + clocks =3D <&tegra_car TEGRA114_CLK_MSENC>; + resets =3D <&mc TEGRA114_MC_RESET_MPE>, + <&tegra_car TEGRA114_CLK_MSENC>; + power-domains =3D <&pd_core>; + #power-domain-cells =3D <0>; + }; + + pd_3d: td { + clocks =3D <&tegra_car TEGRA114_CLK_GR3D>; + resets =3D <&mc TEGRA114_MC_RESET_3D>, + <&tegra_car TEGRA114_CLK_GR3D>; + power-domains =3D <&pd_core>; + #power-domain-cells =3D <0>; + }; + + pd_vde: vdec { + clocks =3D <&tegra_car TEGRA114_CLK_VDE>; + resets =3D <&mc TEGRA114_MC_RESET_VDE>, + <&tegra_car TEGRA114_CLK_VDE>; + power-domains =3D <&pd_core>; + #power-domain-cells =3D <0>; + }; + + pd_venc: venc { + clocks =3D <&tegra_car TEGRA114_CLK_ISP>, + <&tegra_car TEGRA114_CLK_VI>, + <&tegra_car TEGRA114_CLK_CSI>; + resets =3D <&mc TEGRA114_MC_RESET_ISP>, + <&mc TEGRA114_MC_RESET_VI>, + <&tegra_car TEGRA114_CLK_ISP>, + <&tegra_car 20 /* VI */>, + <&tegra_car TEGRA114_CLK_CSI>; + power-domains =3D <&pd_core>; + #power-domain-cells =3D <0>; + }; + + pd_xusbss: xusba { + clocks =3D <&tegra_car TEGRA114_CLK_XUSB_SS>; + resets =3D <&tegra_car TEGRA114_CLK_XUSB_SS>; + #power-domain-cells =3D <0>; + }; + + pd_xusbdev: xusbb { + clocks =3D <&tegra_car TEGRA114_CLK_XUSB_DEV>; + resets =3D <&tegra_car 95>; + #power-domain-cells =3D <0>; + }; + + pd_xusbhost: xusbc { + clocks =3D <&tegra_car TEGRA114_CLK_XUSB_HOST>; + resets =3D <&tegra_car TEGRA114_CLK_XUSB_HOST>; + #power-domain-cells =3D <0>; + }; + }; }; =20 fuse@7000f800 { @@ -670,6 +786,7 @@ fuse@7000f800 { clock-names =3D "fuse"; resets =3D <&tegra_car 39>; reset-names =3D "fuse"; + power-domains =3D <&pd_core>; }; =20 mc: memory-controller@70019000 { @@ -691,6 +808,7 @@ emc: external-memory-controller@7001b000 { interrupts =3D ; clocks =3D <&tegra_car TEGRA114_CLK_EMC>; clock-names =3D "emc"; + power-domains =3D <&pd_core>; =20 nvidia,memory-controller =3D <&mc>; operating-points-v2 =3D <&emc_icc_dvfs_opp_table>; @@ -885,6 +1003,8 @@ mmc@78000000 { clock-names =3D "sdhci"; resets =3D <&tegra_car 14>; reset-names =3D "sdhci"; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&sdmmc1_dvfs_opp_table>; status =3D "disabled"; }; =20 @@ -907,6 +1027,8 @@ mmc@78000400 { clock-names =3D "sdhci"; resets =3D <&tegra_car 69>; reset-names =3D "sdhci"; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&sdmmc3_dvfs_opp_table>; status =3D "disabled"; }; =20 @@ -918,6 +1040,8 @@ mmc@78000600 { clock-names =3D "sdhci"; resets =3D <&tegra_car 15>; reset-names =3D "sdhci"; + power-domains =3D <&pd_core>; + operating-points-v2 =3D <&sdmmc4_dvfs_opp_table>; status =3D "disabled"; }; =20 @@ -930,6 +1054,7 @@ usb@7d000000 { resets =3D <&tegra_car 22>; reset-names =3D "usb"; nvidia,phy =3D <&phy1>; + power-domains =3D <&pd_core>; status =3D "disabled"; }; =20 @@ -970,6 +1095,7 @@ usb@7d008000 { resets =3D <&tegra_car 59>; reset-names =3D "usb"; nvidia,phy =3D <&phy3>; + power-domains =3D <&pd_core>; status =3D "disabled"; }; =20 --=20 2.51.0